51results about "Reliability increasing modifications" patented technology

The present application relates to the technical field of optical coupling, and particularly relates to a constant current optical coupling isolation circuit based on a depletion mode MOSFET; through the cooperation of a reverse protection module, a self-bias constant current module and a response enhancement module, super-wide voltage input, low power consumption and high-speed dynamic response are realized in the circuit, to a certain extent, the inherent technical contradiction that the traditional resistance current limiting scheme cannot simultaneously consider reliable conduction and low power consumption under wide voltage, and the slow response of high CTR optical coupling is solved, the structure is extremely simple and the reliability is high, a self-bias constant current source based on a depletion mode MOSFET is adopted, only one resistor is needed to realize relatively accurate constant current output in a super-wide input range of 9.6V to 400V, replacing the current limiting resistor with huge power consumption under high voltage or the active constant current source with complex circuit in the traditional scheme, and the power consumption under high voltage application is reduced; the technical problem that the existing resistance current limiting scheme is limited in widening the input voltage range of the optical coupling is solved.

The application discloses a CAN transceiver circuit, which comprises a logic and timing module, a current mirror driving group and a resistance driver group; the input end of the logic and timing module is connected with a TXD signal, and the output end outputs a plurality of groups of driving signals, each group of the driving signals controls a current mirror driving group or a resistance driver group; the current mirror driving group and the resistance driver group are used for driving a CANH port and a CANL port, wherein a single CANH port or a single CANL port is provided with upper and lower current mirror driving groups and upper and lower resistance driver groups; the upper current mirror driving group is connected with the upper resistance driver group in parallel, and the lower current mirror driving group is connected with the lower resistance driver group in parallel. The application realizes the bit width consistency improvement and the adaptive baud rate through the independent impedance control of the current mirror pull structure and the differential port, and the process of adjusting the port impedance does not affect the bit width consistency.

The present disclosure relates to a level shifter for shifting a voltage signal from a first voltage domain to a second voltage domain, the level shifter comprising: an input circuit configured to receive a voltage signal in the first voltage domain, an output circuit configured to output a voltage signal in the second voltage domain, and a protection circuit configured to prevent a reverse current flow between the input circuit and the output circuit.

Herein presented are systems and methods for majority-vote, single fault tolerant switching of a switch using an electrical circuit that involves power transistors that carry relatively large electrical currents through the switch. The number of power transistors in the circuit of a majority-vote, single fault tolerant power switch may be reduced to four, thus saving circuit board space and producing relatively less heat. This may be done by avoiding the use of a third electrical branch that is generally used for triple module redundant power switches. In cases where a power transistor is relatively large and produces a relatively large amount of heat, reducing the number of this type of circuit component in a switch circuit may provide benefits such as reduced circuit board footprint and reduced heat generation.

This invention provides a digital isolator with feedback capability and its application circuit. The first isolation circuit of the digital isolator includes a first coupler, a first matching network, a first transmitter, an envelope detector, and a decoder; the second isolation circuit includes a second coupler, a second matching network, a second transmitter, a second receiver, and an encoder. The envelope detector is connected to the first isolated circuit through the decoder; the first transmitter and the envelope detector are respectively connected to the first matching network; the first matching network is connected to the first coupler; the first coupler is coupled to the second coupler; the second coupler is connected to the second matching network; the second receiver and the second transmitter are respectively connected to the second matching network; the second transmitter is connected to the second isolated circuit through the encoder. This invention enables the feedback of various types of abnormal signals from the second isolation circuit to the first isolation circuit using only a single channel composed of a single pair of couplers.

Disclosed in the present invention are a low-voltage differential signaling device and a low-voltage differential signaling driver. An output circuit of the low-voltage differential signaling driver comprises a first current source and a differential push-pull output circuit, wherein the first current source is connected between a power source end and the differential push-pull output circuit, and the differential push-pull output circuit is connected to a differential output end of the low-voltage differential signaling driver, and is used for generating a first output voltage and a second output voltage on the basis of a first input signal and a second input signal. A turn-off circuit of the low-voltage differential signaling driver is connected to the differential output end of the low-voltage differential signaling driver and is used for turning off the first current source by using a short-circuited power source on the differential output end when the low-voltage differential signaling driver is in a leakage protection state. A first end of a substrate clamping circuit of the low-voltage differential signaling driver is connected to the power source end, and a second end thereof provides a substrate potential to a MOS transistor in the first current source. When the low-voltage differential signaling driver is in the leakage protection state, the substrate clamping circuit is in an off-state in the direction from the second end to the first end, such that effective leakage protection can still be performed on the low-voltage differential signaling driver when the low-voltage differential signaling driver is in a power-off state.

The utility model relates to interface circuit technical field, concretely relates to an interface circuit with protection function, including connector J1, connector J2, thyristor Q2, resistance R2, resistance R4 and stabilivolt diode VT2, the anode of thyristor Q2 is connected with connector J1 and connector J2 respectively, the cathode of thyristor Q2 is grounded, the grid of thyristor Q2 is connected with one end of resistance R2, the other end of resistance R2 is grounded through resistance R4, the other end of resistance R2 is connected with the anode of stabilivolt diode VT2, the cathode of stabilivolt diode VT2 is connected with the anode of thyristor Q2, the utility model discloses that the overvoltage trigger loop that stabilivolt diode VT2 and thyristor Q2 constitute, realize overvoltage threshold accurate control, when overvoltage, thyristor Q2 fast conduction, bypass and form big current loop to load, instantaneous fuse F1, cut off power supply thoroughly, avoid continuous overvoltage damage load.

An electronic device includes a logic gate coupled to a first node of application of a reference voltage, a random voltage generator configured to generate a random voltage at a second node, and a first diode having a cathode coupled to the second node and an anode coupled to the first node.

This invention discloses a level shifting structure for an ultra-large area array ultra-low temperature infrared image sensor, comprising a conversion signal input transistor; a level clamping transistor whose gate receives a level VREF, and whose source is connected to the source of a feedback transistor, the gate of an inverting N-transistor, and the gate of an inverting P-transistor; the drain of the level clamping transistor connected to the source of the conversion signal input transistor; the drain of the conversion signal input transistor grounded; the gate of the conversion signal input transistor connected to IP; the drain of the feedback transistor connected to the source of a pull-up transistor, whose gate is connected to IP, and whose drain is connected to power supply VDD; the source of the inverting P-transistor connected to power supply VDD, whose drain is connected to the source of the inverting N-transistor, and whose drain is grounded; and a level VREF generated by a level VREF clamping matching voltage generation circuit. This ensures that the source-drain voltage of the conversion signal input transistor (low threshold transistor) does not exceed 1.2V, ensuring that the device operates within its normal voltage range and avoiding the risk of breakdown.

The application discloses a kind of anti-radiation reinforcement circuits based on TMR, including input unit, latching unit and two-out-of-three voting unit, input unit is for the input signal IN being divided into three paths respectively to reverse processing, output three reverse signals;Latching unit is for one of reverse signal is latched and is handled, and two other reverse signals are handled using double interlocking structure, output three latching signals;Two-out-of-three voting unit is for selecting the same two or three signals from three latching signals as voting result, obtains reinforcement output signal.In the application, latching unit is handled using conventional latching structure and double interlocking structure respectively, output three latching signals, the effect of anti-radiation reinforcement is good, and circuit structure is simple, occupies small area, and reduce power consumption.

An input circuit includes an input buffer, a first voltage conversion circuit, a second voltage conversion circuit, and a third voltage conversion circuit. The input buffer includes: first and second transistors serially connected between a first power supply and an output terminal; and third and fourth transistors serially connected between a second power supply and the output terminal. The first voltage conversion circuit is provided between an input terminal and a second node connected to the gate of the first transistor. The second voltage conversion circuit is provided between the input terminal and a fifth node connected to the gate of the third transistor. The third voltage conversion circuit is provided between the second node and a third node connected to the gates of the second transistor and the fourth transistor.

This semiconductor device includes: a gate voltage control circuit that applies on-bias and off-bias to a gate terminal of a power semiconductor element in accordance with a first drive signal; and an off-bias voltage control circuit that changes a voltage level of the off-bias in accordance with the first drive signal and a second drive signal and controls an application period of the changed off-bias.

This invention discloses a high-speed zero-current level conversion circuit suitable for a wide voltage range, comprising a low-voltage to high-voltage circuit and a high-voltage to low-voltage circuit. The low-voltage to high-voltage circuit includes a high-voltage level shifting module, a high-voltage level converter, and a high-voltage latching module. The high-voltage to low-voltage circuit includes a low-voltage level shifting module, a low-voltage level converter, and a low-voltage latching module. This invention adapts to both high-voltage and low-voltage operation with zero quiescent current and exhibits low transmission delay.

The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.

Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.

Systems and methods for monitoring a plurality of operating conditions of a programmable device are disclosed. In some embodiments, the system can include a root monitor including circuitry configured to generate a reference voltage; a plurality of sensors and satellite monitors distributed across the programmable device; and an interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each satellite monitor can be proximate a respective one of the plurality of sensors and coupled to the respective one of the plurality of sensors via a local interconnect. The interconnect system can include one or more analog channels configured to distribute the reference voltage to each of the plurality of satellite monitors and can include one or more digital channels configured to selectively route digital data from each of the plurality of satellite monitors as data packets to the root monitor.

Methods, systems, and apparatus for producing CCZ states and T states. In one aspect, a method for transforming a CCZ state into three T states includes obtaining a first target qubit, a second target qubit and a third target qubit in a CCZ state; performing a X−1 / 2 gate on the third target qubit; performing an X gate on the first target qubit and the second target qubit using the third target qubit as a control; performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control; performing a Z−1 / 4 gate on the third target qubit; and performing a Z gate on the first target qubit and the second target qubit using the third qubit as a X axis control to obtain the three T states.

The application relates to a circuit for preventing high-voltage external connection of a transmitter output. The circuit comprises a first input end of the circuit for connecting a first output end of an input structure, a second input end of the circuit for connecting a second output end of the input structure, a third input end of the circuit for connecting a first end of a transmitter output structure, a first output end of the circuit for connecting a second end of the transmitter output structure, and a second output end of the circuit for connecting a third end of the transmitter output structure. The circuit can feed back a high-voltage external connection control signal to the transmitter output structure to protect the transmitter.

Latch circuit, which includes: a first inverter coupled to a supply voltage and a cancel terminal (CANCEL terminal), wherein the first inverter has a first resistive load (R0); and a second inverter which is cross-coupled with the first inverter and coupled to the supply voltage terminal (VPOS) and an adjustment terminal (SET), wherein the second inverter includes a second resistive load (R3), wherein the first and second resistive loads cause the latch circuit to automatically set or reset in response to a change in the supply voltage, and wherein at least one of the first or second resistive loads is set up to set a threshold voltage at which the latch circuit is automatically set or reset.

The application discloses an output driving circuit, which comprises an input unit, a multi-stage output unit, a load unit, a feedback network, a bias network and a balance network; the input unit, the multi-stage output unit and the load unit are connected in sequence, the feedback network is connected with the output of the multi-stage output unit, the bias network is connected with the input unit and the multi-stage output unit, and the balance network is connected with the multi-stage output unit. The output driving circuit has the advantages of large output swing, high output bandwidth and good reliability.

A level shift assembly, a method for over-current protection, and a display apparatus. The level shift assembly includes a level shift module, which includes a control unit, a current detection unit, a level shift unit, and an over-current protection unit. The controller determines, at a first falling edge of a digital clock signal, a first analog clock signal among a plurality of analog clock signals which corresponds to the first falling edge based on a correspondence of a current display mode; the current detection unit detects a current of the first analog clock signal; and a moment, at which a falling edge of the digital clock signal is present, is within a last line of a corresponding analog clock signal, and an over-current signal is sent to the over-current protection unit when the current of the first analog clock signal is not within a current threshold range.

Circuit (100A, 100B, 100C, 100D, 100E), comprising: a transistor sub-circuit (106) with several detection nodes and a gate node; a point detector (104) with multiple inputs coupled to the multiple detection nodes of the transistor sub-circuit (106), and one output; and a control circuit (102) with a gate control node, which is coupled to the gate node of the transistor sub-circuit (106), and an overcurrent protection node which is coupled to the output of the peak detector (104), wherein the tip detector (104) comprises several diodes (D1-D4), each diode of the several diodes (D1-D4) having an anode coupled to one of the several inputs of the tip detector (104) and a cathode coupled to the output of the tip detector (104).

The application provides an analog input conversion system and method, and belongs to the electrical and electronic technical field.The system comprises a single-chip microcomputer, a charging circuit for receiving an analog signal and charging by using the analog signal, and a time base circuit for receiving a pulse signal from the single-chip microcomputer, controlling an output end of the time base circuit to output a first level according to the pulse signal, and controlling the charging circuit to charge by using the received analog signal, wherein the output end of the time base circuit outputs a second level when the charged quantity reaches a predetermined size, and the single-chip microcomputer determines the size of the analog signal according to the time required for the output end of the time base circuit to change from the first level to the second level.The application converts the analog signal into a time signal, calculates the size of the analog signal through the time signal, realizes higher precision and more accurate photoelectric isolation, and improves the anti-interference ability in the analog signal transmission process.

This invention belongs to the field of analog integrated circuit technology, specifically relating to an edge modulation and demodulation circuit for optically isolated transmission. It includes an SOI substrate, a waveguide layer, and a cladding layer. The SOI substrate comprises a substrate layer and a buried oxide layer. The waveguide layer comprises a lower silicon waveguide, a middle silicon dioxide spacer layer, and an upper silicon nitride waveguide. The upper silicon nitride waveguide modulates the width of the etched regions and the grating duty cycle on both sides of the central silicon nitride waveguide according to the near-field uniform emission principle, forming a fishbone-like grating antenna structure. The proposed double-layer grating structure utilizes the strong optical confinement of silicon waveguides and the weak perturbation characteristics of silicon nitride waveguides through full etching, reducing etching difficulty, effectively extending the effective length of the grating, thereby reducing the far-field emission angle of the beam, and exhibiting high wavelength tuning efficiency and high upward diffraction efficiency. The structure is simple and relatively easy to fabricate.

The application provides a communication circuit, a semiconductor integrated circuit, a system on chip and an electronic device, which are applied to the technical field of computers, and the circuit comprises a first selection circuit and a second selection circuit. The first selection circuit is connected with a first end of a signal TSV and a redundant TSV respectively, the second selection circuit is connected with a second end of the signal TSV and the redundant TSV respectively, the first selection circuit and the second selection circuit transmit a configuration signal for switching a communication signal transmission path through the signal TSV, in the case that the signal TSV is normal, the first selection circuit and the second selection circuit transmit a communication signal through the signal TSV, in the case that the signal TSV is abnormal, the first selection circuit and the second selection circuit transmit a communication signal through the redundant TSV, the circuit can realize self-detection of the state of the signal TSV, switch the signal TSV and the redundant TSV automatically, can omit a feedback TSV, and effectively reduces TSV cost.

This application relates to the field of power electronics technology and discloses a drive holding circuit, electronic device, and vehicle. The drive holding circuit includes a first circuit and a second circuit. The first circuit is adapted to receive a power supply signal and a control signal, and to conduct when the control signal switches from invalid to valid, thereby generating a drive signal based on the power supply signal and latching the drive signal to keep it valid. The second circuit is adapted to receive the drive signal and a safety logic signal, and to release the latch of the drive signal when the control signal and the safety logic signal meet preset conditions, causing the drive signal to fail. This application can maintain a valid drive state even when a drive signal source failure occurs, thereby effectively avoiding the impact of a single fault on the function of the electronic device and significantly improving system reliability.

The utility model discloses a kind of redundant logic gate cascade circuit based on dynamic threshold and path cooperation, the circuit includes: adaptive control module includes clock signal input end, reset signal input end, noise sensing signal input end, detection enable signal input end, high noise threshold input end, low noise threshold input end, threshold selection signal output end and redundant path enable signal output end;Redundant logic gate array module includes the redundant path enable signal input end of being connected with redundant path enable signal output end one-to-one correspondence, redundant logic gate unit input end and redundant logic gate array output end;Multiple voter module includes the threshold selection signal input end being connected with threshold selection signal output end, the redundant logic gate output signal input end being connected with redundant logic gate array output end one-to-one correspondence and voting signal output end.The utility model can improve the anti-interference ability of circuit, to dynamically adapt different noise level, reduce resource waste.

This invention discloses a single-particle radiation hardening CMOS pseudo-resistor circuit, comprising: an adjustable CMOS pseudo-resistor circuit for generating an adjustable CMOS pseudo-resistor; wherein the adjustable CMOS pseudo-resistor circuit has a radiation-sensitive node located between the drain of a first transistor and the drain of a second transistor, the first transistor generating a current injected into the radiation-sensitive node, and the second transistor generating a current drawn from the radiation-sensitive node; a first balancing current mirror circuit for generating a discharge current when a single particle irradiates the drain of the first transistor, discharging the discharge current injected into the radiation-sensitive node to ground, thereby hardening the radiation-sensitive node; and a second balancing current mirror circuit for generating a compensation current when a single particle irradiates the drain of the second transistor, injecting the compensation current into the radiation-sensitive node, thereby hardening the radiation-sensitive node.