968results about "Reliability increasing modifications" patented technology

An output driver includes a pull-up transistor having a first current path coupled between a supply voltage and an output node; a pull-down transistor having a second current path coupled between the output node and a reference ground; the gate driving circuit is used for driving the control end of the pull-up transistor according to the first control signal and driving the control end of the pull-down transistor according to the second control signal; the logic control circuit is used for generating a first control signal and a second control signal according to an input signal and an enable control signal; and the current source circuit is used for respectively providing pull-down or pull-up current related to the power supply voltage to the control end of the pull-up transistor or the pull-down transistor when the output signal at the output node is in a rising edge or falling edge process, so as to counteract the influence of the power supply voltage on the transmission time of the output signal. Therefore, stable transmission time can be maintained in a wide power supply voltage range.

The utility model provides an insulated gate bipolar transistor driving circuit with adjustable positive and negative voltages, comprising a magnetic isolation module, the input end of which is connected with a driving signal and outputs an isolation driving signal; the input end of the first voltage regulating module is connected with the first positive voltage and outputs a second positive voltage within a first preset range; the input end of the second voltage regulating module is connected with the first negative voltage and outputs a second negative voltage within a second preset range; the push-pull output module is connected between the second positive voltage and the second negative voltage, the control end of the push-pull output module is connected with an isolation driving signal, and the output end of the push-pull output module is connected with the gate pole of the to-be-tested insulated gate bipolar transistor through a gate resistor; and the protection module is controllably connected between the output end of the push-pull output module and the second voltage regulation module under the action of the control signal. The driving circuit has the beneficial effects that the positive and negative voltage output capability can be flexibly adjusted according to debugging requirements, the working condition requirements of different clients are met, and the flexibility and adaptability of the driving circuit are improved.

A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

The invention discloses a wide input voltage range current-limiting protection circuit suitable for a load switch. The wide input voltage range current-limiting protection circuit comprises a power tube MN1, a sampling tube MN3, a sampling resistor Rsense, a power switching module, a sampling module, an error amplifier EA, a resistor Rload and a capacitor Cload. The whole loop can achieve the current-limiting protection function within the power supply voltage range of 0.5-5.5 V, and the current-limiting protection function can also be achieved when the output is as low as 0V. Different from a current-limiting protection circuit in a traditional load switch, the current-limiting protection circuit has the advantages that a sampling loop is formed by sampling the potential of the drain end, and the problem that the loop cannot work normally when the output voltage is too low due to sampling of the potential of the source end is solved; and secondly, a mode of combining a power supply switching module and a rail-to-rail operational amplifier is designed, so that a current-limiting protection function can be realized in a wider input voltage range.

The invention relates to a level control circuit and electric equipment. The level control circuit comprises a level shift circuit, an enable signal processing circuit and a level determination circuit. The level shift circuit is used for receiving a first control signal corresponding to the first voltage domain, converting the first control signal into a second control signal corresponding to the second voltage domain, and outputting the second control signal. The enable signal processing circuit is connected with a first positive power supply end of the first voltage domain and a second positive power supply end of the second voltage domain, and outputs an enable signal on the basis of a second power supply voltage provided by the second positive power supply end under the condition that the first power supply voltage is not connected to the first positive power supply end. And the level determining circuit is connected with the enable signal processing circuit and the output end of the level shifting circuit, and is used for controlling the level of the output end of the level shifting circuit to be in a preset state according to the received enable signal. The level shift circuit is clear in output state and high in output reliability under the condition that the second positive power supply end provides the second power supply voltage.

A level conversion assembly (50), an overcurrent protection method and a display device, the level conversion assembly (50) comprising a level conversion module (51), the level conversion module (51) comprising a control unit (511), a current detection unit (512), a level conversion unit (513) and an overcurrent protection unit (514). When a control unit (511) is at a first falling edge of a digital clock signal (CPV), a first analog clock signal corresponding to the first falling edge in a plurality of analog clock signals (CLK1-CLK8) is determined based on the corresponding relation of the current display mode, and a current detection unit (512) is controlled to detect the current of the first analog clock signal. Since the moment of the falling edge of the digital clock signal (CPV) is located in the last row of the high level period or the low level period in the corresponding analog clock signal, the current detection unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not located in the current threshold range. The effect of improving the accuracy of over-current phenomenon detection is achieved.

The utility model provides a bidirectional anti-backflow circuit, a protection chip and an adapter plate. The bidirectional anti-backflow circuit comprises at least one anti-backflow module, each anti-backflow module comprises two anti-backflow branches with the same circuit structure, and each anti-backflow branch comprises a first control circuit, an isolation circuit, an IO circuit and a second control circuit. Wherein the first end of the first control circuit of one anti-backflow branch is coupled with the first end of the second control circuit of the other anti-backflow branch to form a first IO node, and the first end of the second control circuit of the anti-backflow branch is coupled with the first end of the first control circuit of the other anti-backflow branch to form a second IO node; wherein the control end of the first control circuit and the control end of the second control circuit of one anti-backflow branch are both coupled with a first driving signal, and the control end of the first control circuit and the control end of the second control circuit of the other anti-backflow branch are both coupled with a second driving signal. According to the utility model, bidirectional transmission and isolation protection between chips can be realized with low cost.

The invention provides a bias voltage providing circuit of an avalanche photodiode and a PON gateway, and relates to the technical field of optical communication. The bias voltage providing circuit of the avalanche photodiode comprises a bias voltage input unit, a bias voltage control input processing unit and an avalanche photodiode protection unit. When the illumination intensity of the target avalanche photodiode exceeds the preset illumination intensity, the photo-generated current of the target avalanche photodiode exceeds the preset current, and the avalanche photodiode protection unit responds to the situation that the photo-generated current of the target avalanche photodiode exceeds the preset current. The diode bias voltage applied to the target avalanche photodiode is reduced, so that the photo-generated current of the target avalanche photodiode is reduced, and overload protection of the target avalanche photodiode is completed. Based on the above content, the problem that the target avalanche photodiode is easy to damage due to overload in the prior art can be improved.

The invention provides a high-voltage level shift circuit with an adaptive dead zone. The level shift circuit comprises a level shift module, a dv / dt noise detection module, a bank signal control module and an output module. According to the invention, the problem that dv / dt noise affects output through a signal chain is prevented by using a bank turn-off technology; the Blank time of dv / dt noise with different intensities is adaptively adjusted through the dv / dt noise detection module, so that the limitation on the minimum conduction time of an input signal in the application is solved; a low transmission delay, high dv / dt noise resistance and low minimum input signal conduction time are obtained, and the application requirements of a DCDC system and a driving circuit system are met.

The invention provides a chip and a trimming control circuit and a trimming control method thereof, and the trimming control circuit comprises a trimming position generation unit which latches a trimming mode control signal according to a power-on signal so as to generate a trimming enable signal, and counts received trimming clock signals according to the trimming enable signal and a counting enable signal, a trimming position control signal is correspondingly output in each period of counting the trimming clock signal; and a fuse is connected between each trimming control unit and the power supply end, and whether the fuse is fused or not is controlled according to the trimming mode control signal, the corresponding trimming position control signal and the general control signal. According to the method and the device, wrong trimming caused by writing of wrong trimming codes can be avoided, so that the yield and the manufacturing cost of the chip are improved.

The invention relates to an anti-radiation level conversion circuit. The circuit comprises a level conversion circuit based on a DICE structure and an anti-radiation reinforcement circuit. The level conversion circuit based on the DICE structure is used for realizing level conversion by adopting redundant control nodes; comprising an input module and a DICE module, and the DICE module comprises four branches formed by connecting one PMOS transistor and one NMOS transistor in series; drain electrodes of the PMOS transistor and the NMOS transistor in each branch are connected to serve as a control node; the input module is used for controlling an MOS switch to transmit a differential input signal to the DICE module through a transmission tube; and the anti-radiation reinforcing circuit is used for performing feedback regulation on the control nodes of the second branch and the third branch through the cross coupling structure. The circuit can complete level switching from ultra-low voltage to high voltage, the radiation resistance of the level converter is improved, the level converter can resist severe environments, and meanwhile power consumption and delay are reduced.

The embodiment of the invention provides a bus holding circuit and a bus holder. The bus holding circuit comprises a bus holding module, a configuration module and an anti-backflow module, the bus holding module comprises a pull-up unit and a pull-down unit, the anti-backflow module comprises an input unit and an output unit, the configuration module is used for responding to the voltage of the input end of the bus holding circuit and controlling the pull-up unit or the pull-down unit to be conducted, and the bus holding module is used for locking the voltage state of the input end of the bus holding circuit; the first end of the input unit is connected with the input end of the bus holding circuit, the control end of the input unit is connected with the control end of the output unit, and the output unit is used for mirroring the current of the input unit when the voltage of the input end of the bus holding circuit is greater than a first voltage or the first voltage is powered down. According to the scheme, the applicability of the bus holding circuit to different processes can be expanded.

The invention relates to a redundant feedback latch multilevel anti-single-particle reinforced trigger of a FinFET (FinFET) process, which comprises a data input structure, a clock input structure, four clock control structures, a delay structure, a data master latch structure, a data slave latch structure and a data output structure, the trigger latches data for both the data master latch structure and the data slave latch structure by using a redundancy feedback circuit, and delays one path of data by using a delay structure to filter external single-particle transient pulses at a data end; through a redundancy feedback latch structure and a delay unit, the circuit realizes multi-dimensional reinforcement of single-particle unit / multi-bit upset and single-particle transient, and the single-particle radiation reinforcement resistance of the trigger is significantly improved. In addition, a design reinforcing method combining a circuit and a layout is preferably adopted, the number of Fins in unit grid spacing is designed to be the maximum, an interdigital structure is used for devices at sensitive nodes, meanwhile, the sensitive nodes are arranged in an isolated mode, and the single-particle multi-bit upset resisting capacity is further enhanced.

Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. One device involves: a circuital arrangement (200A) comprising an integrated circuit, IC, the IC comprising: a shunt switch (T1); a decoupling capacitance (Cd) connecting a source terminal of the switch to a first pin (P1) of the IC; wherein the circuital arrangement further comprises: a storage capacitance (Cs) disposed outside the IC and coupled to the first pin of the IC; a resonance-canceling inductance (L2) disposed outside the IC and in series with the storage capacitance; wherein: the storage capacitance acts as an alternating current, AC, -short circuit across an operational frequency band of the IC; the resonance-canceling inductance is configured to cancel or attenuate a parasitic resonance, by a combination of i) a series arrangement of a parasitic ground inductance (L_IC) inside the IC and a parasitic ground inductance (L_PCB) outside the IC with ii) a parallel arrangement of the decoupling capacitance (Cd) and a parasitic capacitance (Cp), the parasitic resonance to be canceled or reduced occurring at a frequency within an operational frequency band of the circuital arrangement.

The invention discloses a latch, relates to the field of integrated circuit design, and aims to solve the problem that the error rate of circuit output level is relatively high after a plurality of storage nodes of a latch circuit are impacted by particles in the prior art. The latch at least comprises an input module, a clock control module, a storage module and an output module, the first end of an input module is connected with the input end of the latch, and the second end of the input module is connected with the input end of the storage module; the output end of the storage module is connected with the first end of an output module; the second end of the output module is connected with the output end of the latch, and the input end of the clock control module is connected with the clock signal input end; the output end of the clock control module is respectively connected with the input module and the output module; the latch is used for generating an inverse signal of a corresponding level of the target node by using the storage module when particle collision occurs to the target node; therefore, the accuracy of circuit output level after a plurality of storage nodes are impacted by particles at the same time is improved.

The invention discloses a digital quantity output control circuit and method integrating overcurrent instantaneous protection and delay recovery functions. The circuit is mainly composed of a sampling module, a delay module, a voltage following module, an alarm module, an optical coupler isolation module and a typical digital output switch control module. When an over-current phenomenon is detected, the protection circuit can respond quickly, the circuit is cut off immediately to realize protection, and an alarm signal is output synchronously. Thereafter, the protection state will last for a preset delay time. During the period, the processor can monitor an alarm signal and output a circuit turn-off control signal according to the alarm signal. And after the delay time ends, the protection delay circuit automatically recovers to an initial state, and at the moment, the processor takes over signal output control according to the control logic. According to the invention, over-current instantaneous protection and delay recovery functions of the digital output circuit and smooth switching controlled by the processor are successfully realized, and safety risks caused by over-current faults are effectively avoided.

The invention discloses a latch, relates to the field of integrated circuit design, and aims to solve the problem that the error rate of circuit output level is relatively high after a plurality of storage nodes of a latch circuit are impacted by particles in the prior art. The latch at least comprises an input module, a clock control module, a storage module and an output module, the first end of an input module is connected with the input end of the latch, and the second end of the input module is connected with the input end of the storage module; the output end of the storage module is connected with the first end of an output module; the second end of the output module is connected with the output end of the latch, and the input end of the clock control module is connected with the clock signal input end; the output end of the clock control module is respectively connected with the input module and the output module; the latch is used for generating an inverse signal of a corresponding level of the target node by using the storage module when particle collision occurs to the target node; therefore, the accuracy of circuit output level after a plurality of storage nodes are impacted by particles at the same time is improved.

Provided is a single-ended to differential bidirectional bus transmission circuit, comprising: a bus splitting module for splitting a data input bus into a sending path and a receiving path in a data transmission process; the feedback control module is used for feeding back to the bus splitting module by monitoring the states of the sending path and the receiving path so as to use the sending path or the receiving path; and the signal conversion module is used for converting signals transmitted on the transmitting path and the receiving path into differential pair signals. In this way, the circuit complexity is reduced, and the data transmission performance is improved.

The invention discloses a high-reliability cold backup satellite-borne broadband waveform generation assembly, which comprises a main waveform generation module, a backup waveform generation module, an anti-radiation power supply chip and an up-conversion module, and is characterized in that the two waveform generation modules have the same structure and are used for generating broadband waveform signals; the up-conversion module performs up-conversion on broadband waveform signals output by the two waveform generation modules and outputs the broadband waveform signals, and the anti-radiation power supply chip performs mutual exclusion power supply on the two waveform generation modules. The waveform generation module comprises an anti-radiation FPGA chip, an anti-radiation high-speed DAC chip, an anti-radiation FLASH chip, an anti-radiation read-back refreshing chip, an anti-radiation differential transceiver chip and an anti-radiation level conversion chip, the anti-radiation read-back refreshing chip periodically reads a configuration program stored in the anti-radiation FLASH chip, the anti-radiation FPGA chip carries out configuration program refreshing, and the anti-radiation level conversion chip carries out level conversion. Therefore, the bit error upset in the anti-radiation FPGA chip can be corrected. According to the invention, the problems in the prior art can be solved, and the anti-radiation capability and reliability of the assembly are greatly improved.

The invention discloses a Kelvin source series connection type active gate drive circuit, and belongs to the technical field of power generation, power transformation or power distribution. The circuit is composed of a signal conditioning circuit, a bidirectional follower circuit, a feedback capacitor, a gate driver and a power supply circuit thereof, and a driving resistor. The signal conditioning circuit is provided with two input ports and two output ports, the two input ports are respectively connected with a power source electrode and a feedback capacitor of the switching device, and the two output ports are connected with an input port of the bidirectional follower circuit. The bidirectional follower circuit is provided with two input ports and a modulation output port, and the modulation output port is connected with a reference point of the gate driver and the power supply circuit of the gate driver. The output port of the gate driver and power supply circuit is connected with the gate of the switching device after being connected with the driving resistor. On the basis of common gate drive, low-delay and real-time feedback closed-loop active gate drive is realized by changing a circuit connection structure and utilizing reference point voltage modulation, and the purpose of reducing voltage and current overshoot of a power device is achieved.

The invention relates to the technical field of isolation driving chips, and provides a common-mode rejection circuit, an isolation transmission circuit and a motor driving circuit. The common-mode rejection circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a first clamping circuit and a second clamping circuit. The first clamping circuit is coupled between the power supply voltage of the receiver and a common node of the first end of the first transistor and the first end of the second transistor, and is used for clamping the voltage on the first common node; the second clamping circuit is coupled between a common node of the first end of the third transistor and the first end of the fourth transistor and the reference ground of the receiver, and is used for clamping the voltage on a second common node. According to the invention, the common-mode transient interference can be effectively suppressed in the isolation transmission circuit, and the system reliability is improved.

The invention relates to a high-performance low-power-consumption anti-radiation latch capable of tolerating three-node upset, which preserves an original high-performance low-power-consumption anti-radiation latch structure capable of tolerating double-node upset and inherits the capability of tolerating single-node upset and double-node upset of an original circuit. Two extra redundant nodes are introduced and form an interlocking monitoring network with the original nodes through a three-input C unit; a TNU detection and recovery module composed of two three-input C units is additionally arranged outside an original DNU feedback loop, the module continuously monitors the state consistency of a key node group, when errors of three or more nodes are detected, redundant nodes are started for state reconstruction, and a correct value is output through a voting mechanism. According to the invention, the fault-tolerant capability of the latch is comprehensively improved from DNU to TNU under extremely low extra overhead, and meanwhile, the excellent characteristics of low power consumption and high performance of the latch are maintained, so that the ultimate requirements of modern aerospace and other severe radiation environments on the reliability of an integrated circuit are met.

The invention discloses a high-speed level shifter applied to a BUCK converter. The high-speed level shifter comprises a level shifting part, a control logic part and an output part, after the level shift part inputs a signal, a low-delay rising edge and a high-delay falling edge of a conversion level A, and a high-delay rising edge and a low-delay falling edge of a conversion level B are output; the input of the control logic part adopts CLK in a BUCK converter to generate a short pulse, a high-voltage domain where SW and BST are located is isolated from a low-voltage domain, when the short pulse is at a high level, an output control signal is high, and when the short pulse is at a low level, the output signal is low; the input of the output part is the output of the level shift part and the control logic, and when the control signal is high, a low-delay rising edge is selected to be output; and when the control signal is low, selecting to output a low-delay falling edge. The level shift result is output through double ports, and low delay of conversion between the rising edge and the falling edge is achieved.

Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of a switch to remove a decoupling capacitor from an RF circuit on an integrated circuit (IC) pin where the storage cap is connected; or modifying the turn-on threshold of an electrostatic discharge protection device (ESD) on the IC pin with the storage cap present to reduce susceptibility to turning on the ESD with the RF signal; or de-Qing the analog and digital core capacitances to minimize their contribution to resonance; or a combination thereof.

The invention belongs to the field of integrated circuits, and discloses a level shifter with high dv / dt noise resistance and a self-adaptive power tube, which comprises a level shifting main body circuit and an auxiliary pull-up circuit. According to the invention, the auxiliary pull-up circuit which can be adaptively started according to the conduction time of the power tube is added, so that high dv / dt noise resistance can be realized in an application scene that different power tubes are adopted outside a chip.

The present application provides a clock gating circuit and a method for implementing the clock gating circuit. The clock gating circuit includes: a state machine, a triple-module redundant latch circuit and a logic gate circuit; the state machine is used to generate a control state signal according to a state jump triggered by an input control signal, and input the triple-module redundant latch circuit; the triple-module redundant latch circuit is used to latch the control state signal according to the input previous-stage clock signal, and output the latch signal to the logic gate circuit; the logic gate circuit is used to perform an AND operation on the latch signal and the previous-stage clock signal to generate and output a clock control signal. In the present application, the state machine and triple-module redundant technology are applied to the clock gating circuit to enhance the ability of the clock gating circuit to resist radiation.

An input / output (I / O) sensor is provided for a multi-IC (Integrated Circuit) module. The I / O sensor includes: a signal input, configured to receive a data signal from an interconnected part of an IC of the multi-IC module; and a time duration measurement circuit, configured to measure a time duration between a first time, at which the data signal is at a first level, and a second time, at which the data signal is at a second level, different from the first level. The sensor may be incorporated into an I / O block, an IC, and / or a multi-IC module. An I / O sensor which includes a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

A level conversion assembly (50), an overcurrent protection method, and a display device. The level conversion assembly (50) comprises a level conversion module (51); and the level conversion module (51) comprises a control unit (511), a current measurement unit (512), a level conversion unit (513), and an overcurrent protection unit (514). When at a first falling edge of a digital clock signal (CPV), the control unit (511) determines, on the basis of a correspondence of a current display mode, a first analog clock signal corresponding to the first falling edge among a plurality of analog clock signals (CLK1-CLK8), and controls the current measurement unit (512) to measure the current of the first analog clock signal; and the moment of a falling edge of the digital clock signal (CPV) is at the last row of a high-level period or low-level period in a corresponding analog clock signal, so that the current measurement unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not within a current threshold range, thereby achieving the effect of improving the accuracy of overcurrent detection.

The invention discloses an LDO (Low Dropout Regulator) circuit and method for preventing residual electricity hot plug output overcharge under a no-load condition. The LDO circuit comprises a comparator and a pulse signal generation module, the pulse signal generation module is connected with the comparator and is connected with the low static power consumption circuit through the PMOS tube, the first amplifier outputs a voltage signal based on an external reference voltage and a feedback voltage and outputs a driving voltage # imgabs0 # through the NMOS tube and the low static power consumption circuit, and the second PMOS tube generates and controls an output voltage based on an external input voltage and the driving voltage. The comparator compares the external input voltage with the output voltage and outputs a third voltage signal to the pulse signal generation module, and the pulse signal generation module generates a second voltage signal based on the third voltage signal; a pulse signal is generated through the comparator and the pulse signal generation module to modulate the grid electrode of the second PMOS tube, so that the output voltage is prevented from being overcharged when the external input voltage is subjected to residual electricity hot plug power-on under the no-load condition.