70 results about "Megabyte" patented technology

A system for the secure transfer of data and data management on the Internet has a data encryption and transfer module operable in a user computing system, a data management module operable in a server computing system, the transfer of data between the user and server computing systems being effected on the user computing system through use of the data encryption and transfer module, by moving the data to or from a first desktop window, associated with the user computing system, from or to a second desktop window, associated with the server computing system, each window being associated with a password, such that the step of moving the data from one window to the other causes the data to be encrypted/re-encrypted from one associated password to the other. The system also includes a password management module operable in the user computing system for managing the passwords, which are required to be used by a user of the system. The system uses symmetric key encryption coupled with file transfer protocol (FTP) data transfer and allows for the secure transfer of large data files of 100 megabytes or more.

A method is presented that enables the viewing of network data consumption from an alternative data plan (ADP) by a mobile device in terms of content. The method includes associating a mobile device, an application and content with an ADP and viewing data consumption in terms of content. A counter may be adjusted each time content associated with the ADP is consumed and the counter may be displayed on the mobile device which may also display data consumption in terms of megabytes (MB). The threshold size for the counter to increment may be preset per the rules of the ADP.

A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place. Upon presentation of a row and array, the scoreboard determines if the presented row is currently open, and if so, generates a hit signal that allows an immediate read/write access to the presented row. If the presented row is not open, the present invention generates a miss signal so that the row can be immediately opened before access is allowed. The scoreboard contains a memory unit containing row information for each array in the DRAM. The scoreboard, in addition to other novel features, allows an efficient DRAM configuration allowing dual memory accesses per cycle.

The invention discloses a system, a device and a method for testing a power over Ethernet (POE) function. The system comprises tested power sourcing equipment (PSE) ports and a power over Ethernet (POE) function test device, wherein the tested PSE ports connect Ethernet line pairs carrying data signals and electric signals with corresponding ports of the POE function test device respectively; and the POE function test device has ports and transformers, is used for connecting all the Ethernet line pairs which are led in through the ports with corresponding transformers respectively, and separates the electric signals and the data signals through the transformers. The system, the device and the method are compatible with test on the POE function of the Ethernet PSE having different power supply schemes and also compatible with test on POE function of the Ethernet PSE of gigabytes and megabytes, and have the advantages of low cost and simple operation.

The invention provides a multifunctional control system for a light-emitting diode (LED) display screen. The system comprises a transmitting control part on a computer and a receiving processing part on a screen body, wherein the transmitting control part on the computer comprises a high-definition multimedia interface (HDMI) video processing and transmitting module, an HDMI strobe, a microprogrammed control unit (MCU), a 100-megabyte network physical layer (PHY), an audio communication module and a monitoring output module which are connected with the HDMI video processing and transmitting module, a universal serial bus-recommended standard 232 (USB-RS232) conversion module which is connected with the MCU, and a network power supply module which is connected with a network transformer; the receiving processing part on the screen body comprises a 1000-megabyte network matrix, a network power receiving module, an HDMI video processing and receiving module, and a HDMI decoding module, a programmable control module, an infrared receiving module, an audio communication module, a monitoring input module and a network transformer module which are connected with the HDMI video processing and receiving module; the HDMI video processing and transmitting module and the HDMI video processing and receiving module transmit high-definition video and audio signals and infrared information, RS232 information, audio communication information and video monitoring information through network cables, and a network power supply function is supported.

The invention discloses an interpolation-based all-digital high-speed parallel timing synchronization method. Timing synchronization interpolation is performed on the received parallel data signal by a parallel interpolation filter, and the parallel data signal after interpolation is outputted; a parallel timing error detector calculates a timing error signal of the parallel data signal after the interpolation, and an average timing error signal is obtained; the average timing error signal is filtered via a loop filter and a step adjusting signal is outputted; and a parallel digital controlled oscillator adjusts internal control characters according to the step adjusting signal, and then the interpolation is performed on the parallel digital signal by the parallel interpolation filter via controlling at an optimal sampling point so that timing synchronization is realized. The interpolation-based all-digital high-speed parallel timing synchronization method is suitable for any modulation methods and encoding modes under high-speed transmission rate of hundreds of megabytes bits per second and even gigabits per second without being influenced by carrier wave frequency deviation and phase deviation, and timing synchronization can be accurately completed without carrier wave recovery.

A provider of standardized services is provided with guidance on the design of pricing structures for contracts regulating the provision of a commodity good between a supplier and a customer. These are contracts characterized by long duration and dedicated infrastructure. The provision of the commodity good is variable over time, and the rate of provisioning is continuously monitored. Examples are kilowatt hours in the case of electric energy and megabytes/second in the case of Web hosting.

The invention discloses a cross-correlation phase noise detecting device which comprises a to-be-detected signal phase detecting unit, a reference signal phase detecting unit, a first subtracter, a second subtracter and a crosspower spectrum computation module. The technical scheme adopted by the cross-correlation phase noise detecting device provided by the invention has the following advantages: an input signal frequency can cover any single-frequency point within a range of hundreds of megabytes, and real-time measurement to near carrier frequency phase noise is achieved; a testing system does not require a reference source which is the same as a to-be-tested source in frequency and orthographic with the to-be-tested source; the characteristics of a digital filter are fixed, a phase rectification calibration and low-noise amplifier is not required, so that the testing uncertainty of the system is reduced; testing links such as scaling, locking and the like are eliminated, since operation is achieved through several keystrokes, real-time measurement results can be obtained, the operation is simple and easy, and the cost performance of the detecting device is high; compared with a digital phase noise measurement system for removing noise in the prior art, the cross-correlation testing system has the noise bottom indexes improved by about 30dBc/Hz.

What is disclosed is a method by which a client-side handheld device requests a server to convert server-side documents into a compression format prior to transmission of said documents to the client. The server retrieves and converts the requested documents to a raster image that is then compressed according to attributes based on information received from the client device in the initial document request. Instead of having to manipulate multiple formats which the original documents are in and supported by the server, the client-side device is preferably optimized in hardware and/or software to support and otherwise take advantage of the requested compression format. The compressed document is then delivered to the client device, in whole or in part, selectively or progressively over time per individual requests prior to displaying the received data to the end-user. Depending on the requested delivery mode, server-side documents are preferably compressed using wavelet compression methods, such as the JPEG 2000 standard, known in the arts. Through such a compression format, documents of sizes (in total bytes) exceeding one or more Megabytes can be compressed down to as small as 30 kilobytes or less.

The invention discloses an on-site relay protection system, and aims at solving the technical problem of improving the reliability of a digital substation. The on-site relay protection system is provided with a single-space protection device, a cross-space protection device and a measurement and control automation device, wherein the single-space protection device is arranged on site; the cross-space protection device and the measurement and control automation device are arranged in a master control room of the digital substation; and the single-space protection device communicates with the master control room through an optical fiber of hundreds of megabytes. Compared with the prior art, the on-site relay protection system has the advantages that the single-space protection device communicates with the master control room through the optical fiber, so that a lot of cables are saved, one part of optical fiber is saved, the on-site arranged system is terminated in an outdoor cabinet for installation, wiring and connection are facilitated, a device with high heat is arranged outside the outdoor cabinet, direct and natural heat dissipation is carried out through a housing of the device, the heat emitted from the outdoor cabinet is reduced, an air conditioner is not needed, the relay protection cost is reduced, the reliability of the system is improved and operation and maintenance are facilitated.

A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

The invention provides an efficient, robust and safe large data polymerization system and method. The efficient, robust and safe large data polymerization method comprises the steps that mobile equipment log data is sent to web log collection servers through interfaces, and a Flume Agent process is arranged on each web log collection server; the Flume Agent process sends all log data of Agent to a central server by adopting a LoadBalanece Agent strategy in an equilibrium mode; and the data enters the central server and is written in a magnetic disk, and the log data stored in an extranet disk is transmitted to an intranet through GAP. According to the method, massive log data is collected by means of the open source software Apache Flume, Kafkachannel of Flume is used as a data gathering mode, which can both guarantee the efficiency of data collection, and meanwhile guarantee the data will not be lost due to single point failure, thereby having obvious advantages compared with memorychannel and filechannel of the Flume. After the massive log data is written in the disk, Hdfs is recorded through a custom interface, and a speed of hundreds of megabytes per second has been achieved, which approaches to the bottleneck of the traditional bandwidth of hundreds of megabytes and is close to the rotating speed of the magnetic disk.

The invention relates to method for transmitting additional information in a 100 m Ethernet and a system of the method. The transmission method mainly utilizes fixed frame gaps between 100 m Ethernet data frames to transmit the additional data, such as time synchronization information and control information. The communication system based on the idea mainly comprises a mobile terminal, an Ethernet protocol physical layer module and an MII interrupt processing module, and the Ethernet protocol physical layer module switches information of terminals hierarchically, which is convenient for the MII interrupt processing module to insert data and to extract and analyze the data. The method utilizes the fixed frame gaps between the 100 m Ethernet data frames to transmit the additional data, which no longer occupies the in-band bandwidth of the Ethernet package, and the method is a novel data transmission method which has on interference to the normal Ethernet packet transmission and greatly improves the utilization of the bandwidth.

The present invention discloses an analog signal FFT implementation method based on an FPGA. The method comprises the steps of: S1, performing voltage attenuation of analog sampling signals to outputanalog voltage signals; S2, performing A/D conversion of the analog voltage signals to output digital signals; S3, inputting the digital signals to an IP core in the FPGA, transferring the IP core toachieve FFT transform and calculation, and outputting an FFT conversion result; S4, transferring an embedded logic analyzer in the FPGA to perform spectral analysis of the analog sampling signals, thedigital signals and the FFT conversion result; and S5, obtaining a signal frequency, a direct current component, other components and phases through calculation, and performing comparison with the signal frequency, the direct current component, the other components and the phases of the analog sampling signals. The analog signal FFT implementation method is high in transportability, can conveniently correct and process number of points of the signals, is good in real-time response, can conveniently utilize an embedded soft probe to capture and analyze the data, is fast in speed which can reach hundreds of megabytes, and is low in hardware resource occupancy rate.

The invention relates to a multi-screen splicing system based on an FC-AV protocol, and the system comprises an upper computer, a video integration and distribution controller, an optical fiber, and areceiving controller. The upper computer is a video source scheduling control end of the whole system; a video display command is issued by user operation; the video integration and distribution controller is responsible for decoding multiple types of video data into RGB pixel data, processing and packaging the RGB pixel data into a plurality of FC-AV data frames according to instructions of an upper computer and remotely transmitting the FC-AV data frames to the receiving end through optical fibers, and the receiving end identifies frame header numbers to receive the corresponding FC-AV dataframes and converts the data into video signals to be displayed. According to the multi-screen splicing system based on the FC-AV protocol, based on server video coding of the IP protocol, the code stream coding rate is 4Mbps at most; the FPGA coding rate based on the FC-AV protocol takes a pixel clock as a reference and is as high as dozens of megabytes to more than one hundred megabytes. And the video is not compressed, and high-bandwidth, high-reliability, low-delay and long-distance lossless transmission of the video can be realized without compressing the video.

The invention discloses a design method of master/slave station cards for implementing Powerlink industrial real-time Ethernet communication. The master/slave station cards can be configured to be a Powerlink industrial real-time Ethernet communication master station card or slave station card. During the designing process, a kernel layer and an MAC layer of a Powerlink protocol stack are constructed inside an FPGA and a CAL driver is also constructed and is connected with the kernel layer. When the master/slave station cards are used, a gold finger is inserted into an upper computer main board CAL mother base and the upper computer operates the CAL interface driver and a user layer and an application program of the Powerlink protocol stack. According to the invention, with the high-speedserial differential signal CAL interface inside the Powerlink protocol stack, the high-speed transmission of over one hundred megabyte as well as the signal stability is guaranteed, the communicationrate is increased, and the cycle time is shortened, so that the communication real-time performance is improved.

The functions of two virtual operating systems are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques.

A magnetic disk medium having on a support a magnetic layer containing hexagonal ferrite powder dispersed in a binder, with the support having a thickness of 20 μm to 80 μm and the magnetic disk medium having an inside diameter X of 2 mm to 10 mm, an outside diameter Y of 20 mm to 50 mm, an X/Y ratio satisfying the relation 0.05≦X/Y≦0.20 and a curl quantity of 1 mm or below, which is suitable for use in small-diameter portable computer equipment and video recorders, and besides, can attain a recording capacity of at least several hundred megabytes.

The invention discloses a medium gateway network interface alarm detection method and a device thereof. The method includes that: after receiving the issued allocation order, a network interface board judges its own active-standby state; if the network interface board is a standby network interface board, the network interface board is arranged to prohibit transmission, and the working mode of its own gateway and the working mode of a corresponding gateway of a data device in butt joint with the network interface board are arranged to be forced megabyte full-duplex modes; the network port status of the standby network interface board is detected, and an alarm is sent out or recovered according to the change of the detected network port status. The method and the system can realize fault alarm detection of the standby network interface board under current networking mode, realize detection alarm when a fault occurs in the connection of netting twines and realize alarm recovery when the network cable connection is recovered.

The invention discloses a cross-steam interface waveguide generation method based on artificial bubbles. The method is mainly applied to the cross-stream interface uplink transmission of the high-frequency electromagnet wave (megabytes frequency) in the process of reaching a sea surface receiver by penetrating seawater at the shallow sea surface. The method comprises the following steps: a waveguide device integrated with a bubble generation device and an antenna is used underwater, the bubble waveguide generating unit is used for producing a underwater bubble layer, and a signal emitted by a signal emitting unit is propagated to the water surface through the underwater bubble layer. The equivalent dielectric constant and the conductivity of a seawater specific space are changed by use of the bubbles, and then the electromagnetic wave transmission environment is changed, the transmission of the high-frequency electromagnet wave at the megabytes frequency in the bubble waveguide is realized, and the signal has enough energy to accomplish the air-based and space-based signal transmission after crossing the seawater interface. The method disclosed by the invention is simple in operation, high in secrecy, green and environment-friendly, the technical blank in the cross-steam interface transmission is filled; therefore, the high-frequency electromagnet wave can break the attenuation barrier and can be really applied to the underwater communication field.

The invention discloses a fast and real-time video coding and decoding compression algorithm. The coding algorithm comprises the following steps of S01, inputting a bitmap image sequence, and performing the brightness color difference signal transformation on the bitmap image sequence; S02, performing the differential transformation on the bitmap image sequence after the brightness color difference signal transformation process; S03, performing the fast frequency domain transformation on the bitmap image sequence after the differential transformation process; S04, performing the rapid quantization on the bitmap image sequence after the fast frequency domain transformation process; S05, conducting the entropy compression on the fast quantized bitmap image sequence, and outputting the coded data of a compressed video. In addition, the invention discloses the specific steps of the decoding algorithm. According to the invention, the information of a high-definition image can be compressed at about 8-16 megabytes per second based on software. In this way, the transmission and storage problem during the video real-time coding and decoding process of a video processing host and partly embedded equipment without special hardware processing in the prior art is solved. The method can be widely applied to the fields of remote control, remote monitoring and the like for computer equipment.

A Firewire data recorder device in which contains a small electronic circuit that stores digital data onto a Firewire hard disk drive. The recorder is designed to be broadly applicable to many data storage applications, and takes in 16-bit parallel data and writes it to the hard drive at up to 35 Megabytes per second. Data rate is limited by the Firewire protocol and the target hard drive. The recorder device does not require that a host computer be attached. A programmable logic device is used to rapidly format the data structures and transfer data from the source onto the Firewire bus for storage.

The invention belongs to the technical field of bus control, and particularly relates to a terminal board card of a 1553B launch and control bus of hundreds of megabytes. The terminal board card comprises a CPCI base board connector, a processor, an FPGA, a simulation front end and a connector; the effect of the bus of hundreds of megabytes is mainly achieved by adopting high-speed AD and DA technologies and a simulation front end technology; and the board card communicates with a launch and control equipment main board through the bridge piece function of the processor, control over an ADC and a DCA is achieved through the FPGA on the board card, signals of the DAC pass through a differential-to-single end device and a smoothing filter and then are output to an analog switch, the analog switch switches output of the DAC and input of the ADC, input signals of the ADC pass through an anti-alias filter and a single end-to-differential device and then are input into the ADC. According tothe terminal board card, real-time performance requirements of full missile rapid response can be met, and the speed of the launch and control bus is increased.