10 results about "Megabyte" patented technology

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS / W) at 40 megahertz (MHz) with a 1 volt (V) supply.

Some embodiments include an integrated assembly having a memory array over a substrate. The memory array includes a three-dimensional arrangement of memory cells. A sense amplifier is associated with the substrate and directly below the memory array. A vertically extending digit line passes through the arrangement of memory cells and is coupled with the sense amplifier. Some embodiments include an integrated assembly having a memory bank containing 64 memory data blocks arranged in a 16x4 configuration. Some embodiments include an integrated assembly having a memory bank containing 512 megabytes divided among 64 memory data blocks, each memory data block having 8 megabytes. The 64 memory data blocks are arranged in a configuration having a plurality of rows, each row containing two or more of the memory data blocks.

The application provides a data consistency verification method and system for long-distance heterogeneous ends, aiming to solve the technical pain points of low efficiency, long time consumption, high cost and sensitivity to network delay caused by relying on full data network transmission when performing massive data consistency verification between long-distance heterogeneous databases in the prior art. By pushing down data-intensive computing tasks (such as hash calculation and aggregation) to the source and target databases for execution, only lightweight summary data (usually megabyte level) is transmitted in the network, and the final comparison is completed by the coordination end. The application has the following technical advantages: extreme network efficiency, order of magnitude improvement; not sensitive to high network delay; maximum utilization of computing resources; high compatibility of heterogeneous databases; robustness and intelligent degradation.

A stateless artificial intelligence game master system and method enables scalable, provider-agnostic interactive game experiences. The system comprises a stateless game server processing requests without persistent session state, a provider-agnostic AI orchestration engine supporting automatic failover between multiple language model providers, a context reconstruction module dynamically rebuilding game context from transaction logs, and a real-time integration module enforcing game mechanics without state persistence. The architecture achieves memory efficiency of approximately 16 kilobytes per session compared to 10+ megabytes for stateful implementations, enabling horizontal scaling without session affinity requirements. The system supports graceful degradation through template-based fallback when AI providers are unavailable. Security features include AES-256-GCM encryption of API credentials with session-specific initialization vectors. The invention addresses limitations of existing stateful AI game systems including memory accumulation, single-provider dependency, and session affinity requirements.

The application relates to the technical field of hardware detection, in particular to a memory detection method and device, a storage medium and an electronic equipment, which comprises the following steps: loading a pre-compiled memory detection program; setting test parameters of the memory detection program; acquiring a maximum address range of a system environment currently where the memory detection program is located, and converting the maximum address range into a format taking bytes and megabytes as units; dynamically applying for a memory space, and performing address alignment with the maximum address range; performing memory address data bus cycle detection and memory address data sensitivity detection, and outputting a final memory detection result. The pre-compiled detection program can quickly detect abnormal addresses in the memory, realizes the function of quickly and effectively detecting the stability of DDR memory in a VxWorks operating system, and reduces the complexity and development cost of the system.

The invention discloses a high-performance logic controller, which relates to the technical field of industrial automation control, and comprises an ARM core control module, and the ARM core control module is connected with a memory module and is used for storing system programs and user programs; the ARM core control module is also connected with a programmable logic module FPGA (Field Programmable Gate Array) and is used for controlling output and reading an input state through parallel port communication; the parallel port of the programmable logic module FPGA is connected with an IO expansion module which is used for expanding a plurality of inputs and outputs; the programmable logic module FPGA is also connected with an LVDS (Low Voltage Differential Signaling) module for an LVDS communication interface; the ARM core control module is further connected with an Ethernet module used for a network port communication interface, an RS232 module used for a serial port communication interface and a USB module used for a USB communication interface, and the IO expansion module is connected with an input module and an output module. On the premise that stability and reliability are guaranteed, the data transmission rate reaches hundreds of megabytes, input and output of control signals can reach hundreds or more, and the price is low.

The invention relates to configurable partitions and memory type independence in a memory system. The memory system may support different storage configurations for provisioning, including a first configuration for prioritizing high user capacity or megabyte write (TBW), and a second configuration for prioritizing independence or against interference FFI. In the first configuration, the memory system may support at most one partition per supported memory type. The system memory region may share one or more pools with the first partition or memory type, while other pools may be specific to each other partition or memory type. In the second configuration, the memory system may support multiple partitions within some memory types each having one or more respective pools. By selecting different storage configurations at the memory device, different characteristics may be permitted to be prioritized while providing greater provisioning flexibility.

The invention discloses a Chinese character digitalization coding model based on positive and negative heterozygotes. The model maps 98 basic components into unique rational data positive and negative one-bit numerical codes respectively; converting the Chinese character into an ordered positive and negative digital sequence according to the hierarchy, radical and stroke order rule; the sequence is directly converted into a unique binary machine code through a Chinese information exchange standard code table; according to the method, the storage space of the Chinese character information is greatly compressed, massive Chinese characters are disassembled into only 98 basic components to be coded and stored, the mode that tens of thousands and even hundreds of thousands of Chinese character font data need to be independently stored in a traditional scheme is replaced, the storage requirement of a Chinese character library is lowered from the megabyte level to the kilobyte level, and the storage efficiency of the Chinese character library is improved. And hardware storage resources are greatly saved.

The invention provides a data consistency verification method and system for a remote heterogeneous terminal, and aims to solve the technical problems of low efficiency, too long time consumption, high cost and sensitivity to network delay caused by dependence on full data network transmission when mass data consistency verification is carried out between remote heterogeneous databases in the prior art. Data-intensive calculation tasks (such as Hash calculation and aggregation) are pushed down into a source database and a target database to be executed, lightweight summary data (generally in a megabyte level) are only transmitted in a network, and final comparison is completed by a coordination end. The method has the technical advantages that the network efficiency is extremely improved, and the order of magnitude is improved; the method is insensitive to high network delay; the utilization of computing resources is maximized; the heterogeneous database compatibility is high; and robustness and intelligent degradation are realized.