28 results about "Logic analyzer" patented technology

The invention provides a logic analyzer trigger point accurate backtracking control method based on hotspot scoring and boundary learning, and the method comprises the steps: carrying out the popularity scoring according to the ratio of the number of channel compression units in each message segment to the length of an occupied byte, and screening out a hotspot candidate set; analyzing the structure of the hot area message segment and decoding, and realizing time alignment of a multi-channel sampling sequence in combination with the position offset adjusting quantity to form a synchronous sampling matrix; calculating local change intensity based on the matrix, introducing an inter-channel jump consistency constraint to construct a jump probability score, and accurately positioning a trigger point time index and a message segment where the trigger point time index is located; and finally, mapping a logic time position into a physical storage address in combination with a compression structure non-balance compensation parameter, so as to realize efficient reverse reading. According to the method, a mark or an additional address table does not need to be inserted, and high-precision backtracking control of the trigger point can be realized under the conditions of high compression ratio and multiple channels.

The utility model relates to the technical field of integrated circuit testing, and particularly discloses an integrated circuit experiment testing device which comprises a shell. A microcontroller, and a digital oscilloscope, a function generator, a digital logic analyzer, a pattern generator, a virtual digital I / O interface, a front PCB panel and a plurality of test interfaces which are electrically connected with the microcontroller are arranged in the shell; the front end of the shell is provided with a voltage acquisition interface, a current acquisition interface, a display screen and a plurality of voltage output ports which are electrically connected with the front PCB panel, the bottom of the shell is provided with an air inlet, a cooling fan is arranged above the air inlet, and the middle part of the shell is provided with a middle air outlet. According to the utility model, a plurality of instruments and meters are integrated to carry out experimental testing, so that the device is convenient to operate and overhaul, smaller in size and small in occupied space, meets the requirement of carrying out rapid testing in a limited space, and is suitable for design, simulation, manufacturing and testing of integrated circuits and related experimental teaching and scientific research activities.

The application provides a universal analog-digital converter testing device, which comprises at least an analog-digital converter testing module, a plurality of testing interface boards, a testing mainboard, an external power supply, a signal generator and a logic analyzer, the analog-digital converter testing module is sequentially connected to the testing interface boards and the testing mainboard, the external power supply, the signal generator and the logic analyzer are connected to each other and to the analog-digital converter testing module. The testing device can be modularly and independently operated, has strong expandability, can realize different functions in a simple form of building blocks, each component can be operated independently, and can be spliced when needed. The more the spliced module components are, the stronger the realized functions are. The testing device has simple operation and good maintainability, and can well solve the testing problem of analog-digital converters in practice.

The application discloses a bus fault reason determination method and electronic equipment, and relates to the technical field of computers, and comprises the following steps: if a target bus in a controller fails, determining a source pin corresponding to the target bus; determining a target pin corresponding to the source pin from a reserved pin; configuring the target pin based on configuration information of the target bus; configuring an interrupt mode of the source pin as an edge-triggered interrupt mode; when the source pin triggers an interrupt, reading a level signal of the source pin, setting an output level signal of the target pin to be consistent with the level signal of the corresponding source pin; and determining a fault reason of the target bus by collecting the output level signal of the target pin through a reserved terminal corresponding to the target pin by using a logic analyzer. The level signal of the source pin is copied to the target pin, and the logic analyzer is connected to the reserved terminal corresponding to the target pin, so that the technical effect of improving the fault reason determination efficiency is achieved.

The application discloses a kind of mixed radio frequency receiver group time delay test platform and method, including first, second vector signal source, first, second power divider, excitation signal generator, combiner, mixed radio frequency receiver of analog-digital, digital switching board, logic analyzer;First vector signal source simultaneously provides for second vector signal source and mixed radio frequency receiver reference clock, and second vector signal source generates OFDM modulated signal, and excitation signal is sent to logic analyzer by one end of second power divider, and triggers logic analyzer to prepare to accept test signal, and excitation signal is sent to second vector signal source by the other end of second power divider, and is superimposed to radio frequency receiver by combiner with OFDM modulated signal, and is accessed to logic analyzer by digital switching board.It is demodulated I / Q data information of test signal after logic analyzer receives excitation signal again, and calculates group time delay result.The application solves the problem of accurate measurement of group time delay of mixed radio frequency receiver of analog-digital.

The application relates to the technical field of data storage, and discloses a system for improving the test efficiency of a logic analyzer on a storage chip and a test efficiency method thereof, which comprises: an SOC chip connected with a test circuit board on one side and connected with the lower surface of a conversion board on the other side; wherein the first connecting area of the lower surface of the conversion board is used for connecting the SOC chip, and the second connecting area of the upper surface of the conversion board is used for connecting a to-be-tested storage chip; the first connecting area of the lower surface of the conversion board is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure comprises a plurality of first pins; the second connecting area of the upper surface of the conversion board is provided with a second pin structure corresponding to the pin arrangement of the to-be-tested storage chip, and each second pin structure comprises a plurality of second pins; and the conversion board comprises a plurality of metal layers stacked between the upper surface and the lower surface. The application improves the response speed of storage chip testing.

The utility model discloses a measurement interface assembly for a logic analyzer, belongs to the technical field of logic analyzer auxiliary instruments, and aims to solve the problem of unstable connection of a wiring interface between the logic analyzer and a tested device. Comprising an auxiliary seat, the auxiliary seat comprises a main body limiting part and a probe connecting line limiting part, the main body limiting part is arranged on the horizontal plane of the auxiliary seat, the auxiliary seat is connected with a logic analyzer through the main body limiting part, and the probe connecting line limiting part is arranged on a vertical arm of the auxiliary seat to fix a probe connecting line. And the stability of the probe interface is kept when external force dragging is avoided.

The application provides an automatic testing system and method for an ADC chip, wherein a host computer generates a signal starting instruction and parameter information for configuring a tested ADC chip to perform automatic testing; a signal injector inputs a continuous sine wave signal to the tested ADC chip according to the signal starting instruction; the tested ADC chip acquires a digital signal formed after the sine wave signal is converted into a digital signal according to the parameter information; a logic analyzer captures the digital signal and uploads it to the host computer; and the host computer processes the digital signal to obtain a performance test result. The ADC chip is inputted with a continuous sine wave analog signal, and the test parameters are configured by the host computer, and the conversion result is read, so that the test efficiency is improved, the test cost is reduced, and the flexibility of the test is improved by configuring the parameters by the host computer.

A chip-embedded logic analyzer autonomously sequences between logic analysis scenarios, dynamically revising match criteria and match-responsive behavior as match conditions for each successive scenario are met. Through this cascading-scenario operation, the logic analyzer may log selected debug vectors as and / or after complex sequences of device conditions unfold, enabling substantially more targeted and sophisticated operational debugging than conventional trigger-and-log analyzers.

The invention relates to the technical field of data storage, and discloses a system and a method for improving the test efficiency of a logic analyzer on a storage chip, and the system is characterized in that one surface of an SOC chip is connected with a test circuit board, and the other surface of the SOC chip is connected with the lower surface of an adapter plate; wherein the first connection area on the lower surface of the adapter plate is used for connecting an SOC chip, and the second connection area on the upper surface of the adapter plate is used for connecting a storage chip to be tested; a first connection area on the lower surface of the adapter plate is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure comprises a plurality of first pins; a second connection area on the upper surface of the adapter plate is provided with second pin structures corresponding to the pin arrangement of the memory chip to be tested, and each second pin structure comprises a plurality of second pins; the adapter plate includes a plurality of metal layers stacked between the upper surface and the lower surface. According to the invention, the response speed of the memory chip test is improved.

The invention discloses a bus fault reason determination method and electronic equipment, and relates to the technical field of computers, and the method comprises the following steps: if a target bus in a controller fails, determining a source pin corresponding to the target bus; determining a target pin corresponding to the source pin from the reserved pins; based on the configuration information of the target bus, performing corresponding configuration on the target pin; configuring the interrupt mode of the source pin as an edge trigger interrupt mode; when the triggering of the source pin is interrupted, reading the level signal of the source pin, and setting the output level signal of the target pin to be consistent with the level signal of the corresponding source pin; and acquiring an output level signal of the target pin through the reserved terminal corresponding to the target pin by utilizing the logic analyzer, and determining a fault reason of the target bus. The level signal of the source pin is copied to the target pin, and the logic analyzer is connected with the reserved terminal corresponding to the target pin, so that the technical effect of improving the fault cause determination efficiency is achieved.

The utility model discloses a standard EMMC encapsulation adapter bottom plate, chip clamp and debugging tool suit, the standard EMMC encapsulation adapter bottom plate, including the board body, the board body includes the first side and second side on the thickness direction, the first side is suitable for with EMMC chip adaptation or simulation EMMC chip, the other side is provided with pin interface, by this, through setting debugging main body module, standard EMMC encapsulation adapter bottom plate, and the cooperation FPGA platform adapter soft board, EMMC chip clamp and logic analyzer interface, realized the integration of early chip parameter debugging, simulation and later whole platform verification debugging, utilize the standard EMMC encapsulation interface adaptation of standard EMMC encapsulation adapter bottom plate all EMMC platform's storage device, solved the poor problem of compatibility of existing debugging tool, greatly improved the debugging efficiency, reduced the debugging cost.

The invention belongs to the technical field of embedded development instruments, and relates to an integrated multifunctional debugger based on a microcontroller. The integrated multifunctional debugger comprises a shell, a main control board, a signal board, a screen, a battery and a rotary encoder. A microcontroller module, a power meter module, a spectrum analyzer module, a PWM output module, a development module and a Bluetooth module are integrated on the main control board, and bus voltage, current and power measurement, spectrum analysis, adjustable PWM signal output, user-defined function development and remote control operation through keyboard Bluetooth can be achieved. The signal board is provided with a logic analyzer module and a USBHUB module and is used for analyzing digital circuit signals. The debugger integrates multiple functions, and solves the problems that a traditional instrument is single in function, large in size and high in cost.

The invention discloses an independent FPGA online debugging device and debugging method, and belongs to the technical field of electronic device testing. The independent FPGA online debugging device comprises an upper computer, debugging equipment and a to-be-tested FPGA; the upper computer is used for instruction input and data visualization, and the debugging equipment is connected with the upper computer and is provided with an integrated controller, an integrated logic analyzer and a signal decoder; the to-be-tested FPGA is connected with the debugging equipment, and is provided with a signal encoder which is used for transmitting data to the debugging equipment. The debugging device is arranged, the integrated controller, the integrated logic analyzer and the signal decoder are arranged in the debugging device, the signal triggering, signal acquisition and signal storage processes performed in the FPGA to be tested are externally arranged in the debugging device, and the external debugging device breaks away from the constraint of the FPGA to be tested; according to the technical scheme, the data collection amount and the storage amount can be set according to the requirements of designers, the limitation of the performance of the to-be-tested FPGA is avoided, the number of sampling signals and the sampling depth can be greatly improved, and then the testing efficiency and the testing accuracy of the to-be-tested FPGA are improved.

The invention discloses a NAND Flash time sequence measurement method, device and equipment and a storage medium, and the method comprises the steps: welding a first PCB hard board with the size matched with a ball grid array (BGA) pin layout and a NAND Flash particle to be measured on a circuit board to be measured to replace the NAND Flash particle to be measured; the NAND Flash interface signal to be tested is transmitted to the second PCB hard board through the PCB soft board; connecting the logic analyzer to a connector of the second PCB hard board so as to carry out NAND Flash time sequence measurement; according to the NAND Flash interface time sequence testing method and device, efficient and accurate non-intrusive testing of the NAND Flash interface time sequence can be achieved, NAND Flash particles to be tested are seamlessly replaced, signal attenuation and crosstalk are effectively eliminated, the testing efficiency, reliability and data accuracy are remarkably improved, and the NAND Flash time sequence measuring speed and efficiency are improved.

The invention relates to the technical field of communication, in particular to a communication data real-time monitoring method and device, electronic equipment and a computer storage medium, and the method comprises the steps: receiving an original data stream of to-be-debugged equipment transmitted by a communication adaption module, recognizing the original data stream according to a protocol description file which is customized by a user and imported in advance, and transmitting the recognized original data stream to a communication adaption module; and determining a corresponding complete data frame, analyzing and checking the complete data frame to obtain structured data, and associatively storing the structured data and the original data stream. The problems that a universal serial port debugging assistant is low in efficiency and prone to making mistakes, a logic analyzer and the like are high in cost and poor in flexibility, a self-compiled temporary debugging program is long in development period and poor in reusability are solved, and the requirement for real-time monitoring of communication data in program development and debugging in the fields of an embedded system and the like can be effectively met.

The invention discloses an FPGA online debugging device and debugging method based on an external memory, and belongs to the technical field of electronic device testing. The FPGA online debugging device comprises an upper computer, a debugging circuit board and an FPGA to be tested; the upper computer is used for instruction input and data visualization; the debugging circuit board is connected with the upper computer and is used for providing a test environment for the FPGA to be tested; the to-be-tested FPGA is connected with the debugging circuit board through the Ethernet, the to-be-tested FPGA is provided with an integrated controller, an integrated logic analyzer and an external storage controller, and the external storage controller is connected with an external memory. According to the method, the external storage controller is additionally arranged on the original FPGA to be tested, and the external storage controller is connected with the external storage, so that the FPGA to be tested does not depend on RAM resources in the original FPGA any more, and the external storage with any storage capacity can be selected as required; after the external memory is adopted, the number of collected signals is not limited, the sampling depth can be greatly improved, and the debugging efficiency and the debugging accuracy of the online debugging device are improved.

Embedded logic analyzer (50) of an integrated circuit (10) with: a comparator block (100) configured to generate a comparator data signal (CPDT) and a plurality of comparator enable signals (CMPEN) based on an input data signal (INDT) from one of the function blocks (11-17) contained in the integrated circuit (10), such that the comparator enable signals (CMPEN) are each activated based on different comparator conditions; an operation block (200) configured to perform a logic operation on the comparison enable signals (CMPEN) to generate a data enable signal (DTEN) indicating a data acquisition time; and a packer circuit (300) configured to generate a packer data signal (PCKDT) with acquisition data and acquisition time information, based on the acquisition data signal (CPDT), the data release signal (DTEN) and a time information signal (TMINF), where the comparison block (100) contains: a plurality of comparator circuits (COMP1-COMP8), each comparator circuit (COMP1-COMP8) being configured to generate a enable signal (CMPEN1-CMPEN8) from the comparator enable signals (CMPEN) based on the input data signal (INDT) and a control signal from the comparator control signals (CMPCON) specifying the comparator control conditions, where at least one first comparator circuit of the majority of comparators (COMP1-COMP8) is configured to: Shifting of one of the input data signal (INDT) and a first shifted data signal from a second comparator circuit of the plurality of comparators (COMP1-COMP8) to generate a second shifted data signal and Comparing the second shifted data signal with a reference data signal and a third shifted data signal from a third comparator circuit of the plurality of comparators to generate the enable signal generated by the first comparator circuit.

The invention discloses a vector generation method for CPLD (Complex Programmable Logic Device) configuration data, which comprises the following steps of: establishing a set of CPLD configuration data real-time acquisition system through a logic analyzer and a real JTAG downloader, and acquiring and storing all configuration data downloading processes of four pins TDI, TCK, TMS and TDO of a JTAG port; a JTAG protocol decoding function of a logic analyzer is utilized to decode acquired configuration data information to obtain a text record file about a process of running CPLD configuration data by TDI, TCK, TMS and TDO, a standard SVF language format is combined to compile and generate an SVF vector file, and the SVF vector file can be directly used for ATE automatic testing after conversion. Although 500 times of operation needs to be repeatedly executed in the acquisition stage, the generated 500 SVF files can be all used for ATE automatic testing, a real installation system is not needed, and the method has the advantages of automation, high efficiency, low cost and the like.

The application discloses a logic analyzer and method based on real-time state analysis of a pipeline, relates to the technical field of electric digital data processing, and solves the problems that the existing logic analyzer cannot realize real-time online analysis, invalid sampling point data storage is large, storage bandwidth occupation is high, and sampling data dynamic compression is difficult. The application comprises a SerDes sampling module, a synchronous acquisition state clock signal and M digital channel signals; a serial-parallel conversion module, which converts serial sampling data into parallel sampling data; a two-stage pipeline processing module, a first-stage pipeline performs effective edge identification on the parallel state clock sampling data, and a second-stage pipeline extracts the state corresponding to the effective edge from the parallel state sampling data, and the state is recorded as an effective state; a shift register dynamic compression module, which synchronously writes the effective state into a shift register; and a trigger judgment module, which generates a state trigger signal based on the effective state in real time. The application can realize real-time state analysis and dynamic compression of sampling data.

The embodiment of the present application provides a digital signal waveform analysis method, which can effectively solve the problem that the existing logic analyzer is too slow when decoding a large amount of sampling data, comprising: dividing the collected digital signal waveform into a plurality of first sub-digital signal waveforms composed of stable logic waveforms and a plurality of second sub-digital waveforms composed of changeable logic waveforms; judging whether each first sub-digital waveform matches a preset condition one by one, if yes, matching is performed, and if no, subsequent processing is triggered.

The utility model relates to the technical field of testing, in particular to an electronic tester, which comprises a signal input end, a signal processing circuit, a main control module and a signal output end, and is characterized in that the signal input end is used for receiving a signal to be tested; one end of the signal processing circuit is connected with the signal input end, and a conditioning signal is generated after a signal to be tested is conditioned; one end of the main control module is connected with the other end of the signal processing circuit, outputs a waveform signal meeting a first waveform condition according to the conditioning signal, and / or displays the conditioning signal, and / or generates a logic analysis result according to the conditioning signal; and one end of the signal output end is connected with the other end of the main control module and is used for outputting a waveform signal, and / or a conditioning signal, and / or a logic analysis result. Therefore, the problem that an electronic testing instrument has significant limitations in the aspects of function integration level, portability and high-frequency signal processing capacity is solved, the functions of a signal generator, an oscilloscope, a logic analyzer and the like are integrated, and the device has the characteristics of high precision, wide band and portability.

1. The name of the design product: device debugging graphical user interface for laser pipe cutting machine. 2. The use of the design product: for laser pipe cutting machine. 3. The design points of the design product: in the graphical user interface content. 4. The picture or photo that best indicates the design points: design 1 front view. 5. Design 1 is designated as the basic design. 6. The use of the graphical user interface: for configuring the control information of the laser pipe cutting machine. 7. The change state description of the graphical user interface: design 1 front view is used to display the real-time position information of the machine tool processing, and to perform the motion control, manual calibration control, graphical operation, process addition and part nesting settings; design 2 front view is used to perform the cutting process parameter setting, machine tool parameter setting, equipment maintenance and production planning setting; design 3 front view is used to perform the logic analyzer, PLC editing and peripheral connection setting; design 4 front view is used to view the current processing product information and state, current drawing preview, prompt next processing file and information display.

This utility model discloses a multifunctional electronic experimental platform, belonging to the field of electronic circuit testing and measurement technology. It includes a host computer, which houses a control motherboard, an input power module, and an output power module. The control motherboard includes a logic level input module and a logic level status display module, a BCD decoder digital tube, a TYPE-C power input interface, a TYPE-C emulator interface, and a TYPE-C virtual instrument interface. The control motherboard also includes a waveform generator channel, a spectrum analyzer channel, a network analyzer channel, a virtual oscilloscope channel, a programmable power supply channel, a logic analyzer channel, a protocol analyzer channel, and a voltmeter / voltage recorder channel. This utility model creates a multifunctional, portable, and highly flexible electronic experimental platform. It can provide innovative experimental courses for online teaching at a reasonable price.

This application provides an autonomous driving method, apparatus, system, and vehicle for model fine-tuning, relating to the field of autonomous driving. The method includes: acquiring system prompts and multimodal data of an autonomous driving task, where the system prompts indicate the selection of a reasoning mode based on scene information; processing the multimodal data and system prompts using a Virtual Logic Analyzer (VLA) model to obtain current scene information of the autonomous driving task and the corresponding current reasoning mode; processing the multimodal data under the current reasoning mode of the VLA model to obtain a current processing result; and executing the autonomous driving task according to the current processing result. This solution addresses the problems of insufficient cross-scene reasoning flexibility and low reasoning efficiency of the VLA model.

The invention relates to the technical field of data storage, and discloses an LPDDR5 digital signal capturing method based on a logic analyzer, and the method comprises the steps: carrying out ball mounting welding on CA signals and CS signals of A / B channels of LPDDR5 and to-be-tested instruments on a test board, and selecting corresponding plots according to the actual connection condition, the number of the to-be-tested instruments being eight; during connection, Plot is distributed according to actually connected signal lines, sampling clocks of each group of Plot are uniformly connected to a CKt / c signal, impedance of an instrument to be tested is set according to input impedance matching of a logic analyzer, the LPDDR5 adopts a PODL level standard, and a voltage threshold value of the instrument to be tested is set as VDDQ / 2; and a special protocol decoder of the LPDDR5 is loaded in logic analyzer software. According to the invention, the problem of functional faults or performance bottlenecks existing in the final positioning digital system is solved.

An integrated circuit comprises logic circuits, a logic analyzer circuit, and a multiplexer circuit, which are configurable to provide the value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method for acquiring signals within an integrated circuit is provided. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting either the first or the second logic signal as the selected signal using the multiplexer circuit, and storing the value of the selected signal in the logic analyzer circuit within the integrated circuit.