49 results about "Logic analyzer" patented technology

The invention provides a logic analyzer trigger point accurate backtracking control method based on hotspot scoring and boundary learning, and the method comprises the steps: carrying out the popularity scoring according to the ratio of the number of channel compression units in each message segment to the length of an occupied byte, and screening out a hotspot candidate set; analyzing the structure of the hot area message segment and decoding, and realizing time alignment of a multi-channel sampling sequence in combination with the position offset adjusting quantity to form a synchronous sampling matrix; calculating local change intensity based on the matrix, introducing an inter-channel jump consistency constraint to construct a jump probability score, and accurately positioning a trigger point time index and a message segment where the trigger point time index is located; and finally, mapping a logic time position into a physical storage address in combination with a compression structure non-balance compensation parameter, so as to realize efficient reverse reading. According to the method, a mark or an additional address table does not need to be inserted, and high-precision backtracking control of the trigger point can be realized under the conditions of high compression ratio and multiple channels.

The invention relates to the technical field of digital signal processing, in particular to a USB4 high-speed logic analyzer based on an FPGA and a logic analysis method.The USB4 high-speed logic analyzer comprises an electrostatic discharge protection module, an external oscillator, an FPGA module, a high-speed data transmission channel, a USB4-to-PCIe controller and a USB4 interface; the USB4 interface is used for receiving an acquisition instruction sent from an external upper computer in a DMA mode, so that the FPGA-based USB4 high-speed logic analyzer analyzes the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used for controlling the FPGA-based USB4 high-speed logic analyzer to perform data acquisition on to-be-acquired equipment to obtain target data; data transmission is carried out between the FPGA module and the USB4 to PCIe controller through a high-speed data transmission channel; the FPGA module is used for transmitting target data to the USB4 to PCIe controller through a high-speed data transmission channel; the USB4 to PCIe controller is used for performing data conversion on the received target data to obtain a target data packet; and the USB4-to-PCIe controller and an external upper computer carry out data transmission through a USB4 interface in a DMA (Direct Memory Access) mode.

The invention relates to the technical field of digital signal processing, in particular to a single-chip high-speed logic analyzer based on an FPGA and a logic analysis method. The single-chip high-speed logic analyzer based on the FPGA comprises an electrostatic discharge protection module, an external oscillator, a system clock generation module, a dual-data-rate IO port, a pulse width modulation module, a reference voltage module, a first interface and a second interface. The first interface is a USB2.0 interface, the first interface is used for receiving an acquisition instruction of an external upper computer, so that the FPGA-based single-chip high-speed logic analyzer analyzes the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used for controlling the FPGA-based single-chip high-speed logic analyzer to perform data acquisition on to-be-acquired equipment; obtaining target data; the second interface is used for transmitting the target data to the external upper computer, the second interface is a preset SerDes interface, and the preset SerDes interface is used for realizing a data transmission function of a USB3.0 interface so as to perform high-speed data transmission.

The utility model relates to the technical field of integrated circuit testing, and particularly discloses an integrated circuit experiment testing device which comprises a shell. A microcontroller, and a digital oscilloscope, a function generator, a digital logic analyzer, a pattern generator, a virtual digital I / O interface, a front PCB panel and a plurality of test interfaces which are electrically connected with the microcontroller are arranged in the shell; the front end of the shell is provided with a voltage acquisition interface, a current acquisition interface, a display screen and a plurality of voltage output ports which are electrically connected with the front PCB panel, the bottom of the shell is provided with an air inlet, a cooling fan is arranged above the air inlet, and the middle part of the shell is provided with a middle air outlet. According to the utility model, a plurality of instruments and meters are integrated to carry out experimental testing, so that the device is convenient to operate and overhaul, smaller in size and small in occupied space, meets the requirement of carrying out rapid testing in a limited space, and is suitable for design, simulation, manufacturing and testing of integrated circuits and related experimental teaching and scientific research activities.

The invention discloses a system and a method for intelligently eliminating blockage of a preheater and a readable storage medium, and belongs to the field of blockage prevention of the preheater. The problem that an existing preheater anti-blocking method is difficult to meet the requirements of cement production for the anti-blocking technology in the aspects of high efficiency, low consumption and stability is solved. According to the technical scheme, the system comprises a logic analyzer, the logic analyzer is in communication connection with a DCS control system and a plurality of data acquisition instruments, the DCS control system is in communication connection with a plurality of ash removal devices, the ash removal devices are installed on cone parts, prone to crust and blockage, of all levels of the preheater, and each data acquisition instrument is electrically connected with a pressure detection device. According to the technical scheme, before the pressure value of an easy skinning area of the preheater reaches an early warning value, a control signal can be output to a DCS control system according to the change trend of high and low level signals, formation of caked materials is pre-judged and recognized in advance, formation of collapsed materials is avoided, and the preheater system is stably in a good heat exchange state; the anti-blocking device is applied to anti-blocking of the preheater.

The application provides a universal analog-digital converter testing device, which comprises at least an analog-digital converter testing module, a plurality of testing interface boards, a testing mainboard, an external power supply, a signal generator and a logic analyzer, the analog-digital converter testing module is sequentially connected to the testing interface boards and the testing mainboard, the external power supply, the signal generator and the logic analyzer are connected to each other and to the analog-digital converter testing module. The testing device can be modularly and independently operated, has strong expandability, can realize different functions in a simple form of building blocks, each component can be operated independently, and can be spliced when needed. The more the spliced module components are, the stronger the realized functions are. The testing device has simple operation and good maintainability, and can well solve the testing problem of analog-digital converters in practice.

The application discloses a bus fault reason determination method and electronic equipment, and relates to the technical field of computers, and comprises the following steps: if a target bus in a controller fails, determining a source pin corresponding to the target bus; determining a target pin corresponding to the source pin from a reserved pin; configuring the target pin based on configuration information of the target bus; configuring an interrupt mode of the source pin as an edge-triggered interrupt mode; when the source pin triggers an interrupt, reading a level signal of the source pin, setting an output level signal of the target pin to be consistent with the level signal of the corresponding source pin; and determining a fault reason of the target bus by collecting the output level signal of the target pin through a reserved terminal corresponding to the target pin by using a logic analyzer. The level signal of the source pin is copied to the target pin, and the logic analyzer is connected to the reserved terminal corresponding to the target pin, so that the technical effect of improving the fault reason determination efficiency is achieved.

The utility model discloses a verification device and a verification system of a field programmable gate array. The verification device comprises a configuration circuit, a configuration input end of which is connected with a serial port signal and a configuration output end of which outputs a first configuration signal and a second configuration signal; each first input end of the first signal selection circuit is connected with a first to-be-verified signal, a first high-order output end outputs a first high-order signal, and a first low-order output end outputs a first low-order signal; each second input end of the second signal selection circuit is connected with a first to-be-verified signal, a second high-order output end outputs a second high-order signal, and a second low-order output end outputs a second low-order signal; and the output end of the first signal combination circuit outputs the combined verification signal to a logic analyzer. According to the verification device provided by the utility model, free combination and selection of the signals to be verified are realized, the flexibility of observing the verification signals is improved, the consumption of internal resources of the FPGA is reduced, and the verification device is suitable for various use scenes.

An integrated circuit includes logic circuits, a logic analyzer circuit, and a multiplexer circuit configurable to provide a value of a signal selected from one of the logic circuits to the logic analyzer circuit. The logic analyzer circuit is configured to store the value of the signal selected by the multiplexer circuit. A method is provided for capturing signals within an integrated circuit. The method includes providing a first logic signal from a first logic circuit to a multiplexer circuit, providing a second logic signal from a second logic circuit to the multiplexer circuit, selecting one of the first logic signal or the second logic signal as a selected signal using the multiplexer circuit, and storing a value of the selected signal in the logic analyzer circuit in the integrated circuit.

The application discloses a kind of mixed radio frequency receiver group time delay test platform and method, including first, second vector signal source, first, second power divider, excitation signal generator, combiner, mixed radio frequency receiver of analog-digital, digital switching board, logic analyzer;First vector signal source simultaneously provides for second vector signal source and mixed radio frequency receiver reference clock, and second vector signal source generates OFDM modulated signal, and excitation signal is sent to logic analyzer by one end of second power divider, and triggers logic analyzer to prepare to accept test signal, and excitation signal is sent to second vector signal source by the other end of second power divider, and is superimposed to radio frequency receiver by combiner with OFDM modulated signal, and is accessed to logic analyzer by digital switching board.It is demodulated I / Q data information of test signal after logic analyzer receives excitation signal again, and calculates group time delay result.The application solves the problem of accurate measurement of group time delay of mixed radio frequency receiver of analog-digital.

The application relates to the technical field of data storage, and discloses a system for improving the test efficiency of a logic analyzer on a storage chip and a test efficiency method thereof, which comprises: an SOC chip connected with a test circuit board on one side and connected with the lower surface of a conversion board on the other side; wherein the first connecting area of the lower surface of the conversion board is used for connecting the SOC chip, and the second connecting area of the upper surface of the conversion board is used for connecting a to-be-tested storage chip; the first connecting area of the lower surface of the conversion board is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure comprises a plurality of first pins; the second connecting area of the upper surface of the conversion board is provided with a second pin structure corresponding to the pin arrangement of the to-be-tested storage chip, and each second pin structure comprises a plurality of second pins; and the conversion board comprises a plurality of metal layers stacked between the upper surface and the lower surface. The application improves the response speed of storage chip testing.

The utility model discloses a measurement interface assembly for a logic analyzer, belongs to the technical field of logic analyzer auxiliary instruments, and aims to solve the problem of unstable connection of a wiring interface between the logic analyzer and a tested device. Comprising an auxiliary seat, the auxiliary seat comprises a main body limiting part and a probe connecting line limiting part, the main body limiting part is arranged on the horizontal plane of the auxiliary seat, the auxiliary seat is connected with a logic analyzer through the main body limiting part, and the probe connecting line limiting part is arranged on a vertical arm of the auxiliary seat to fix a probe connecting line. And the stability of the probe interface is kept when external force dragging is avoided.

The present application relates to the field of data processing, and in particular to a real-time data reading and writing method for an on-chip logic analyzer and related devices. The method comprises: receiving first data collected in real time by a trigger unit; storing the first data in a first buffer currently in a write state, and analyzing and transmitting the second data through a second buffer currently in a read state; if the remaining storage space in the first buffer is lower than a storage capacity threshold, switching the first buffer from a write state to a read state, and switching the second buffer from a read state to a write state; analyzing and transmitting the first data through the first buffer switched to a read state, and storing the third data received after the switch in the second buffer currently in a write state, thereby realizing real-time data reading and writing of the on-chip logic analyzer. This method can not only ensure the integrity of the on-chip signal and improve the accuracy of the analysis results, but also greatly shorten the debugging time and improve the debugging efficiency.

The present invention discloses a method and system for comparing route status consistency from multiple data sources. The method includes: obtaining an interlocking table and a train control route information table; the interlocking table includes routes and first information corresponding to the routes, and the train control route information table includes routes and second information corresponding to the routes; obtaining real-time data for each route in the interlocking table from multiple data sources; using a logic analyzer to compare the interlocking table and the train control route information table for consistency; if the interlocking table and the train control route information table are consistent, using the logic analyzer to compare the first information corresponding to the route in the interlocking table with the real-time data of the same route for consistency; if the first information corresponding to the route in the interlocking table and the real-time data of the same route are inconsistent, the logic analyzer outputs a first analysis result and issues an alarm prompt; and the first analysis result indicates inconsistent interlock route status. The present invention can promptly detect data discrepancies between various interfaces and issue an alarm prompt.

The application provides an automatic testing system and method for an ADC chip, wherein a host computer generates a signal starting instruction and parameter information for configuring a tested ADC chip to perform automatic testing; a signal injector inputs a continuous sine wave signal to the tested ADC chip according to the signal starting instruction; the tested ADC chip acquires a digital signal formed after the sine wave signal is converted into a digital signal according to the parameter information; a logic analyzer captures the digital signal and uploads it to the host computer; and the host computer processes the digital signal to obtain a performance test result. The ADC chip is inputted with a continuous sine wave analog signal, and the test parameters are configured by the host computer, and the conversion result is read, so that the test efficiency is improved, the test cost is reduced, and the flexibility of the test is improved by configuring the parameters by the host computer.

This application relates to the field of data processing, and in particular to a data caching method and related device for an on-chip logic analyzer. The method includes: obtaining input data to be processed through a trigger unit; using a significant bit mask to mark corresponding data bits to be analyzed in the input data; comparing whether the data bits to be analyzed match a pattern mask to obtain a matching result of the data bits to be analyzed; controlling the data storage process of a custom storage array and a ping-pong buffer according to the matching result and / or the data caching method in which the trigger unit is located, so that target input data in the input data that meets the caching requirements is stored in the ping-pong buffer. This method can flexibly set trigger conditions according to specific analysis requirements, meet different debugging and analysis scenarios, more accurately capture data related to target events, improve the adaptability, debugging efficiency of the logic analyzer, and the utilization rate of storage resources, and provide strong support for in-depth data analysis.

A chip-embedded logic analyzer autonomously sequences between logic analysis scenarios, dynamically revising match criteria and match-responsive behavior as match conditions for each successive scenario are met. Through this cascading-scenario operation, the logic analyzer may log selected debug vectors as and / or after complex sequences of device conditions unfold, enabling substantially more targeted and sophisticated operational debugging than conventional trigger-and-log analyzers.

The invention relates to the technical field of data storage, and discloses a system and a method for improving the test efficiency of a logic analyzer on a storage chip, and the system is characterized in that one surface of an SOC chip is connected with a test circuit board, and the other surface of the SOC chip is connected with the lower surface of an adapter plate; wherein the first connection area on the lower surface of the adapter plate is used for connecting an SOC chip, and the second connection area on the upper surface of the adapter plate is used for connecting a storage chip to be tested; a first connection area on the lower surface of the adapter plate is provided with a first pin structure corresponding to the pin arrangement of the SOC chip, and the first pin structure comprises a plurality of first pins; a second connection area on the upper surface of the adapter plate is provided with second pin structures corresponding to the pin arrangement of the memory chip to be tested, and each second pin structure comprises a plurality of second pins; the adapter plate includes a plurality of metal layers stacked between the upper surface and the lower surface. According to the invention, the response speed of the memory chip test is improved.

The invention discloses a bus fault reason determination method and electronic equipment, and relates to the technical field of computers, and the method comprises the following steps: if a target bus in a controller fails, determining a source pin corresponding to the target bus; determining a target pin corresponding to the source pin from the reserved pins; based on the configuration information of the target bus, performing corresponding configuration on the target pin; configuring the interrupt mode of the source pin as an edge trigger interrupt mode; when the triggering of the source pin is interrupted, reading the level signal of the source pin, and setting the output level signal of the target pin to be consistent with the level signal of the corresponding source pin; and acquiring an output level signal of the target pin through the reserved terminal corresponding to the target pin by utilizing the logic analyzer, and determining a fault reason of the target bus. The level signal of the source pin is copied to the target pin, and the logic analyzer is connected with the reserved terminal corresponding to the target pin, so that the technical effect of improving the fault cause determination efficiency is achieved.

This application relates to the field of data processing, in particular to a method for multiplexing on-chip information and related devices. The method includes: obtaining on-chip information generated by each module in the system-on-chip and storing it in a first-in, first-out (FIFO) buffer that matches each module; according to a shared scheduling rule, transferring the on-chip information from their respective currently cached first-level FIFO buffers to a second-level FIFO buffer through a first-level polling arbiter; the second-level FIFO buffer is a common storage area shared by multiple modules; transferring the on-chip information from the second-level FIFO buffer to an on-chip logic analyzer through a second-level polling arbiter; processing the on-chip information through the on-chip logic analyzer to achieve multiplexing processing of on-chip information generated by multiple modules. This method can achieve multiplexing of on-chip information, effectively improve the debugging and tracing efficiency of the system-on-chip, and at the same time reduce system complexity and cost.

The utility model discloses a standard EMMC encapsulation adapter bottom plate, chip clamp and debugging tool suit, the standard EMMC encapsulation adapter bottom plate, including the board body, the board body includes the first side and second side on the thickness direction, the first side is suitable for with EMMC chip adaptation or simulation EMMC chip, the other side is provided with pin interface, by this, through setting debugging main body module, standard EMMC encapsulation adapter bottom plate, and the cooperation FPGA platform adapter soft board, EMMC chip clamp and logic analyzer interface, realized the integration of early chip parameter debugging, simulation and later whole platform verification debugging, utilize the standard EMMC encapsulation interface adaptation of standard EMMC encapsulation adapter bottom plate all EMMC platform's storage device, solved the poor problem of compatibility of existing debugging tool, greatly improved the debugging efficiency, reduced the debugging cost.

The present invention provides a performance analysis system and method for a memory. The performance analysis system includes a test board, to which a memory and a logic analyzer are connected. The logic analyzer is communicatively connected to the flash interface of the memory. A processing module is disposed on the test board and is communicatively connected to the storage interface of the memory. And a host is communicatively connected to the processing module and the logic analyzer. The host is used to send different test instructions to the memory through the processing module so that the memory performs different operations. Among them, the logic analyzer is used to obtain the instruction stream and response data sent by the firmware of the memory to the flash interface when the memory performs different operations, upload the instruction stream and response data to the host, and perform performance analysis on different memories. Through the performance analysis system and method for a memory provided by the present invention, the differences in the firmware of different memories can be analyzed to improve the performance of the firmware.

The invention belongs to the technical field of embedded development instruments, and relates to an integrated multifunctional debugger based on a microcontroller. The integrated multifunctional debugger comprises a shell, a main control board, a signal board, a screen, a battery and a rotary encoder. A microcontroller module, a power meter module, a spectrum analyzer module, a PWM output module, a development module and a Bluetooth module are integrated on the main control board, and bus voltage, current and power measurement, spectrum analysis, adjustable PWM signal output, user-defined function development and remote control operation through keyboard Bluetooth can be achieved. The signal board is provided with a logic analyzer module and a USBHUB module and is used for analyzing digital circuit signals. The debugger integrates multiple functions, and solves the problems that a traditional instrument is single in function, large in size and high in cost.

The invention discloses an independent FPGA online debugging device and debugging method, and belongs to the technical field of electronic device testing. The independent FPGA online debugging device comprises an upper computer, debugging equipment and a to-be-tested FPGA; the upper computer is used for instruction input and data visualization, and the debugging equipment is connected with the upper computer and is provided with an integrated controller, an integrated logic analyzer and a signal decoder; the to-be-tested FPGA is connected with the debugging equipment, and is provided with a signal encoder which is used for transmitting data to the debugging equipment. The debugging device is arranged, the integrated controller, the integrated logic analyzer and the signal decoder are arranged in the debugging device, the signal triggering, signal acquisition and signal storage processes performed in the FPGA to be tested are externally arranged in the debugging device, and the external debugging device breaks away from the constraint of the FPGA to be tested; according to the technical scheme, the data collection amount and the storage amount can be set according to the requirements of designers, the limitation of the performance of the to-be-tested FPGA is avoided, the number of sampling signals and the sampling depth can be greatly improved, and then the testing efficiency and the testing accuracy of the to-be-tested FPGA are improved.

A logic analyzer circuit includes a trace capture circuit to acquire N observation target signals from an observation target circuit when there is change in at least one of the N observation target signals and a buffer where signal data acquired by the trace capture circuit is stored. The signal data has a time stamp of an M-bit width indicating time of acquisition and state change data of an N-bit width corresponding to respective values of the N observation target signals. The signal data is data in a binary format having a fixed length of (M+N) bits.

The invention discloses a NAND Flash time sequence measurement method, device and equipment and a storage medium, and the method comprises the steps: welding a first PCB hard board with the size matched with a ball grid array (BGA) pin layout and a NAND Flash particle to be measured on a circuit board to be measured to replace the NAND Flash particle to be measured; the NAND Flash interface signal to be tested is transmitted to the second PCB hard board through the PCB soft board; connecting the logic analyzer to a connector of the second PCB hard board so as to carry out NAND Flash time sequence measurement; according to the NAND Flash interface time sequence testing method and device, efficient and accurate non-intrusive testing of the NAND Flash interface time sequence can be achieved, NAND Flash particles to be tested are seamlessly replaced, signal attenuation and crosstalk are effectively eliminated, the testing efficiency, reliability and data accuracy are remarkably improved, and the NAND Flash time sequence measuring speed and efficiency are improved.

The utility model provides a UART-CAN bus monitoring device for an automobile lamp, which is used for monitoring the state of the lamp and comprises a driving chip used for switching between the state of the lamp and a UART-CAN signal; the monitoring module is used for conversion between the UART-CAN signal and the USB signal; and the PC host is connected with the monitoring module and is used for reading the USB signal. The technical problems that in the prior art, in the monitoring process of capturing messages on a UART-CAN bus of an automobile lamp through a logic analyzer, automobile lamp controllers such as HCM or RCM need to read automobile lamp DID information and then analyze the state of the automobile lamp, so that the state of the automobile lamp is monitored, additional analysis is needed, and convenience and rapidness are not enough are solved.

The invention relates to the technical field of communication, in particular to a communication data real-time monitoring method and device, electronic equipment and a computer storage medium, and the method comprises the steps: receiving an original data stream of to-be-debugged equipment transmitted by a communication adaption module, recognizing the original data stream according to a protocol description file which is customized by a user and imported in advance, and transmitting the recognized original data stream to a communication adaption module; and determining a corresponding complete data frame, analyzing and checking the complete data frame to obtain structured data, and associatively storing the structured data and the original data stream. The problems that a universal serial port debugging assistant is low in efficiency and prone to making mistakes, a logic analyzer and the like are high in cost and poor in flexibility, a self-compiled temporary debugging program is long in development period and poor in reusability are solved, and the requirement for real-time monitoring of communication data in program development and debugging in the fields of an embedded system and the like can be effectively met.

The invention discloses multi-protocol video signal quality analyzer equipment. The multi-protocol video signal quality analyzer equipment comprises an FPGA (Field Programmable Gate Array) Virtex subsystem, an FPGA ZYNQ subsystem, a multi-channel high-speed video signal acquisition subsystem, an analog video signal input module, a power supply module, a clock module and a PC (Personal Computer). According to the invention, consistency test, protocol analysis and signal quality analysis of various mainstream video protocols such as LVDS, HDMI, DisplayPort, FPD-LINK and RGB in an avionics display system are realized, static image analysis, video stream dynamic detection and physical layer signal integrity test are supported, and high-precision signal acquisition and multi-protocol compatibility analysis capabilities are realized. The system integrates the functions of a high-speed oscilloscope, a logic analyzer, a protocol analyzer and a video signal generator, achieves the integrated, standardized and self-loopback test of multi-protocol video equipment, remarkably improves the test efficiency and precision, and has important engineering application values for the research and development verification, production quality inspection and fault diagnosis of display equipment.