Logic analyzer with serial bus protocol continuous triggering function

A technology of logic analyzer and serial bus, which is applied in the field of logic analyzer and can solve problems such as failure to provide

A technology of logic analyzer and serial bus, which is applied in the field of logic analyzer and can solve problems such as failure to provide

CN103995764AInactive Publication Date: 2014-08-20UNIV OF ELECTRONICS SCI & TECH OF CHINA

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  • Logic analyzer with serial bus protocol continuous triggering function
  • Logic analyzer with serial bus protocol continuous triggering function
  • Logic analyzer with serial bus protocol continuous triggering function

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0025] In order to better illustrate the content of the present invention, a brief introduction to the logic analyzer is firstly made. figure 1 It is a schematic diagram of a logic analyzer in the present invention. Such as figure 1 As shown, like common logic analysis, the channel part of the logic analyzer of the present invention adopts probe+comparator+level conversion+DAC (Digital to Analog Converter, digital-to-analog converter), and DAC is subjected to FPGA (Field-Programmable Gate Array , Field Programmable Gate Array) control the output threshold threshold level to the comparator; the comparator completes the analog-to-digital conversion, if the probe input voltage is greater than the threshold threshold, it is logic "1", otherwise it is logic "0"; The conversion chip converts level logic into LVDS (Low Voltage Differential Signal, low voltage differential signal), so that FPGA can accurately receive channel data. The system software running the logic analyzer in th...

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Abstract

The invention discloses a logic analyzer with a serial bus protocol continuous triggering function. Each continuous triggering module in an FPGA corresponds to a serial bus protocol. A clock timer in each continuous triggering module provides a clock overflow mark and clock data. Each continuous triggering state machine corresponds to a triggering mode. Channel data are received, and continuous triggering data collecting is triggered according to continuous triggering control words. In a next cycle after data collecting is completed, data storing enable signals are enabled to be effective. A data selector is triggered to select continuous triggering data to be output to a data splicing module. The data storing enable signals are selected to be output to the data selector. The data splicing module combines the clock data and the continuous triggering data and then output the data to the data selector. The data selector in the FPGA outputs corresponding continuous triggering data and data storing enable signals to an asynchronization FIFO module according to triggering type control words. The asynchronization FIFO module stores the continuous triggering data which are provided for an ARM processor to read. According to the logic analyzer, hardware is used for achieving continuous triggering of the serial bus protocol.

Description

technical field [0001] The invention belongs to the technical field of data domain testing, and more specifically relates to a logic analyzer with a serial bus protocol continuous trigger function. Background technique [0002] With the rapid development of digital electronic technology, the composition of modern digital electronic systems is becoming more and more complex, and the communication between various components of the system is increasingly dependent on a variety of digital buses, which also puts higher demands on the field of data testing. Require. [0003] As a traditional data domain test instrument, a logic analyzer plays an irreplaceable role in the development and testing of hardware logic, timing analysis, fault diagnosis and embedded software codes of digital electronic systems, and is indispensable for product development and functional maintenance of digital electronic systems. missing tools. In order to improve the test capability of logic analyzers f...

Claims

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Application Information

Patent Timeline
20 Aug 2014
Publication
CN103995764A
IPC
G06F11/25; G06F13/42
Inventors
戴志坚; 杨万渝