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591results about How to "Minimize degradation" patented technology

Captured synchronous DRAM fails in a working environment

A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate. The test assembly re-drives the system clocks with a phase lock loop (PLL) buffer to a memory module socket on the test assembly to permit timing adjustments to minimize the degradation to the system's memory bus timings due to the additional wire length and loading. The test assembly is programmable to adjust to varying bus timings such as: CAS (column address strobe) Latencies and Burst Length variations. It is designed with Field Programmable Gate Arrays (FPGAs) to allow for changes internally without modifying the test assembly.
Owner:GLOBALFOUNDRIES INC

Method and apparatus for monitoring polishing pad wear during processing

In a chemical-mechanical polishing (CMP) process, semiconductor substrates are rotated against a polishing pad in order to planarize substrate layers. The condition of the polishing pad directly affects the polishing rate of material removal and uniformity of removal from the semiconductor wafer. Conditioning of the polishing pad surface with an abrasive improves polishing uniformity and rates, however, it has the detrimental affect of removing a quantity of pad material. A method and apparatus for monitoring polishing pad wear during processing is developed to extend the pad's useful life, and maintain pad uniformity. This is accomplished in the present invention by measuring and monitoring the diminished pad thickness using a non-intrusive measurement system, and creating a closed-loop system for adjusting the chemical-mechanical polishing tool process parameters. The non-intrusive measurement system consists of an interferometer measurement technique utilizing ultrasound or electromagnetic radiation transmitters and receivers aligned to cover any portion of the radial length of a polishing pad surface. The measurement system is sensitive to relative changes in pad thickness for uniformity, and to abrupt changes such as detecting wafer detachment from the CMP wafer carrier.
Owner:INT BUSINESS MASCH CORP
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