The invention belongs to the field of security in a multi-
core system chip, and discloses a security
bus architecture for a multi-core Chiplet
chip system, which comprises five parts, namely an active intermediate layer, a functional
chip, a storage chip, a Core chip and a security chiplet, and is characterized in that the Core chip comprises a CPU core of the chip
system; the storage chip comprises a memory for storing data and codes; the functional chip comprises most peripherals and functional IPs; the active
interposer is used for connecting all the chiplets and realizing
access control of each chiplet, and the security chiplet is used for managing and controlling security configuration of the whole chip
system. When a chiplet provided by a supplier cannot be trusted, the secure
bus architecture can isolate and
restrict access to non-secure chiplets. A
bus architecture is realized in a secure active
interposer, and the access authority of each small chip in a chip system is configured by a secure small chip, so that the
data access of other small chips can be ensured to be controlled, and the system security is enhanced.