40 results about "Common word" patented technology

Described herein are interactive systems and methods for training language models using input from distributed computing environments. The system can receive prompts for a language model. Each prompt can include at least one common term corresponding to an intent relating to wagers. The system can determine that the language model has not been updated using training examples that include the at least one common term corresponding to the intent. The system can generate, using the prompts and additional information corresponding to the at least one common term, a set of training examples. Each set of training examples can include a respective prompt having the at least one common term. The system can update the language model using the set of training examples.

Computer-implemented method (500) for training a model to improve speech recognition, wherein the computer-implemented method comprises: Receiving (502) an utterance by one or more processors, wherein the receiving is performed by a virtual assistant in a specific node of the virtual assistant, wherein frequently occurring terms have been identified for the specific node over a period of time; Transcription (504) of the utterance into text by the one or more processors; Generating (506) a transcription confidence score based on transcription and audiometry by one or more processors; in response to the transcription confidence score being below a threshold, comparing (510) phonemes in the utterance with phonemes in at least one term from a list of frequently occurring terms by one or more processors; Generating a sound similarity score for phonemes in which at least one term from a list of frequently occurring terms is selected by one or more processors; and Replacing (512) the transcription with at least one term from the list of frequently occurring terms if the sound similarity score is above a threshold, by one or more processors.

According to one embodiment, a document classification apparatus includes a processing circuit. The processing circuit is configured to: acquire text content for each of logical elements for semi-structured document data including text data stored for each of the logical elements; select logical elements from the logical elements and generating logical element sets each including the logical elements; analyze text contents for the respective logical element sets and constructing respective word embedded spaces; select a first word embedded space and a second word embedded space including a common word shared with the first word embedded space from the word embedded spaces, and update the first word embedded space based on similarity to the common word in the second word embedded space; and output a classification result of the document data using the first word embedded space and embedding information of a feature quantity of a classification target.

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin-type words, a fin connector connecting the fin-type word line, and a common word line on the fin connector. The memory cell also includes a body line physically contacting one of the sidewalls of the semiconductor substrate and an insulating layer covering the body line, wherein the remaining sidewalls of the semiconductor substrate are partially covered by the fin word lines. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

The application relates to an entity matching method, system, device and medium based on word frequency, wherein the method comprises the following steps: performing word segmentation on aliases in a plurality of entity data to obtain a first word segmentation list and an alias word set, counting word frequency data of words in the alias word set, removing city words existing in the first word segmentation list to obtain a second word segmentation list, judging whether the words in the second word segmentation list are common words according to the word frequency data, processing the words in the second word segmentation list according to the judgment result, obtaining alias keywords corresponding to the aliases, and querying whether the alias keywords exist in a text corpus; if the alias keywords exist, an entity corresponding to the alias keywords is recognized in the text corpus. Through the application, the problems of missed recognition caused by alias simplification and alias synonym misjudgment are solved. The alias keywords are obtained based on the word frequency of the words in the aliases, entity matching is more accurate, and the accuracy of entity matching is improved.

The application provides an interview conversation audio processing method and device, electronic equipment and a storage medium, and relates to the technical field of AI interview. In the method, a pre-trained language model is used to extract first words and second words from a resume of an interview candidate and a standard answer of an interview question, wherein the first words and the second words include common words and non-common words related to a post to which the interview candidate applies; an intervention hot word table is generated according to the first words and the second words; and text conversion processing is performed on the interview conversation audio based on the intervention hot word table to obtain converted text corresponding to the interview conversation audio, so that when the interview candidate uses some professional terms or industry terms, the recognition error is reduced, and the accuracy of the obtained converted text is improved.

This invention discloses a large-scale watermarking method based on an improved red-green table, belonging to the field of large-scale security. Specifically, it first pre-divides commonly used words into a red list according to their frequency of occurrence, and includes commonly used standardized Chinese characters and uncommon characters not included in the list in a static exemption list. Then, when the user inputs a prompt, the large model generates an initial dynamic red list for token 0, and simultaneously generates candidate tokens for token 0. The final token 0 is then selected based on the dynamic red list. This process continues, generating the next dynamic red list for token 1 based on the final token 0, and selecting the final token 1. This continues until all user-input prompts have generated final tokens, forming a complete text with a watermark. When the user inputs text Q to be verified, the corresponding dynamic red list is reconstructed based on the initial key, and the frequency of tokens belonging to the dynamic red list in text Q is counted. If the actual frequency is <15% and z-score ≥2.58, the complete text Q is determined to contain a watermark. This invention improves the simplicity and security of large-scale watermarking.

To provide an information retrieval system configured to enable highly accurate information retrieval.SOLUTION: An information retrieval system is configured to: acquire a post text posted on a network, and analyze, for each information to be retrieved, the post text posted for the information, to extract words included in the post text; identify the frequency of the extracted words appearing in the post text and a co-occurrence relation between the extracted words, and set the words having the appearance frequency in the post text equal to or higher than a threshold, as frequent words; and set related words, which are words related to the frequent words, based on the co-occurrence relation. When retrieving information, the system retrieves information with the frequent words or related words set thereto, which matches a search word input by a user, and retrieves information while applying heavier weight to the frequent words than the related words.SELECTED DRAWING: Figure 13

It is proposed an in-memory computing (IMC) circuit (116), comprising:-an array comprising a matrix of memory cells (112) having a plurality of rows and columns wherein the memory cells (112) within the same column are connected by a common bit line and the memory cells within the same row are connected by a common word line, wherein the memory unit (112) is configured for storing weights of a trained neural network architecture, wherein the order of the weights is pre-disorganized; -at least one decoder (126) configured for outputting, using the key, a number of shift operations to be performed by each of the plurality of shift registers (128); -the plurality of shift registers (128) configured to shift an output of the array according to an output of the decoder (126).

Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

The invention discloses a semiconductor storage array, a semiconductor memory and a data processing method, and the semiconductor storage array comprises M rows and N columns of storage units, a power supply voltage line, M common word lines, N first selection gate lines and N bit lines, the m row and n column storage unit comprises a control sub-circuit and a storage sub-circuit; and the control sub-circuit is electrically connected with the mth common word line, the nth first selection gate line, the nth bit line and the connection node respectively, and is configured to store a signal of the nth bit line in the connection node during writing under the control of the signal lines of the mth common word line and the nth first selection gate line, or store the signal of the nth bit line in the connection node during reading. Reading a signal of the connection node to the nth bit line; and a storage sub-circuit electrically connected to the connection node and the power supply voltage line, respectively, and configured to store a voltage difference between signals of the connection node and the power supply voltage line.

A method, computer system, and computer program product are provided for automatically extracting semantically-similar question topics. A set of documents, wherein each document includes a plurality of words. One or more clusters of documents are identified in the set of documents based on a presence of common words in the documents of the one or more clusters. The one or more clusters are adjusted based on semantic similarity by adding or removing one or more documents from the one or more clusters. A topic is extracted from each adjusted cluster of documents.

A memory and an access method therefor, and an electronic device. The memory comprises at least one memory array, a plurality of common word lines, and a plurality of common bit lines. The memory array comprises a plurality of vertically stacked memory cell arrays and a plurality of vertical local bit lines. Each memory cell array comprises a plurality of local word lines extending in a second direction. The plurality of local word lines in a same memory cell array are divided into a plurality of word line groups, and different word line groups are connected to different common word lines. Each word line group comprises two local word lines connected to memory cells that are spaced one column apart from the word line group, each row of local bit lines corresponds to four common bit lines, and the common bit lines connected to the local bit lines connected to the memory cells connected to the local word lines in a same word line group are not adjacent.

An in-memory computation (IMC) circuit. The IMC circuit includes: an array comprising a matrix of memory cells having a plurality of rows and columns, wherein memory cells within the same column are connected through a common bit line and memory cells within the same row are connected through a common word line, wherein the memory cells are configured for storing weights of a trained neural network architecture, wherein the order of the weights is pre-scrambled; at least one decoder configured for outputting a number of shifting operations to be performed by each shifting register of a plurality of shifting registers using a secret key; the plurality of shifting registers configured for shifting outputs of the array according to the output of the decoder.

A memory and an access control method therefor, and an electronic device. The memory comprises: a plurality of memory arrays distributed on a substrate in the direction parallel to the substrate, a plurality of first word line gating sub-circuits (21), and a plurality of first word line gating control lines (HB_MAT_S); each memory array comprises a plurality of layers of memory cell arrays and a plurality of common word lines (CWLs), each memory cell array comprises a plurality of word lines extending in parallel, and the CWLs are connected to at least one word line; each CWL is connected to a corresponding word line driving terminal (HB_SWD) by means of the corresponding first word line gating sub-circuit (21); and a same word line driving terminal (HB_SWD) is separately connected to at least two CWLs of different memory arrays, and each first word line gating sub-circuit (21) is configured to electrically connect the corresponding word line driving terminal (HB_SWD) to the corresponding CWL or disconnect the corresponding word line driving terminal (HB_SWD) from the corresponding CWL under the control of the corresponding first word line gating control line (HB_MAT_S), wherein different CWLs of a same memory array are connected to different word line driving terminals (HB_SWD).

This invention discloses a Chinese spelling error correction method. The method increases training difficulty by replacing common words and characters in the original dataset with easily confused words and characters, thereby increasing the accuracy of model predictions. Simultaneously, the error correction model provided by this invention is optimized by integrating glyph and pinyin information based on the Macbert model, resulting in a more accurate error detection score and thus a more accurate identification of the corrected character. When the error correction model cannot obtain a suitable corrected character for a specific position in a sentence, this invention introduces a binary classification model to predict each candidate character at that specific position to obtain the corrected character, thereby enabling more accurate and efficient error correction of Chinese spelling.

The invention provides a semiconductor memory device and a refresh control method thereof to suppress unnecessary power consumption. The semiconductor memory device includes: a memory cell array having a plurality of segments, each segment having a plurality of normal word lines and a plurality of redundant word lines; and a row redundancy circuit configured to activate a non-defective one of the normal word lines and a non-defective one of the redundant word lines during a refresh operation; wherein activation and replacement of defective ones in the common word lines and defective ones in the redundant word lines are not performed in each section.

A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row and a plurality of columns, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track; and a plurality of first bit line metal tracks, wherein the plurality of first bit line metal tracks comprises a first group of first bit line metal tracks and a second group of first bit line metal tracks interposed in the first horizontal direction, and each of the first group is disposed on only one of the memory cells in the first row, and each of the second group is disposed on only one of the memory cells in the second row.

Embodiments of the present disclosure provide a memory device and a vertical fin-gate transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin type word lines and a common word line connecting the fin type word lines, where the fin type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite to the first sidewall of the semiconductor substrate, and an insulating layer embedding the body line. The body line is grounded to direct the accumulated charges out of the semiconductor substrate, thereby reducing the floating body effect in the memory cell.

The application discloses a sensitive data identification method and device, electronic equipment, medium and program product, and relates to the technical field of data security. The sensitive data identification method comprises the following steps: performing sentence segmentation on to-be-identified text data to obtain a plurality of short sentences; counting specific words in each short sentence which are not in a preset common word library, and recording the word frequency in a corresponding time residence matrix; performing word segmentation on each short sentence according to a preset word segmentation rule, determining a plurality of word segmentation paths corresponding to each short sentence; calculating the joint probability corresponding to each word segmentation path based on the word frequency of each time residence matrix, taking the word segmentation path with the highest joint probability as a target word segmentation path, and performing sensitive word retrieval on each word segmentation to obtain a sensitive data identification result. The technical scheme of the application solves the problem that the traditional sensitive word matching algorithm is prone to errors when processing Chinese text, thereby affecting the accuracy of sensitive data identification.

The invention discloses a semiconductor device and a manufacturing method thereof, electronic equipment and a working method, and the semiconductor device comprises a plurality of storage units, and each storage unit comprises a first storage subunit and a second storage subunit which are distributed at different layers; a plurality of word lines, one column of storage units arranged along a second direction is respectively connected with two word lines, one word line is connected with one column of first storage subunits, and the other word line is connected with one column of second storage subunits; the plurality of common word lines extend along a second direction and are connected with the first storage subunits and the second storage subunits at the same time; wherein the word lines and the common word lines are alternately distributed in the direction perpendicular to the substrate, and the common word lines are located between the two word lines. According to the semiconductor device, common gate control of the storage subunits can be achieved through the common word line, the space in the vertical direction is saved, the stacking number of the storage units is increased, and the manufacturing cost is saved.

This invention discloses a robust image semantic-driven steganography method based on a large language model and dual-channel modulation. By cleaning image descriptions, extracting image semantics and object cues, a large language model is jointly driven to generate steganographic text. A dual-channel feature modulation and multi-layer embedding mechanism is constructed to embed continuous floating-point secrets into the text through affine transformation. This invention can generate long steganographic text with consistent image semantics and low "illusion," and its statistical imperceptibility is lower than current methods. This method can still extract secret information well under four common word-level attacks, demonstrating high information transmission security and privacy protection capabilities.

Embodiments of the present disclosure provide a memory device and a vertical fin-gate transistor. The memory device includes a memory cell including a bit line, a word line above the bit line, and a semiconductor substrate on the bit line. The word line includes a plurality of fin type word lines, a fin connector connecting the fin type word lines, and a common word line on the fin connector. The memory cell also includes a body line physically contacting one of sidewalls of the semiconductor substrate and an insulating layer embedding the body line, where the fin type word lines partially cover others of the sidewalls of the semiconductor substrate. The body line is grounded to direct the accumulated charges out of the semiconductor substrate, thereby reducing the floating body effect in the memory cell.

The invention discloses a memory, an access method thereof and electronic equipment. The memory comprises at least one memory array, a plurality of common word lines and a plurality of common bit lines, the storage array comprises a plurality of layers of storage unit arrays which are vertically stacked and a plurality of vertical local bit lines; the memory cell array comprises a plurality of local word lines extending along a second direction, the plurality of local word lines of the same memory cell array are divided into a plurality of word line groups, and different word line groups are connected with different common word lines; each word line group comprises two local word lines connected with the storage units in the spaced columns, each row of local bit lines correspond to four common bit lines, and the common bit lines connected with the local bit lines connected with the storage units connected with the word lines of the same word line group are not adjacent. According to the scheme provided by the embodiment of the invention, the spacing between the local bit lines connected with the same word line is large, so that the interference between the bit lines is reduced, one common bit line can be connected with more bit lines, and the number of the common bit lines is reduced.

The invention discloses a memory, an access control method thereof and electronic equipment. The memory comprises a plurality of memory arrays, a plurality of first word line gating sub-circuits and a plurality of first word line gating control lines, wherein the memory arrays are distributed on a substrate in the direction parallel to the substrate; the storage array comprises multiple layers of storage unit arrays and multiple common word lines, the storage unit arrays comprise multiple word lines extending in parallel, and the common word lines are connected with at least one word line; the common word line is connected with a word line driving end through a first word line gating sub-circuit; the same word line driving end is respectively connected with at least two common word lines of different storage arrays, and the first word line gating sub-circuit is configured to electrically connect or disconnect the word line driving end and the common word lines under the control of a first word line gating control line; wherein different common word lines of the same storage array are connected to different word line driving ends. According to the scheme provided by the embodiment of the invention, different memory arrays can share the word line driver, and the number of hybrid bonding pads can be reduced.

Embodiments of the present disclosure provide a memory device and a vertical fin gate transistor. A memory device includes a memory cell, wherein the memory cell includes a bit line, a word line over the bit line, and a semiconductor substrate on the bit line. The word lines include a plurality of fin-type word lines and a common word line connecting the fin-type word lines, wherein the fin-type word lines partially cover a first sidewall of the semiconductor substrate. The memory cell also includes a body line physically contacting a second sidewall of the semiconductor substrate opposite the first sidewall of the semiconductor substrate, and an insulating layer covering the body line. The body line is grounded to direct accumulated charge out of the semiconductor substrate, thereby reducing floating body effects in the memory cell.

This invention discloses a method for programming three pages of user data in a memory array of a non-volatile memory system, comprising: converting each three-bit data pattern of the user data into a pair of representative two-bit data values; simultaneously programming two single-state memory cells with the first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of the two memory cell strings; and simultaneously programming two single-state memory cells with the second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.

The invention relates to the technical field of electrical digital data processing, in particular to a disguise word recognition method and device based on a dictionary tree and a medium. The method comprises the following steps: constructing a disguise word knowledge base; the disguise word knowledge base comprises the following candidate knowledge bases: a radical base, an emoticon mapping base, a similar word base, a homophone base, a homophone alphabet base and a phonetic alphabet mixed base; performing camouflage word expansion on keywords in a keyword set according to the camouflage word knowledge base to generate a camouflage word set; constructing a dictionary tree based on the disguise word set, and performing matching recognition on an input text in the dictionary tree; if the camouflage words exist in the input text, the recognized camouflage words are replaced with the corresponding common words; otherwise, judging that the camouflage words do not exist in the input text. The efficiency and accuracy of camouflage word recognition are improved.

A memory and an access method therefor, and an electronic device. The memory comprises: at least one memory array, a plurality of common word lines, and a plurality of common bit lines; the memory array comprises a multi-layer memory cell array and vertically extending bit lines; the memory cell array comprises: a plurality of memory cells and a plurality of word lines; the plurality of word lines are divided into a plurality of word line groups, and each word line group is connected to one common word line; each word line group comprises S word lines, and the S word lines are respectively connected to memory cells in alternate columns; each row of bit lines corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups comprising two adjacent bit lines, and every S bit line groups is respectively connected to S common bit lines corresponding to the row of bit lines.

A memory and an access control method thereof, and an electronic device, the memory comprising: at least one memory array, the memory array comprising a plurality of layers of memory cell arrays stacked vertically and a plurality of vertically extending local bit lines; the memory cell array includes: a plurality of local word lines extending in a second direction; the plurality of local word lines of the same memory cell array are divided into a plurality of word line groups, and each word line group comprises two local word lines connected with the memory cells in the spaced columns and connected with a common word line; each row of local bit lines corresponds to four common bit lines, and the common bit lines connected with the local bit lines connected with the storage units connected with the word lines of the same word line group are not adjacent; the common bit lines respectively connected with the two input ports of the sensing amplifier are two common bit lines of the same storage array, and the storage units connected with the two common bit lines are connected to different common word lines. According to the scheme provided by the embodiment of the invention, the wiring length of the common bit line can be reduced, and the coupling capacitance of the common bit line is reduced.