332 results about "Common word" patented technology

A method of displaying tab titles in a computer user interface receives a request to display a new tab in a tab area having a length. The new tab has a width and the new tab has a title having a length. The method determines a number of tabs to be displayed in the area and determines if the number of tabs to be displayed multiplied by the tab width is greater than the length of the tab area. If so, the method sets the tab width equal to the length of the tab area divided by the number of tabs. The method determines if the length of the title is greater than the tab width. If so, the method determines if the title has any words in common with any other titles of tabs. If so, the method deletes the common words from the titles, and displays the titles with the deleted common words in the tabs. The method may set a maximum number of tabs to be displayed in the tab area. The maximum number of tabs may be determined by the length of the tab area and a minimum tab width. If the number of tabs is greater than the maximum number of tabs is to be displayed, the method collapses some of the tabs in to a tab of tabs.

The present invention employs a memory cell structure in that one end of a variable resistance element (1) for storing information by change of electric resistance is connected to a source of a selection transistor (2) to form a memory cell (3) and, in a memory cell array (4), a drain of the selection transistor (2) is connected to a common bit line (BL) in a column direction, the other end of the variable resistance element (1) is connected to a source line (SL) and a gate of the selection transistor (2) is connected to a common word line (WL) in a row direction. In the memory cell structure, an operation of resetting data stored in the memory cell (3) is carried out for each of sectors including the plural memory cells (3) commonly connected to the source line (SL).

In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of the first dimension and the second dimension. The method allows the formation of very small phase-change memory cells.

A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a first dimension of a bottom electrode and a second dimension controlled by an etch process. The contact area is a product of the first dimension and the second dimension. The method allows the formation of very small phase-change memory cells.

A six transistor static random access memory (SRAM) cell with thin-film pull-up transistors and method of making the same includes providing two bulk silicon pull-down transistors of a first conductivity type, two active gated pull-up thin-film transistors (TFTs) of a second conductivity type, two pass gates, a common word line, and two bit line contacts. The bulk silicon pull-down transistors, two active gated pull-up TFTs, and two pass gates are connected at four shared contacts. In addition, the two bulk silicon pull-down transistors and the two active gated pull-up TFTs are formed with two polysilicon layers, a first of the polysilicon layers (poly1) is salicided and includes poly1 gate electrodes for the two bulk silicon pull-down transistors. A second of the polysilicon layers (poly2) includes desired poly2 stringers disposed along side edges of the poly1 gate electrodes, the desired poly2 stringers forming respective channel regions of the pull-up TFTs.

A memory cell array is included which is constituted by arranging the plurality of nonvolatile memory cells in a row direction and column direction respectively and arranging the plurality of word lines (WL) and the plurality of bit lines (BL) in the row direction and the column direction respectively in order to select a predetermined memory cell or a memory cell group out of the arranged nonvolatile memory cells, in which the memory cells are respectively constituted by connecting one end of a variable resistive element for storing information in accordance with a change of electrical resistances with the source of a selection transistor while in the memory cell array, the drain of the selection transistor is connected with a common bit line (BL) along the column direction, the other end of the variable resistive element is connected with a source line (SL), and the gate of the selection transistor is connected with the common word line (WL) along the row direction. According to the above memory cell configuration, it is possible to provide a nonvolatile semiconductor memory device capable of reducing voltage stresses applied to the variable resistive element of an unselected memory cell at the time of the reading and programming operations and securing a higher-reliability data holding characteristic.

A non-volatile random access memory (NVRAM) cell and method of fabrication thereof. Pairs of NVRAM cells, each including three FETs stacked in a NAND-like structure are formed vertically in silicon pillars. Source devices at the bottom of the pillar selectively provide ground to one of the cells. A floating gate extends upward from the source device's gate line. A control gate plate extending between adjacent pillars selectively provides a programming voltage to the control gate. Both the source gate and the control gate are capacitively coupled through silicon rich oxide to the floating gate. Polysilicon plugs between silicon pillars are word line gates for cells in adjacent pillars. A diffusion at the top of each pillar is a bit line contact for both cells at the pillar. Each pair of cells on a pillar are on a common bit line and a common word line. The word line, control gate and source gate line select individual cells in the pair.

A method of constructing a list of alternate transcripts from a recognized transcript includes generating a list of close call records, matching partial sub-histories from the recognized transcript with one of the history pairs stored in each of the records, and substituting the other of the history pairs for the partial sub-history of the recognized transcript. A close call record is generated each time a pair of partial hypotheses attempt to seed a common word. Each close call record includes history information and scoring information associated with a particular pair of partial hypotheses seeding a common word. Alternate transcripts are constructed by substituting close call histories for partial histories of the recognized transcripts, and also by substituting close call histories for partial histories of other alternate transcript.