274 results about "12-bit" patented technology

A single chip wireless sensor (1) comprises a microcontroller (2) connected by a transmit/receive interface (3) to a wireless antenna (4). The microcontroller (2) is also connected to an 8 kB RAM (5), a USB interface (6), an RS232 interface (8), 64kB flash memory (9), and a 32 kHz crystal (10). The device (1) senses humidity and temperature, and a humidity sensor (11) is connected by an 18 bit ΣΔ A-to-D converter (12) to the microcontroller (2) and a temperature sensor (13) is connected by a 12 bit SAR A-to-D converter (14) to the microcontroller (2). The device (1) is an integrated chip manufactured in a single process in which both the electronics and sensor components are manufactured using standard CMOS processing techniques, applied to achieve both electronic and sensing components in an integrated process.

An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For ⅓ rate, the relevant parameters are as follows: q=120, n_ldpc=64,800, k_ldpc=n_BCH=21600, k_BCH=21408 (12 bit error correcting BCH). For ¼ rate, the LDPC code has the following relevant parameters: q=135, n_ldpc=64,800, k_ldpc=n_BCH=16200, k_BCH=16008 (12 bit error correcting BCH). For ⅖ rate, the following parameters exist: q=108, n_ldpc=64800, k_ldpc=n_BCH=25920, k_BCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.

Methods, apparatus and systems for the display, on a remote node, of a three-dimensional (3D) image rendered on a host system in a first image format are described. In general, the 3D image is transformed into a second image format that is compressed (i.e., uses fewer data bits per pixel) relative to the first image format, (optionally) scaled to a screen size of remote node, and subsequently transferred to remote node for display. In instances, the transformation of the image from the first image format to the second image format and the optional scaling of the image to the screen size of remote node may be done in a graphics processing unit (GPU) on the host system. As an example, the first image format may be an RGB-based format, such as RGBA (32-bits per pixel) or standard RGB (24-bits per pixel) and the second image format may be a YUV-based format, such as YV12 (12-bits per pixel).

The invention discloses a wide dynamic processing method for a single-frame double-exposure image. The single-frame double-exposure image is a 12-bit original image comprising long exposure pixel blocks and short exposure pixel blocks simultaneously, and the method comprises the following steps of: (1) performing interpolation calculation, namely completing values of three channels of red, green and blue (RGB) for each pixel; (2) performing wide dynamic mapping, namely mapping and compressing the interpolated image; (3) segmenting image subjected to wide dynamic mapping to obtain two images only with the long exposure pixels and the short exposure pixels respectively; and (4) combining the two images by using a brightness distribution histogram interval segmenting method. Through the wide dynamic processing method for the single-frame double-exposure image, the pixels in two exposure modes in the single-frame image are combined, so that each part is subjected to proper exposure. Moreover, the single-frame image is only needed to be processed, the calculated quantity is reduced, and the wide dynamic image quality is improved through detection and correction of dead pixels and correction of the image.

The invention presents a scalable solution to encode the whole 12-bit raw video once to generate one bitstream that contains an H.264/AVC compatible base layer and a scalable enhancement layer. If a color bit depth scalable decoder is available at the client end, both the base layer and the enhancement layer sub-bitstreams will be decoded to obtain the 12-bit video and it can be viewed on a high quality display that supports more than eight bit; otherwise only the base layer sub-bitstream is decoded using an H.264/AVC decoder and the decoded 8-bit video can be viewed on a conventional 8-bit display. The enhancement layer contains a residual based on a prediction from the base layer, which is either based on bit-shift or based on an advanced bit depth prediction is utilized, wherein the advanced bit depth prediction method is a Smoothed Histogram method or a Localized Polynomial Approximation method.

For example, samples included in a frame constituted by a 3840×2160/24P,25P,30P/4:4:4,4:2:2,4:2:0/10,12-bit signal are mapped into first to fourth sub-images specified in the HD-SDI format, in units of two adjoining samples. Thus, it is possible to transmit through a transmission constitution for the HD-SDI format. The signal can be converted into serial digital data permitting a bit rate of 10.692 Gbps or the like and transmitted, and the receiving side can accurately reproduce original data.

The invention provides a wireless lock control system of an electronic lock based on an intelligent terminal and a method, the wireless lock control system is used in a U type glass door lock /bicycle lock, the wireless lock control system comprises a main control CPU, a wireless module, a fingerprint module, a touch key module, a distribution network button, a LED display circuit, a buzzer module, an alarm circuit, an EEPROM memory, a power supply circuit module and a motor driver circuit module which are connected with the main control CPU, the power supply circuit module includes a rechargeable device; wireless transmission is encrypted by an AES encryption mode, the touch key module can add a 6 to 12 bit password, and a 32 bit virtual password is set; the fingerprint module adopts a semiconductor fingerprint sensor, and can add 100 pieces of user passwords, and a door can be opened by direct pressing of a user fingerprint; the electronic door lock is connected with the wireless main control CPU to realize the real-time monitoring and remote control of a door lock device so as to achieve full intelligent user experience.

An optically coupled rotary encoder that is capable of measuring and encoding the angle of rotation of a rotating or stationary object. A polarizer rotates synchronously with the rotatable object and inputs broadband or single frequency unpolarized light. The polarizer outputs and directs polarized light towards a plurality of fixed analyzers and light detectors. Each fixed analyzer outputs and directs further polarized light towards one of the light detectors. Each light detector outputs an electrical signal to a phase processor based upon one attribute of the further polarized light. The phase processor outputs a phase angle with high resolution (>12 bit) with high accuracy and frequency (5 MHz). The system and method can operate in harsh environments having high temperatures, dirt and debris and is not susceptible to EMI/RFI.

The dynamic characteristic analysis method of real-time tendency of heart state includes: obtaining electorcardiac waveform with multipath electorcardiac amplifier and 12-bit A/D converter; forming time sequence related heart rate variation scatter diagram by means of space-time correlation technology and scatter diagram technology; extracting time sequence related characteristic parameters, short time-real time characteristic conversion illustration parameter and quantized space-time parameter indexes of characteristic illustration via automatic and manual interaction; classifying the illustration and quantized space-time parameters in artificial neural network; and describing dynamic characteristics and relevant invariance characteristics of heart rate variation in a nine-dimensional and a five-dimensional space with two independent curve surfaces and their boundary to represent the heart function.

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R′_i[10]=R′_i−1[0]⊕R′_i−1[2], and the permutation code forms, with an additional bit, a twelve bit address. The permutation code is changed from one OFDM symbol to another, thereby providing an improvement in interleaving the data symbols for a 4K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.

The invention provides a 12-bit intermediate-rate successive approximation type analog-digital converter and relates to the field of analog-digital converters. The 12-bit intermediate-rate successive approximation type analog-digital converter comprises a sampling network, a differential capacitor array connected with the sampling network, and a comparator circuit connected with the differential capacitor array, wherein the differential capacitor array comprises a first capacitor array connected with the positive-phase input end of the comparator circuit, and a second capacitor array connected with the negative-phase input end of the comparator circuit; both the first capacitor array and the second capacitor array are composed of 11 groups of binary-structured bit capacitors, and the bottom plates of the redundant capacitors of the second capacitor array are constantly connected with a common-mode voltage VCM. The 12-bit intermediate-rate successive approximation type analog-digital converter solves the problems of large capacitor area and high power consumption of a traditional binary capacitor type structure.

The present invention provides a PCI Bus Diagnostic Monitor which eliminates the need to hook up a logic analyzer and manually analyze the data passing on the PCI Bus. The present invention provides an accurate analysis of the PCI Bus master's utilization and/or latency time to acquire the PCI Bus by controlling a 12-bit counter and analyzing count values at appropriate times, e.g., between the time the PCI Bus request is output and the time that the data transfer begins, and the time between when the data transfer begins and when the data transfer ends. The data corresponding to a large number of data transfers may be buffered and analyzed to provide performance statistics relating to the PCI Bus. The analysis can be performed in lightly loaded, typically loaded, and heavily loaded PCI bus situations to fully and accurately test real-world capabilities of new peripherals, particular combinations of peripherals, and statistics relating to customized usage of a host system. The accurate statistics relating to the performance of the PCI Bus will also allow a system designer to assign and/or reassign PCI Bus priorities for various bus agents or peripherals.

The present disclosure relates to an apparatus and a method for transmitting muting information in a wireless communication system, and to an apparatus and a method for acquiring channel state using same. In an exemplary embodiment, muting information includes: a first data field, having a serving cell for receiving from peripheral cells in a multi-cell environment, at least one of a CSI-RS pattern, the number of CSI-RS antenna ports, a CSI-RS duty cycle, and CSI-RS transmission subframe offset information, and using same for expressing the cycle and the offset of muting subframes, which pertain to information on a resource block that can generate interference between the peripheral cells and CSI-RS; and a second data field for expressing a specific muting pattern, which must be muted within the muting subframes, having either 12 bits or 28 bits that display muting application in a bitmap format.

The invention discloses an automatic testing system of characteristic parameters of a direct-current breaker, which consists essentially of an analyzing and managing system controlled by a computer, a digital storage oscillograph and a program-controllable direct-current power source. 12-bit digital values that are output by a single chip microcomputer output 0 to 5V voltage through a digital-to-analog converting circuit, and the voltage is output to a phase-shifting-control full-bridge zero-voltage switching and a pulse modulation converting circuit through an isolating amplifier as well as to an EA+ end of a main chip, thus changing output current. The electromagnetic tripping action time is measured by a waveform breaking method and taking the largest constant short-circuit current in electromagnetic instantaneous acting tripping as the starting point of timing, thus having the advantages of high accuracy, efficiency and reliability.

Disclosed herein is a signal transmission apparatus, including: a two-pixel sampling out control section adapted to sample out, from among pixel samples extracted from a class image defined by a 3840×2160/100P, 119.88P, 120P/4:4:4, 4:2:2, 4:2:0/10-bit, 12-bit signal of the UHDTV1 wherein the pixel number of one frame exceeds a pixel number prescribed by the HD-SDI format, two pixel samples adjacent each other on the same line such that the pixel samples on each odd-numbered line of each frame are sampled out to a first sub image and a second sub image from among first to fourth sub images and the pixel samples on each even-numbered line of each frame are sampled out to the third sub image and the fourth sub image; a line sampling out control section; a field sampling out control section; a word sampling out control section; and a readout control section.

Novel subway stray current automatic monitoring system comprises that a plurality of stray current online automatic monitoring devices which are utilized as local monitoring slave machines are connected with a remote monitoring main machine. A switch power module, a data collecting module, an Ethernet communication module, an auxiliary hardware module and a man-machine interactive module are arranged on the same PCB printing circuit board around the processor of the system. The switch power module is internally-equipped with an EMC filter with high-performance. A/D transformation circuit employs bipolar and 12 bit A/D transducer MAX197 which is internally equipped with 8 ways sample-taking passages. The auxiliary hardware module comprises an EEPROM secondary permanent storage module, a hardware watchdog circuit, a self-contained battery calendar clock module and a serial port communication interface circuit. The invention simplifies the structure of the system, enables data sharing, information fusion and synergic observation among slave machines, which greatly strengthens the accuracy and tightness of the monitoring of the stray current, additionally, the cost of the monitoring device is reduced.