15 results about "12-bit" patented technology

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

This invention relates to the field of embedded motion control technology, specifically to a multi-channel servo smooth motion control system and method based on a real-time operating system, comprising: S1. Receiving multi-channel servo linkage instructions: receiving linkage control instructions containing multiple servo IDs, their respective target positions, and unified motion times, wherein the linkage control instructions are defined as: This invention employs an architecture of multiple PCA9685 chips cascaded through multiple I²C buses, combined with an external high-precision crystal oscillator. The system theoretically supports up to 48 independent servo controls, with a PWM resolution of 12 bits and a frequency error of less than 0.1%. This architecture fundamentally solves the pain point of limited timer resources in traditional microcontrollers, making it difficult to drive large-scale servo arrays, and provides a hardware foundation for high-channel-count applications such as complex bionic robots and multi-degree-of-freedom robotic arms.

An electronic device for performing a multiply and accumulate (MAC) operation includes at least one MAC unit, a memory, at least one 8b×8b operator, at least one 8b×4b operator, at least one 4b×4b operator, a bit shifter, an adder, at least one accumulator, and a processor. The processor receives first bit string data and second bit string data which include 12 bits, divides the first bit string data into 4 bits and 8 bits, divides the second bit string data into 4 bits and 8 bits, outputs two 8-bit results corresponding to activation 8-bit, weight 8-bit (A8W8) by using the bit shifter and a first accumulator on the basis of determining to output an A8W8 result, and outputs one 12-bit result corresponding to activation 12-bit, weight 12-bit (A12W12) on the basis of determining to output an A12W12 result.

The present disclosure relates to an apparatus and a method for transmitting muting information in a wireless communication system, and to an apparatus and a method for acquiring channel state using same. In an exemplary embodiment, muting information includes: a first data field, having a serving cell for receiving from peripheral cells in a multi-cell environment, at least one of a CSI-RS pattern, the number of CSI-RS antenna ports, a CSI-RS duty cycle, and CSI-RS transmission subframe offset information, and using same for expressing the cycle and the offset of muting subframes, which pertain to information on a resource block that can generate interference between the peripheral cells and CSI-RS; and a second data field for expressing a specific muting pattern, which must be muted within the muting subframes, having either 12 bits or 28 bits that display muting application in a bitmap format.

The invention discloses an SGPIO (Serial General Purpose Input / Output) unified coding method, system and device, and the method is characterized in that the method comprises the steps: powering on a server host, and completing the initialization of a CPLD (Complex Programmable Logic Device) and an SATA / SAS controller; a register and a counter are established, and an SGPIO input Data buffer register, an output Data buffer register and a Clock counter of the SGPIO are established in the CPLD; data frame bit length calculation: the CPLD waits for receiving the SGPIO signal, and calculates the bit length of the input data frame after receiving the input SGPIO signal; whether the bit length of a data frame is equal to 12 bits or not is judged, if the length of the data frame is 12 bits, Clock, Load and Data signals of input SGPIO are directly transmitted to an output IO pin in a transparent mode, and the SGPIO signals of an output interface are completely equal to the SGPIO signals input by the CPLD; and if the data frame length is greater than 12 bits, the signal is processed, so that the SGPIO data of the output port is unified into 12-bit data. By unifying the SGPIO data of the output port into 12 bits, the problem that the bit lengths of SGPIO signals of different devices or interfaces are inconsistent is effectively solved, and the compatibility and standardization degree of the system are remarkably improved.

This invention discloses an S-box generation method with optimal algebraic immunity and high nonlinearity, belonging to the field of cryptography. The invention comprises: a control signal register receiving and storing control signals from a nonlinear transformation controller; an information memory receiving and storing 8 bits of information to be processed; an expansion transformer expanding and transforming the information to be processed into 12 bits; a segmenter segmenting it into 6-bit groups LT and RT; the nonlinear transformation controller reading its control signal from the control signal register; if the signal is 1, the control sequence LT enters nonlinear transformation unit 1, and the sequence RT enters nonlinear transformation unit 2; if the signal is 0, the opposite occurs; a connector connecting the output sequences of nonlinear transformation units 1 and 2 yields the information output Y, which is stored in the information memory. This invention, while ensuring optimal algebraic immunity, high nonlinearity, and balance of the S-box, increases the difficulty of deciphering encrypted information by thoroughly obfuscating the plaintext.

The utility model discloses an intelligent Bluetooth power roller control circuit which comprises a motion detection module, a data processing module, a display module and a power module. The motion detection module is a high-precision Hall sensor and is used for detecting the motion trail, the rotation frequency and the displacement distance of the power roller in real time; the data processing module adopts a low-power-consumption MCU processor and is based on an ArmCortex-M0 kernel, the dominant frequency is not lower than 48 MHz, and at least 28 GP IO interfaces are configured; the display module is a low-power-consumption LCD (Liquid Crystal Display) screen and is connected with the MCU processor through a driving chip; the MCU processor integrates a Bluetooth communication module, wirelessly transmits motion data to an external terminal device, collects signals through a Cortex-M0 core MCU with a 48 MHz dominant frequency and a 12-bit ADC at a 200 Hz high sampling rate, calculates the motion data in real time and eliminates mechanical vibration interference in combination with a sliding window algorithm and a three-point positioning method, guarantees data real-time performance and accuracy, meanwhile, GPIO interface distribution is clear, and the motion data can be transmitted to the external terminal device in a wireless mode. The circuit structure is clear, and hardware debugging and function expansion are facilitated.

To satisfactorily transmit uncompressed RAW data between devices. A transmission unit transmits uncompressed RAW data to an external device via an HDMI transmission path. For example, the uncompressed RAW data is uncompressed RAW data in a Bayer layout. Furthermore, for example, the bit depth of each pixel of the uncompressed RAW data is 16 bits, and the transmission unit transmits the uncompressed RAW data using the YC 12 bit transfer mode. For example, the transmission unit transmits metadata related to the uncompressed RAW data together with the uncompressed RAW data.

The invention discloses a communication method and system based on a Beidou short message, and relates to the technical field of Beidou communication, and the method comprises the steps: a transmitting end obtains a to-be-communicated text, and encodes the to-be-communicated text based on the corresponding relation between 12 bits and Chinese characters, thereby obtaining an encoded byte code; the sending end performs subpackage processing on the byte code according to a preset communication protocol to generate a plurality of communication packets; the sending end sends the plurality of communication packets to a receiving end in sequence through a Beidou short message; a receiving end receives a plurality of communication packets, and obtains a complete coding byte code based on the preset communication protocol; and based on the corresponding relationship between 12 bits and Chinese characters, the receiving end decodes the complete coding byte code to obtain a to-be-communicated text. On the basis of the traditional coding format, the corresponding relation between the byte codes and the common Chinese characters is extracted, and the Chinese characters are compressed and expressed by 12-bit coding, so that more Chinese characters can be transmitted under the same byte number, and the single-time transmission efficiency is improved.

An external speech processor of a cochlear implant based on a clock image method-based cochlear implant data transmission protocol according to an embodiment defines an NP2 interface and an NP2 protocol to stably capture NP2 data transmitted using an NP2 clock internally restored at a period inferred by a conversion chip from data transmitted by a speech processing chip even in a situation where a clock period of the speech processing chip and a clock period of the conversion chip are not related to each other at all. In addition, the external speech processor of a cochlear implant based on a clock image method-based cochlear implant data transmission protocol according to the embodiment stores the amount of data period variation during 12 bits in a buffer through a clock image, which is a snap-shot for a predetermined section, and repeatedly uses same. In the embodiment, all count values are stored as one data set and the stored data set is used. That is, in the embodiment, it is assumed that the sum of period changes of each bit during 12 bits and the sum of period changes of each bit during next 12 bits will have the same amount of variation, and each bit during the next 12 bits is captured at different time points according to the period of each bit stored in the buffer.

Particular embodiments provide a variable, BitDepth, that may be set at a value based on a number of bits used to represent pixels in pictures of a video. The variable may be used in syntax elements in HEVC, such as the HEVC range extension, but other coding standards may be used. By using the variable, different resolutions for the video may be accommodated during the encoding and decoding process. For example, the number of pixels in the pictures may be represented by 8 bits, 10 bits, 12 bits, or another number of bits depending on the resolution. Using the BitDepth variable in the syntax provides flexibility in the motion estimation and motion compensation process. For example, syntax elements used in the weighted prediction process may take into account different numbers of bits used to represent the pictures.

The application discloses a self-defined frequency offset compensation method and system based on a CSS modulation network. The method comprises the following steps: initialization setting, including self-defined redundancy bits, selection of a spread spectrum factor SF, a bandwidth BW and a coding rate CR; constructing a data packet and transmitting after interleaving coding, wherein the self-defined redundancy bits are inserted in the process of coding the data packet, the header Header of the data packet is set to 12 bits, the first 8 bits are used for indicating the length of the data packet, the 9th-11th bits are used for indicating the selected coding rate, and the 12th bit is a parity check bit; at a receiving end, the self-defined redundancy bits are used as a reference signal to calculate the offset of each symbol in each data packet, and then the offset of the data packet is corrected and supplemented at a symbol level. The application solves the problem of severe frequency offset of the CSS modulation network in a harsh environment, and guarantees the stability of network performance.

Particular embodiments provide a variable, BitDepth, that may be set at a value based on a number of bits used to represent pixels in pictures of a video. The variable may be used in syntax elements in HEVC, such as the HEVC range extension, but other coding standards may be used. By using the variable, different resolutions for the video may be accommodated during the encoding and decoding process. For example, the number of pixels in the pictures may be represented by 8 bits, 10 bits, 12 bits, or another number of bits depending on the resolution. Using the BitDepth variable in the syntax provides flexibility in the motion estimation and motion compensation process. For example, syntax elements used in the weighted prediction process may take into account different numbers of bits used to represent the pictures.

The invention discloses a method for constructing a pseudorandom sequence of a conservative hyperchaotic system based on an FPGA (Field Programmable Gate Array), which belongs to the field of information security, and comprises the following steps: firstly, respectively constructing a four-dimensional conservative hyperchaotic system and a five-dimensional conservative hyperchaotic system, and then fixing initial values and parameters of the two chaotic systems; the method comprises the following steps of: intercepting low 12 bits output by two hyperchaotic signals as a random source of a pseudo-random sequence generator, dividing each dimension of output signal into high 6 bits and low 6 bits, executing exclusive OR and connection operations, and finally combining results to obtain final output of a pseudo-random sequence. Two conservative hyper-chaotic systems are adopted to design the pseudo-random sequence generator, the safety and throughput are improved by means of the high sensitivity of the pseudo-random sequence generator to an initial value and the pseudo-random characteristic of the pseudo-random sequence generator, the randomness of the sequence is guaranteed by extracting low 12 bits output in each dimension, the utilization rate of chaotic signals is improved, the use of a multiplier is reduced by adopting simple bit operation, and the cost is reduced. Resource occupation is reduced, hardware implementation is facilitated, and the advantage of large throughput is achieved.

The present disclosure relates to an apparatus and a method for transmitting muting information in a wireless communication system, and to an apparatus and a method for acquiring channel state using same. In an exemplary embodiment, muting information includes: a first data field, having a serving cell for receiving from peripheral cells in a multi-cell environment, at least one of a CSI-RS pattern, the number of CSI-RS antenna ports, a CSI-RS duty cycle, and CSI-RS transmission subframe offset information, and using same for expressing the cycle and the offset of muting subframes, which pertain to information on a resource block that can generate interference between the peripheral cells and CSI-RS; and a second data field for expressing a specific muting pattern, which must be muted within the muting subframes, having either 12 bits or 28 bits that display muting application in a bitmap format.