18results about "Fail-safe circuits" patented technology

The utility model relates to interface circuit technical field, concretely relates to an interface circuit with protection function, including connector J1, connector J2, thyristor Q2, resistance R2, resistance R4 and stabilivolt diode VT2, the anode of thyristor Q2 is connected with connector J1 and connector J2 respectively, the cathode of thyristor Q2 is grounded, the grid of thyristor Q2 is connected with one end of resistance R2, the other end of resistance R2 is grounded through resistance R4, the other end of resistance R2 is connected with the anode of stabilivolt diode VT2, the cathode of stabilivolt diode VT2 is connected with the anode of thyristor Q2, the utility model discloses that the overvoltage trigger loop that stabilivolt diode VT2 and thyristor Q2 constitute, realize overvoltage threshold accurate control, when overvoltage, thyristor Q2 fast conduction, bypass and form big current loop to load, instantaneous fuse F1, cut off power supply thoroughly, avoid continuous overvoltage damage load.

The invention discloses a voltage comparator circuit, a chip and electronic equipment, and the voltage comparator circuit comprises a differential comparison circuit which is used for receiving an input voltage signal and a reference voltage signal, and outputting a differential signal based on the input voltage signal and the reference voltage signal; the output buffer circuit is connected with the differential comparison circuit and is used for outputting an output voltage signal of the voltage comparator circuit based on the differential signal; the hysteresis control circuit is connected with the output buffer circuit and the differential comparison circuit and is used for outputting an adjusting signal based on the output voltage signal so as to adjust the threshold voltage of the differential comparison circuit; and the clamping circuit is connected with the differential comparison circuit and is used for protecting the differential comparison circuit so as to prevent the differential comparison circuit from overvoltage breakdown. The voltage comparator circuit can bear dynamic high-voltage impact.

The invention relates to a fail-safe input-output circuit. A circuit includes an input-output, a power supply terminal (113), a reference terminal (117), transistors (122) and (123), a driver circuit (120), and a bias generation circuit (125). The driver circuit (120) includes: a first inverter having an output; a second inverter having an input, an output, and a first power supply input and a second power supply input; and a transfer gate having an input, an output, and an enable input. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transfer gate is coupled to an output of a driver circuit (120), the first supply input of the second inverter is coupled to the output of the transfer gate, and the second supply input of the second inverter is coupled to the output of the driver circuit (120). And the second supply input of the second inverter is coupled to a reference terminal (117).

A first circuit has a predetermined function with an output that has a small dependence on a certain operation condition. A second circuit has the same function as that of the first circuit with an output that has a large dependence on the certain operation condition. When the first circuit is operating normally, the main circuit operates according to the output of the first circuit. The main circuit is capable of generating a detection signal that indicates the certain operation condition based on a relative relation between the output of the first circuit and the output of the second circuit.

Embodiments of the present application provide a method and system for controlling stable operation of an isolation device, comprising: obtaining a sampling value of a sampling port; adjusting a duty cycle of a pulse width signal output by a control port according to the sampling value to obtain a target pulse width signal; and controlling stable operation of the isolation device by the target pulse width signal. By the present application, the problem of power waste caused by the need for continuous high level of weak point equipment in related art is solved.

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

The invention discloses a receiver, a digital isolator and a disconnection protection method thereof. The digital isolator includes a transmitter and a receiver connected via a differential line. The receiver comprises an amplifier, an envelope detector and a driver which are connected in sequence, and the envelope detector is configured to perform envelope detection on a differential input signal received by the receiver so as to generate a corresponding envelope signal; the switch module is configured to control the on-off state of an input signal path of the envelope detector; and the broken line protection module is used for detecting the line fault of the differential line according to the signal change of the envelope signal in different on-off states during the power-on reset period, and stopping providing the output signal when the line fault exists in the differential line.

The invention relates to the technical field of integrated circuit design, and discloses a high-reliability low-overhead dual-node flipping resistant latch and a D flip-flop. The latch adopts a composite redundant architecture and comprises a first two-input Mueller C unit, a second two-input Mueller C unit, a three-input Mueller C unit, a plurality of transmission gates and phase inverters, and three parallel storage paths are constructed. And when the Mueller C unit inputs are inconsistent, a high-resistance-state error interception mechanism is output to isolate errors so as to realize complete tolerance of single-node upset (SNU) and various double-node upset (DNU). The working state of the latch is controlled by a clock signal, transmission delay is reduced through a high-speed straight-through path in a transparent mode, and data are latched through a cross coupling feedback loop in a holding mode. The structure is compact, the area is effectively reduced, the power consumption overhead is effectively reduced, and the power consumption-delay-area product (PDAP) competitiveness is outstanding. In addition, an edge-triggered D flip-flop can be formed based on the latch.

A circuit includes an input-output, a supply terminal, a reference terminal, a high-side transistor, a low-side transistor, a driver, and a bias generation circuit. The driver circuit includes a first inverter having an output, a second inverter having an input, an output, and first and second supply inputs, and a transmission gate having an input, an output, and first and second enable inputs. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transmission gate is coupled to the output of the driver, the first supply input of the second inverter is coupled to the output of the transmission gate, and the second supply input of the second inverter is coupled to a reference terminal.

This application relates to the field of power electronics technology and discloses a drive holding circuit, electronic device, and vehicle. The drive holding circuit includes a first circuit and a second circuit. The first circuit is adapted to receive a power supply signal and a control signal, and to conduct when the control signal switches from invalid to valid, thereby generating a drive signal based on the power supply signal and latching the drive signal to keep it valid. The second circuit is adapted to receive the drive signal and a safety logic signal, and to release the latch of the drive signal when the control signal and the safety logic signal meet preset conditions, causing the drive signal to fail. This application can maintain a valid drive state even when a drive signal source failure occurs, thereby effectively avoiding the impact of a single fault on the function of the electronic device and significantly improving system reliability.

The application provides a data transmission circuit and a communication module, comprising: a current mode driving circuit and a voltage mode driving circuit; the current mode driving circuit is configured to be turned on when a first mode selection signal is received; the voltage mode driving circuit is configured to be turned off when a second mode selection signal is received; the current mode driving circuit comprises two groups of current mode semiconductor switching elements, and can control the first group of current mode semiconductor switching elements or the second group of current mode semiconductor switching elements to be opened according to different driving signals; the voltage mode driving circuit comprises two voltage mode semiconductor switching elements, and can control the first voltage mode semiconductor switching element or the second voltage mode semiconductor switching element to be opened according to different driving signals. The scheme can realize single-chip integrated voltage type TX and current type TX two driving modes, so that users can flexibly switch according to requirements.

This disclosure relates to a voltage tracking circuit. Various embodiments described herein relate to a device having an output pad configured to provide an output pad voltage. The device may include a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage. The device may include an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.

A signal transmission device for transmitting a power transistor drive signal to a secondary circuit system from a primary circuit system while insulating the interval between the primary circuit system and the secondary circuit system, said device having: a first abnormality detection circuit configured so as to detect abnormalities in the primary circuit system; a second abnormality detection circuit configured so as to detect abnormalities in the secondary circuit system; a first signal transmission path configured so as to transmit detection results of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while insulating the interval between the primary circuit system and the secondary circuit system; and a self-diagnosis circuit configured so as to self-diagnose the first abnormality detection circuit, the second abnormality detection circuit and the first signal transmission path.

A circuit includes an input-output, a supply terminal, a reference terminal, a high-side transistor, a low-side transistor, a driver, and a bias generation circuit. The driver circuit includes a first inverter having an output, a second inverter having an input, an output, and first and second supply inputs, and a transmission gate having an input, an output, and first and second enable inputs. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transmission gate is coupled to the output of the driver, the first supply input of the second inverter is coupled to the output of the transmission gate, and the second supply input of the second inverter is coupled to a reference terminal.

Perform a proper diagnosis of the signal transmission device. [Solution] The signal transmission device transmits a drive signal for a power transistor from the primary circuit system to the secondary circuit system while insulating the primary circuit system from the secondary circuit system, and includes a first abnormality detection circuit configured to detect an abnormality in the primary circuit system, a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system, a first signal transmission path configured to transmit the detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while insulating the primary circuit system from the secondary circuit system, and a diagnostic circuit configured to diagnose the first abnormality detection circuit, the second abnormality detection circuit, and the first signal transmission path, respectively.

The invention discloses a dual-redundancy signal interlocking logic conversion circuit. The dual-redundancy signal interlocking logic conversion circuit comprises an interface input conversion circuit, a logic voting circuit, a driving circuit and a relay circuit, wherein the interface input conversion circuit comprises a plurality of groups of input and output interface chips, each group of input and output interface chips respectively outputs two paths of outputs, and each path of output end is respectively connected with one path of input end of the logic voting circuit; each path of input end of the logic voting circuit corresponds to one path of output end and is connected with one path of input end of the driving circuit; each path of input end of the driving circuit corresponds to one path of output end and is connected with one path of input end of the relay circuit. Through output anti-logic design, existing logic is converted into pre-stage logic which is normally open logic and closed logic after action, logic conversion locking is carried out through the logic voting circuit, and signals after logic conversion and locking are output, so that false triggering of a post-stage device caused by missing of a pre-stage device in interlocking control is avoided, and the reliability of interlocking control is improved. And the safety of the interlocking control process is ensured.

This application provides an interface circuit and an interface device. The interface circuit includes a first protection branch and a second protection branch; both the first end of the first protection branch and the first end of the second protection branch are electrically connected to a positive power supply voltage; the second end of the first protection branch is electrically connected to a first communication pin, and the second end of the second protection branch is electrically connected to a second communication pin; the first protection branch is used to limit the voltage of a first internal node to less than or equal to a first voltage threshold and the voltage of a second internal node to less than or equal to a second voltage threshold when the first communication pin is short-circuited to the bus power supply VBUS pin; the second protection branch is used to limit the voltage of a third internal node to less than or equal to a third voltage threshold and the voltage of a fourth internal node to less than or equal to a fourth voltage threshold when the second communication pin is short-circuited to the bus power supply VBUS pin. This interface circuit can achieve high-voltage short-circuit protection.