44results about "Fail-safe circuits" patented technology

An electronic device and a method for monitoring a driver's output signal are provided. The electronic device includes: a driver connected to a pin, receiving an input signal, and outputting an output signal to the pin in response to the input signal; a core circuit that transmits the input signal to the driver; and a monitoring circuit that receives the input signal and an output signal and detects a stagnation voltage state of the output signal based on the input and output signals. The monitoring circuit includes: a first detection circuit that detects a stagnation voltage state when the input and output signals are logically incorrect; a second detection circuit that detects a stagnation voltage state when the input and output signals are logically correct and the output signal is at a low level; and a third detection circuit that detects a stagnation voltage state when the input and output signals are logically correct and the output signal is at a high level.

An application specific integrated circuit, ASIC, package for use in an electrical or electronic device is disclosed. The ASIC package comprises a plurality of functional units (411, 412, 413), a plurality of terminals, and a plurality of switches (421, 422). The plurality of switches are connected in series along a portion of an electrical current path within the ASIC package, and at least one of the functional units comprises switching control logic configured to independently switch each of the switches between an open-circuit state and a closed-circuit state. Additionally, at least one of the functional units is configured to provide a monitoring function comprising determining occurrence of a fault condition associated with operation of the electrical or electronic device, and to transmit a fault trigger signal to the switching control logic in response to a fault condition being determined. The switching control logic is configured to trigger an open-circuit state of at least one of the plurality of switches in response to receiving the fault trigger signal. This can provide enhanced safety by enabling the isolation of the ASIC package from power sources (e.g. a charger and / or a battery) and / or a load (e.g. a heater) if a fault is determined by a safety-related functional unit of the ASIC package.

The utility model relates to interface circuit technical field, concretely relates to an interface circuit with protection function, including connector J1, connector J2, thyristor Q2, resistance R2, resistance R4 and stabilivolt diode VT2, the anode of thyristor Q2 is connected with connector J1 and connector J2 respectively, the cathode of thyristor Q2 is grounded, the grid of thyristor Q2 is connected with one end of resistance R2, the other end of resistance R2 is grounded through resistance R4, the other end of resistance R2 is connected with the anode of stabilivolt diode VT2, the cathode of stabilivolt diode VT2 is connected with the anode of thyristor Q2, the utility model discloses that the overvoltage trigger loop that stabilivolt diode VT2 and thyristor Q2 constitute, realize overvoltage threshold accurate control, when overvoltage, thyristor Q2 fast conduction, bypass and form big current loop to load, instantaneous fuse F1, cut off power supply thoroughly, avoid continuous overvoltage damage load.

The invention discloses a voltage comparator circuit, a chip and electronic equipment, and the voltage comparator circuit comprises a differential comparison circuit which is used for receiving an input voltage signal and a reference voltage signal, and outputting a differential signal based on the input voltage signal and the reference voltage signal; the output buffer circuit is connected with the differential comparison circuit and is used for outputting an output voltage signal of the voltage comparator circuit based on the differential signal; the hysteresis control circuit is connected with the output buffer circuit and the differential comparison circuit and is used for outputting an adjusting signal based on the output voltage signal so as to adjust the threshold voltage of the differential comparison circuit; and the clamping circuit is connected with the differential comparison circuit and is used for protecting the differential comparison circuit so as to prevent the differential comparison circuit from overvoltage breakdown. The voltage comparator circuit can bear dynamic high-voltage impact.

A PFC channel failure fault detection and device protection circuit, method, device, and medium are disclosed. The circuit comprises a channel current detection module for detecting and comparing three channel currents with a set current threshold; a PWM wave logic operation module composed of three trigger integrated modules, each identically structured and containing two D flip-flops. Each trigger integrated module receives PWM waves from the driver chip pin and the switch control pin of the corresponding channel of the PFC circuit at its two input terminals, respectively. The trigger integrated modules perform logic operations on these PWM waves. A processor determines the type of abnormality in each PFC channel with no channel current based on the results of the logic operations and adjusts accordingly based on the total input current. The present invention reduces the input current by lowering the device frequency to below the current rating of the open channel, thereby controlling the current in the event of a PFC channel failure and preventing device damage.

A signal transmission device that transmits a driving signal for a power transistor from a primary circuit system to a secondary circuit system while isolating between the primary and secondary circuit systems includes: a first fault detection circuit configured to detect a fault in the primary circuit system; a second fault detection circuit configured to detect a fault in the secondary circuit system; a first signal transmission path configured to transmit the result of detection by the second fault detection circuit from the secondary circuit system to the primary circuit system while isolating between the primary and secondary circuit systems; and a self-test circuit configured to perform a self-test on each of the first fault detection circuit, the second fault detection circuit, and the first signal transmission path.

The invention relates to a fail-safe input-output circuit. A circuit includes an input-output, a power supply terminal (113), a reference terminal (117), transistors (122) and (123), a driver circuit (120), and a bias generation circuit (125). The driver circuit (120) includes: a first inverter having an output; a second inverter having an input, an output, and a first power supply input and a second power supply input; and a transfer gate having an input, an output, and an enable input. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transfer gate is coupled to an output of a driver circuit (120), the first supply input of the second inverter is coupled to the output of the transfer gate, and the second supply input of the second inverter is coupled to the output of the driver circuit (120). And the second supply input of the second inverter is coupled to a reference terminal (117).

A first circuit has a predetermined function with an output that has a small dependence on a certain operation condition. A second circuit has the same function as that of the first circuit with an output that has a large dependence on the certain operation condition. When the first circuit is operating normally, the main circuit operates according to the output of the first circuit. The main circuit is capable of generating a detection signal that indicates the certain operation condition based on a relative relation between the output of the first circuit and the output of the second circuit.

To provide a device for and a method of separating a plurality of tenants in an integrated circuit including a programmable logic circuit, a processor system, and a network-on-chip.SOLUTION: The present invention is directed to a system-on-chip (SoC) 100 having a programmable logic (PL) circuit 104 arranged to operate with a plurality of tenants, a processor system (PS) 106 coupled with the PL circuit 104, and a network-on-chip (NoC) 108 coupled with the PL circuit 104 and the processor system. The PL circuit 104 is equipped with one or more hardware acceleration functions for the plurality of tenants and routes data between a first interface communicating with a host data processing system so as to separate the plurality of tenants and a second interface operating with the plurality of tenants.SELECTED DRAWING: Figure 1

Embodiments of the present application provide a method and system for controlling stable operation of an isolation device, comprising: obtaining a sampling value of a sampling port; adjusting a duty cycle of a pulse width signal output by a control port according to the sampling value to obtain a target pulse width signal; and controlling stable operation of the isolation device by the target pulse width signal. By the present application, the problem of power waste caused by the need for continuous high level of weak point equipment in related art is solved.

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

The invention discloses a receiver, a digital isolator and a disconnection protection method thereof. The digital isolator includes a transmitter and a receiver connected via a differential line. The receiver comprises an amplifier, an envelope detector and a driver which are connected in sequence, and the envelope detector is configured to perform envelope detection on a differential input signal received by the receiver so as to generate a corresponding envelope signal; the switch module is configured to control the on-off state of an input signal path of the envelope detector; and the broken line protection module is used for detecting the line fault of the differential line according to the signal change of the envelope signal in different on-off states during the power-on reset period, and stopping providing the output signal when the line fault exists in the differential line.

The invention relates to the technical field of integrated circuit design, and discloses a high-reliability low-overhead dual-node flipping resistant latch and a D flip-flop. The latch adopts a composite redundant architecture and comprises a first two-input Mueller C unit, a second two-input Mueller C unit, a three-input Mueller C unit, a plurality of transmission gates and phase inverters, and three parallel storage paths are constructed. And when the Mueller C unit inputs are inconsistent, a high-resistance-state error interception mechanism is output to isolate errors so as to realize complete tolerance of single-node upset (SNU) and various double-node upset (DNU). The working state of the latch is controlled by a clock signal, transmission delay is reduced through a high-speed straight-through path in a transparent mode, and data are latched through a cross coupling feedback loop in a holding mode. The structure is compact, the area is effectively reduced, the power consumption overhead is effectively reduced, and the power consumption-delay-area product (PDAP) competitiveness is outstanding. In addition, an edge-triggered D flip-flop can be formed based on the latch.

In described examples of an input / output (10) circuit (700) powered by an input / output (10) supply voltage (VDDS), a supply detector cell detects a core supply voltage (VDD) and generates a supply detect signal. A driver circuit (705) is connected to a PAD (722) and receives the supply detect signal. A failsafe circuit (725) receives a PAD (722) voltage. The failsafe circuit (725) and the supply detector cell control a leakage current from the PAD (722) based on the IO supply voltage (VDDS) and the PAD (722) voltage.

A signal transmission device that transmits a driving signal for a power transistor from a primary circuit system to a secondary circuit system while isolating between the primary and secondary circuit systems includes: a first fault detection circuit configured to detect a fault in the primary circuit system; a second fault detection circuit configured to detect a fault in the secondary circuit system; a first signal transmission path configured to transmit the result of detection by the second fault detection circuit from the secondary circuit system to the primary circuit system while isolating between the primary and secondary circuit systems; and a self-test circuit configured to perform a self-test on each of the first fault detection circuit, the second fault detection circuit, and the first signal transmission path.

A microelectronic circuit includes a plurality of logic cells and register circuits arranged in a plurality of processing paths, and a plurality of monitoring cells associated with individual ones of the processing paths. Each monitoring cell is configured to generate an observation signal in response to abnormal operation of the individual processing path. Each of the plurality of logic cells belongs to one of a plurality of delay levels, depending on the amount of delay that may be generated. The delay levels include first, second, and third levels, wherein the first level covers logic cells that may generate the longest delay, the second level covers logic cells that may generate shorter delays than the first level, and the third level covers logic cells that may generate shorter delays than the second level. At least some of the plurality of processing paths include logic cells that belong to the second level but do not have monitoring cells. At least some of the plurality of processing paths include logic cells that belong to the third level but have monitoring cells associated with them.

A circuit for mitigating single-event transients (SETs) comprising: a first sub-circuit comprising a first p-type transistor arrangement configured to produce a first output and a first n-type transistor arrangement configured to produce a second output; and a second sub-circuit comprising a connected p-type transistor arrangement and a connected n-type transistor arrangement connected in series, wherein the first output and the second output are electrically coupled to each other by the second sub-circuit.

The activation of processing paths in a microelectronic circuit is achieved by providing one or more input messages (101, 102, 103) to decision software (104) and executing the decision software (104) to determine whether one or more of the processing paths of the microelectronic circuit will be activated with a test signal (112). The decision to activate the processing path with the test signal results in continued activation of one or more of the processing paths with the test signal, and the monitoring of whether a timing event occurs on the one or more activated processing paths. A timing event is a change in the digital value at the input of the corresponding register circuit on the activated processing path, occurring after an allowable time limit defined by the trigger signal of the corresponding register circuit.

An electronic device includes at least two electronic components. A reset circuit includes: a parity control circuit; at least two first flip-flops, wherein each first flip-flop has an output coupled to at least one of the at least two electronic components; and at least two second flip-flops, wherein each second flip-flop has at least one output coupled to an input of the parity control circuit.

Disclosed herein are independent safety isolation regions with integrated protection for power and signal lines. A single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety region that is used to verify proper operation of the main logic. The safety region is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while preventing shorting of external lines that carry the external voltage. The safety region includes protection circuitry that moves voltage levels of external analog signals down for monitoring within the safety region, the protection circuitry used to prevent shorting of external lines that carry the external analog signals.

A circuit includes an input-output, a supply terminal, a reference terminal, a high-side transistor, a low-side transistor, a driver, and a bias generation circuit. The driver circuit includes a first inverter having an output, a second inverter having an input, an output, and first and second supply inputs, and a transmission gate having an input, an output, and first and second enable inputs. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transmission gate is coupled to the output of the driver, the first supply input of the second inverter is coupled to the output of the transmission gate, and the second supply input of the second inverter is coupled to a reference terminal.

The invention provides a data transmission circuit and a communication module. The data transmission circuit comprises a current mode driving circuit and a voltage mode driving circuit, the current mode driving circuit is configured to be switched on when receiving a first mode selection signal; the voltage mode driving circuit is configured to be switched on when receiving a second mode selection signal; the current mode driving circuit comprises two groups of current mode semiconductor switch elements, and can control the first group of current mode semiconductor switch elements or the second group of current mode semiconductor switch elements to be turned on according to different driving signals; the voltage-mode driving circuit comprises two voltage-mode semiconductor switch elements, and can control the first voltage-mode semiconductor switch element or the second voltage-mode semiconductor switch element to be turned on according to different driving signals. According to the scheme, a single-chip integrated voltage type TX driving mode and a current type TX driving mode can be realized, so that a user can perform flexible switching according to requirements.

This application relates to the field of power electronics technology and discloses a drive holding circuit, electronic device, and vehicle. The drive holding circuit includes a first circuit and a second circuit. The first circuit is adapted to receive a power supply signal and a control signal, and to conduct when the control signal switches from invalid to valid, thereby generating a drive signal based on the power supply signal and latching the drive signal to keep it valid. The second circuit is adapted to receive the drive signal and a safety logic signal, and to release the latch of the drive signal when the control signal and the safety logic signal meet preset conditions, causing the drive signal to fail. This application can maintain a valid drive state even when a drive signal source failure occurs, thereby effectively avoiding the impact of a single fault on the function of the electronic device and significantly improving system reliability.

The embodiments of the present disclosure provide a semiconductor device, belonging to the field of semiconductor technology. The semiconductor device includes: a plurality of main interconnection elements configured to provide a plurality of signal transmission channels; a redundant interconnection element; and a logic control circuit configured to provide a signal transmission channel through the redundant interconnection element to replace the two or more signal transmission channels provided by the failed main interconnection element if any two or more of the main interconnection elements fail.

An application specific integrated circuit (ASIC) package for use in an electrical or electronic device is disclosed, the ASIC package comprising a plurality of functional units and a plurality of terminals. Each functional unit is configured with control logic operable to provide a discrete monitoring and / or control function associated with an aspect of operation of the electrical or electronic device. Each terminal comprises a plurality of input and / or output terminals, each input and / or output terminal being connected to at least one of the functional units. An operating status of each of the functional units is independently configurable into one of an enabled and non-enabled operational state, and the ASIC package is configured to be set into a target functional configuration selected from a plurality of different functional configurations. Each of the plurality of functional configurations comprises a different combination of operating states associated with respective ones of the plurality of functional units. In this way, the ASIC package provides a degree of customisability of supported functions, enabling the same 'master' ASIC package (e.g. the as-fabricated ASIC package) to be modified after manufacture to tailor the supported function set to a specific one of a plurality of devices.

The present disclosure describes an electronic circuit for performing a self-test, including a first circuit and a second circuit. During a reference defined mode of the electronic circuit: a first signal generator provides an inspection signal to a first event processor, the first event processor generates an output signal based on the inspection signal and a function, and a first signature generator generates a reference signature based on this output signal. During a self-test mode of the electronic circuit: a second signal generator provides an inspection signal to a second event processor, the second event processor generates an output signal based on the inspection signal and the function, and a second signature generator generates a test signature based on this output signal. The comparison block compares the test signature with a reference signature to provide a test result signal.

The application provides a data transmission circuit and a communication module, comprising: a current mode driving circuit and a voltage mode driving circuit; the current mode driving circuit is configured to be turned on when a first mode selection signal is received; the voltage mode driving circuit is configured to be turned off when a second mode selection signal is received; the current mode driving circuit comprises two groups of current mode semiconductor switching elements, and can control the first group of current mode semiconductor switching elements or the second group of current mode semiconductor switching elements to be opened according to different driving signals; the voltage mode driving circuit comprises two voltage mode semiconductor switching elements, and can control the first voltage mode semiconductor switching element or the second voltage mode semiconductor switching element to be opened according to different driving signals. The scheme can realize single-chip integrated voltage type TX and current type TX two driving modes, so that users can flexibly switch according to requirements.

This disclosure relates to a voltage tracking circuit. Various embodiments described herein relate to a device having an output pad configured to provide an output pad voltage. The device may include a tracking circuit configured to receive a first voltage, receive a second voltage different from the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage, and the feedback voltage. The device may include an output circuit configured to receive the first tracking voltage and the second tracking voltage from the tracking circuit, and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.