6results about "Fail-safe circuits" patented technology

The utility model relates to interface circuit technical field, concretely relates to an interface circuit with protection function, including connector J1, connector J2, thyristor Q2, resistance R2, resistance R4 and stabilivolt diode VT2, the anode of thyristor Q2 is connected with connector J1 and connector J2 respectively, the cathode of thyristor Q2 is grounded, the grid of thyristor Q2 is connected with one end of resistance R2, the other end of resistance R2 is grounded through resistance R4, the other end of resistance R2 is connected with the anode of stabilivolt diode VT2, the cathode of stabilivolt diode VT2 is connected with the anode of thyristor Q2, the utility model discloses that the overvoltage trigger loop that stabilivolt diode VT2 and thyristor Q2 constitute, realize overvoltage threshold accurate control, when overvoltage, thyristor Q2 fast conduction, bypass and form big current loop to load, instantaneous fuse F1, cut off power supply thoroughly, avoid continuous overvoltage damage load.

A first circuit has a predetermined function with an output that has a small dependence on a certain operation condition. A second circuit has the same function as that of the first circuit with an output that has a large dependence on the certain operation condition. When the first circuit is operating normally, the main circuit operates according to the output of the first circuit. The main circuit is capable of generating a detection signal that indicates the certain operation condition based on a relative relation between the output of the first circuit and the output of the second circuit.

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

A circuit includes an input-output, a supply terminal, a reference terminal, a high-side transistor, a low-side transistor, a driver, and a bias generation circuit. The driver circuit includes a first inverter having an output, a second inverter having an input, an output, and first and second supply inputs, and a transmission gate having an input, an output, and first and second enable inputs. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transmission gate is coupled to the output of the driver, the first supply input of the second inverter is coupled to the output of the transmission gate, and the second supply input of the second inverter is coupled to a reference terminal.

This application relates to the field of power electronics technology and discloses a drive holding circuit, electronic device, and vehicle. The drive holding circuit includes a first circuit and a second circuit. The first circuit is adapted to receive a power supply signal and a control signal, and to conduct when the control signal switches from invalid to valid, thereby generating a drive signal based on the power supply signal and latching the drive signal to keep it valid. The second circuit is adapted to receive the drive signal and a safety logic signal, and to release the latch of the drive signal when the control signal and the safety logic signal meet preset conditions, causing the drive signal to fail. This application can maintain a valid drive state even when a drive signal source failure occurs, thereby effectively avoiding the impact of a single fault on the function of the electronic device and significantly improving system reliability.

Perform a proper diagnosis of the signal transmission device. [Solution] The signal transmission device transmits a drive signal for a power transistor from the primary circuit system to the secondary circuit system while insulating the primary circuit system from the secondary circuit system, and includes a first abnormality detection circuit configured to detect an abnormality in the primary circuit system, a second abnormality detection circuit configured to detect an abnormality in the secondary circuit system, a first signal transmission path configured to transmit the detection result of the second abnormality detection circuit from the secondary circuit system to the primary circuit system while insulating the primary circuit system from the secondary circuit system, and a diagnostic circuit configured to diagnose the first abnormality detection circuit, the second abnormality detection circuit, and the first signal transmission path, respectively.