104results about "Voltage/temperature variation compensation" patented technology

The present application discloses a high-speed transmitter and a serial data transmitter circuit, which relates to the technical field of signal transmission circuit design, wherein the high-speed transmitter includes a signal transmission unit, and the signal transmission unit includes: a signal transceiver module, which is used to transmit an input target signal; a first power tube, whose input end is used to receive an input target voltage, and whose output end is connected to the power supply end of the signal transceiver module. The technical solution of the present application is to set a first power tube in the signal transmission unit, and control the first power tube to power the signal transceiver module according to the target voltage input at the input end of the first power tube, and at the same time, combined with the characteristic of the power tube having a lower on-resistance, so that the setting of the first power tube can reduce the voltage drop at the power supply end of the signal transceiver module, thereby being able to meet the normal supply voltage requirements during high-speed serial link transmission.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

The invention provides a control method and device of a radio frequency power supply, the radio frequency power supply and semiconductor process equipment, and is applied to the technical field of semiconductor process equipment, the method is applied to the radio frequency power supply which provides at least one pulse signal in each work period, and in the at least one pulse signal in each work period of the radio frequency power supply, the pulse signal is transmitted to the radio frequency power supply. Wherein one pulse signal is controlled according to a first control mode, and the first control mode is as follows: according to a forward power feedback value, a reflection power feedback value, a dissipation power feedback value and a bus voltage threshold value of a current radio frequency power supply, a bus voltage output to the radio frequency power supply is adjusted, and a bias voltage output to the radio frequency power supply is kept unchanged; compared with a protection circuit built according to electronic components in the prior art, the invention provides a software protection mechanism, the execution process is not easily influenced by factors such as environment temperature and electromagnetic interference, the protection mechanism is more reliable, and the safety of the radio frequency power supply in the operation process can be ensured.

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. The bitstream is filtered and decimated to produce an output code representative of the temperature of the chip.

The invention discloses an AFE analog front-end circuit applied to a multi-channel high-speed optical receiver. The circuit comprises an SF-TIA, a single-ended to differential circuit and a CLTE. The SF-TIA, the single-ended to differential circuit and the CLTE are connected in sequence; the SF-TIA is used for converting an input current signal into a voltage signal and transmitting the voltage signal to the single-ended to differential circuit; wherein the current signal is obtained by converting an input optical signal; the single-ended to differential circuit is used for converting the voltage signal into a differential voltage signal and transmitting the differential voltage signal to the CLTE; and the CLTE is used for compensating the high-frequency gain of the differential voltage signal to obtain a compensated voltage signal and outputting the compensated voltage signal. The amplifier has the advantages of being high in gain, low in power consumption, low in input impedance, low in noise, low in requirement for power supply voltage and simple in structure.

A display panel driving device includes a control IC, a power management integrated circuit (PMIC), and a digital circuit unit configured to drive a display panel. The digital circuit unit is supplied with an adjusted external power supply voltage according to a load mode of the digital circuit unit to control driving of the display panel, and the control IC is configured to control the PMIC according to the load mode and enable the external power supply voltage to be variably supplied to the digital circuit unit according to the control operation of the control IC.

The invention relates to a signal transmission circuit (1) for analog current signals in an explosion-proof region, comprising: a transformer (2) having one or more primary coils (4, 4a, 4b) and one or more secondary coils (6, 6a, 6b) coupled in a common magnetic circuit via a transformer yoke (J); a control circuit (10) configured to control a voltage across the one or more secondary coils (6, 6a, 6b) to zero by providing a compensation current for flux compensation, where the control variable corresponds to a measurement voltage that is one of: obtained from a voltage across a measurement coil (8) arranged in the magnetic circuit; the analog current signal to be transmitted corresponds to or depends on the compensation current, and is obtained as a function of the voltage across one of the plurality of secondary coils (6a, 6b) in the magnetic circuit when it is powered off.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

The invention relates to the technical field of transistor driving, in particular to an adaptive variable resistance transistor driving system, which comprises a data acquisition module; the driving analysis module is used for determining whether grid resistance driving needs to be carried out on the current opening process according to the abnormal reference value, and carrying out staged driving or overall driving on the grid resistance according to the Miller plateau time and the change rate fluctuation value when the grid resistance driving is carried out on the current opening process; the stage division module is used for determining whether to perform secondary division on each stage according to the stage comparison value corresponding to each stage; the stage driving module is used for determining grid resistance adjustment aiming at the characteristic pre-adjustment sections or all the pre-adjustment sections according to the number of the pre-adjustment sections and adjusting the grid resistance according to the abnormal degree of section change; and the integral driving module is used for adjusting the grid resistance according to the turn-on stage characterization value. According to the invention, the conduction loss of the transistor can be reduced.

The invention discloses a capacitor isolation load control circuit and method, and the method comprises the steps: controlling two output ends of a signal transmitting module U1 to output voltage signals with opposite levels respectively, and inputting the voltage signals to one end of a first isolation capacitor C1 and one end of a second isolation capacitor C2 respectively; the other ends of the first isolation capacitor C1 and the second isolation capacitor C2 are respectively connected with the first input end and the second input end of the signal conversion circuit; the signal conversion circuit rectifies and multiplies the voltage between the two input ends, and inputs the rectified and multiplied voltage into the load driving circuit; the load driving circuit comprises a first field effect transistor Q1 and a second field effect transistor Q2, the two field effect transistors are connected in a back-to-back mode, the two back-to-back field effect transistors are controlled to be switched on or switched off through the voltage after voltage doubling, and the output ends of the two back-to-back field effect transistors are connected to the two ends of a load M1 respectively. According to the invention, the back-to-back field effect transistors are adopted to control the load, the two back-to-back field effect transistors are ensured to only work in a cut-off or saturation conduction stage, and the method is suitable for controlling the large-current load.

The present disclosure relates to compensating for temperature variation of a mixer. Embodiments herein may include the mixer, a calibration circuit coupled to the mixer, a replica mixer circuit coupled to the calibration circuit, and a temperature compensation circuit coupled to the calibration circuit. The replica mixer circuit may generate or be used to generate a reference voltage that varies with a common mode voltage and / or a threshold voltage of a replica mixer. The reference voltage may be applied to a resistor ladder of the calibration circuit to adjust a bias voltage and compensate for temperature variations. Further, the temperature compensation circuit may generate a temperature coefficient that may be applied to a current going through the calibration circuit to facilitate compensating for temperature variation.

The application discloses a kind of sensing transducer and its voltage signal processing circuit, belong to the field of transducer, for using analog circuit to realize for sensor voltage signal segmented calibration, solved the problem that voltage signal is difficult to maintain higher signal accuracy under strong interference environment.Considering that the way of segmented calibration can improve the accuracy of sensor output voltage signal, and analog circuit has strong anti-interference ability, the segmented identification circuit of the application can deliver voltage signal to the segmented calibration circuit corresponding to the voltage value interval to which the voltage signal belongs, so that the segmented calibration circuit can multiply the received voltage signal by a predetermined slope and add a predetermined intercept, and output after signal conditioning circuit, so as to realize the segmented calibration of voltage signal, and each part of circuit is analog circuit, has strong anti-interference ability, so that voltage signal can maintain higher signal accuracy under strong interference environment, widen the application scenario of sensing transducer.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The present disclosure relates to a method for implementing a VPTAT multiplier in a high-precision thermal sensor. A temperature sensing circuit and a switched capacitor circuit selectively sample ΔVbe and Vbe voltages and provide the sampled voltages to the input of an integrator. A quantization circuit quantizes the output of the integrator to generate a bit stream. When the latest bit of the bit stream is a logic zero, the operation includes sampling and integrating ΔVbe a first given number of times to generate a voltage proportional to the absolute temperature. When the latest bit of the bit stream is a logic one, the operation includes sampling and integrating Vbe a second given number of times to generate a voltage complementary to the absolute temperature. A low-pass filter and a decimator filter and decimate the bit stream generated by the quantization circuit to generate a signal indicating the temperature of a chip in which the temperature sensing circuit is integrated.

The invention relates to the field of control circuits, and discloses a universal output interface circuit, a circuit board and electronic equipment, the universal output interface circuit comprises a first-stage switch tube and a second-stage switch tube, the first-stage switch tube is electrically connected with the second-stage switch tube; wherein the first-stage switching tube is used for receiving a control signal of a controller, and the second-stage switching tube is used for outputting a level state of the universal output interface circuit; and the first-stage switching tube controls the on or off of the second-stage switching tube according to a control signal of a controller, so that the second-stage switching tube outputs the level state of the universal output interface circuit. Therefore, the general output interface circuit is simple in structure and can have relatively high power output while outputting a level signal, and the driving capability of the general output interface circuit is improved; moreover, the output state of the interface is stable, the interface is not in an uncertain level state, the misoperation of the load is prevented, and the reliability of the universal output interface circuit is improved.

The present disclosure provides a device, a method and a semiconductor device for reducing current change rate, relates to the technical field of semiconductors, and particularly relates to the fields of semiconductor chips, artificial intelligence chips, power control and the like. The implementation scheme is: a virtual data generator configured to generate virtual data that changes with clock cycles; a signal injection controller configured to activate a power maintenance flag signal for providing to a dynamic power logic circuit in a first period and a second period, and control the virtual data to be provided to the dynamic power logic circuit, deactivate the power maintenance flag signal in a third period, and control the data load to be provided to the dynamic power logic circuit; and a multiplexer configured to provide the virtual data to the dynamic power logic circuit in the first period and the second period based on the control of the signal injection controller, and provide the data load to the dynamic power logic circuit in the third period.

An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit. The compensation control mechanism operation logic includes a subset handle interface which generates a subset read control signal and transmits the subset read control signal to a corresponding storage circuit.

According to the sampling circuit and method for the IGBT temperature maximum value, two identical temperature sampling sub-circuits are integrated, signal collection can be conducted on two independent temperature sampling resistors, on the basis that only one sampling circuit PCB area is occupied, only one MCU data processing port is needed, and the sampling circuit is simple in structure, convenient to use and high in sampling efficiency. Therefore, acquisition, analysis and signal output of two paths or even multiple paths of temperature signals can be realized, errors caused by interference caused by overlong-path transmission can be avoided by the simplified sampling circuit, and the acquisition precision of the maximum temperature signal is improved. Specifically, target parameter processing functions such as operational amplification, voltage comparison and minimum voltage output are integrated in each temperature sampling sub-circuit, so that a relatively small voltage signal (corresponding to a relatively high temperature) in the two temperature sampling sub-circuits can be screened out and output, and it is ensured that even under complex and changeable working conditions, the temperature of the temperature sampling sub-circuits can be accurately detected. And the highest temperature of the IGBT can be accurately captured, so that the use safety and reliability of the sampling circuit are improved.

An apparatus is provided which comprises: a data sampler coupled to an output of a driver, wherein the data sampler is to sample data and to compare it with a first threshold voltage and a second threshold voltage, and wherein the data sampler is to generate an up or down indicator according to comparing the data with the first and second threshold voltages; and logic coupled to the data sampler, wherein the logic is to receive the up or down indicator and to increment or decrement a number of already DC compensated impedance legs of the driver according to the up or down indicator.

Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

A circuit (55) comprising: a semiconductor switch (34) having a gate terminal (G); first, second, third and fourth gate resistors (40), each having an upstream end (41) and a downstream end (42), the downstream end (42) of each gate resistor (40) being electrically connected to the gate terminal (G) of the semiconductor switch (34); first, second, third and fourth buffer switches (32), each having a gate terminal (G) and a source terminal (S), wherein the source terminal (S) of the first, second, third and fourth buffer switches (32) are each connected to the upstream end (41) of the first, second, third and fourth gate resistors (40); a plurality of sensors (21); a microcontroller (50) in conjunction with a gate driver IC (30) and arranged, to receive a set of circuit measurements from the plurality of sensors (21), and in response thereto, to: Determining, based on the set of circuit measurements, switching control values ​​and gate resistance identities; and Transmitting on / off control signals and a gate resistance selection signal (13) to the gate driver IC (30) to thereby select a respective on / off state of the individual buffer switches (32), the on / off control signals and the gate resistance selection signal (13) according to the switching control values ​​and gate resistance identities; wherein the gate driver IC (30) is connected to the gate terminals of each of the buffer switches (32); and a terminal circuit (45, 46) electrically connected to the semiconductor switch (34) and which is arranged to increase a gate voltage to the semiconductor switch (34) in response to a threshold voltage across the semiconductor switch (34), wherein the threshold voltage transmitted to the gate terminal (G) causes the semiconductor switch (34) to enter a conducting state.

The invention discloses a feedback expansion conversion device and method for an encoder, the output end of the encoder is connected with the feedback expansion conversion device, the encoder outputs a differential signal, and the feedback expansion conversion device comprises a signal buffer circuit, a signal processing circuit and a feedback expansion conversion circuit, the input end of the driver is connected with the output end of the encoder so as to perform driving enhancement on the differential signal to generate an enhanced signal; and the interface expansion circuit comprises a plurality of groups of connectors, and the input ends of the connectors are respectively connected with the signal buffer circuit so as to realize expansion output of the enhanced signal. Through the design of signal buffering, multi-path expansion, impedance matching, overcurrent protection and electrical isolation, the transmission stability, the driving capability, the system expansibility and the anti-interference capability of feedback signals of the encoder are remarkably improved, multiple pain points in the prior art are solved, and the precision, the reliability and the maintenance convenience of the shaft control system are improved.

Embodiments of the present application provide a method and system for controlling stable operation of an isolation device, comprising: obtaining a sampling value of a sampling port; adjusting a duty cycle of a pulse width signal output by a control port according to the sampling value to obtain a target pulse width signal; and controlling stable operation of the isolation device by the target pulse width signal. By the present application, the problem of power waste caused by the need for continuous high level of weak point equipment in related art is solved.

The invention relates to a signal transmission circuit (1) for an analog current signal in an explosion-proof area, comprising: - a transformer (2) with one or more primary-side coils (4, 4a, 4b) and one or more secondary-side coils (6, 6a, 6b) which are coupled via a transformer yoke (J) in a common magnetic circuit; - a control circuit (10) which is designed to control the voltage across the one or more secondary-side coils (6, 6a, 6b) to zero by providing a compensation current for flux compensation, wherein the control variable corresponds to a measuring voltage which is one of: o obtained as a function of a voltage across a measuring coil (8) arranged in the magnetic circuit;and o is obtained as a function of a voltage across one of the plurality of secondary coils (6a, 6b) in the magnetic circuit when it is de-energized, wherein the analog current signal to be transmitted corresponds to or depends on the compensation current.;

The invention discloses a frequency-voltage conversion circuit, which realizes the function of generating a two-phase switch control signal with a phase difference by multiplexing a clock input signal representing frequency information in front of a frequency dividing circuit and performing simple combinational logic on the clock input signal and a frequency dividing signal. Therefore, the influence of process, voltage or temperature fluctuation on the stability of the circuit is avoided.

The present invention relates to the control of semiconductor devices, in particular MOS devices, in order to reduce RTS / flicker noise. A circuit (100) comprises a first MOS device (103, 104) and a bias controller (107). The circuit is capable of at least one first circuit state (P RO ) and the second circuit state (P RST ) operation, in the first circuit state, the first MOS device is active to contribute to a first signal (Sout), and in the second circuit state, the first MOS device does not contribute to the first signal. The bias controller is operable to control the voltage at one or more terminals of the first MOS device to apply a pre-bias voltage (Vout) during instances of the second circuit state. PB1 、V PB2 ). The pre-bias is applied to set an occupied state of charge carrier traps within the first MOS device to limit noise during subsequent operation in the first circuit state. In an embodiment, the bias controller is configured such that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

To suppress characteristic deterioration of a transistor in a driver circuit.SOLUTION: An embodiment includes: a first transistor; a second transistor to which a second signal is inputted to a gate and one of a source and a drain; a third transistor whose gate is electrically connected to the other of the source or the drain of the first transistor, for controlling whether or not to set a voltage state of an output signal by turning on or off; and a fourth transistor whose gate is electrically connected to the other of the source or the drain of the second transistor, for controlling whether or not to set a voltage state of the output signal by turning on or off.SELECTED DRAWING: Figure 6

The application discloses a kind of level shifter circuit, high-speed digital-to-analog converter and high-speed analog-to-digital converter, level shifter circuit includes MOS tube PM1b, MOS tube PM2b, MOS tube PM2a, MOS tube PM1a, current mode logic unit and clocked latch, the source of MOS tube PM1b, MOS tube PM2b, MOS tube PM2a and MOS tube PM1a is connected to voltage VDDA, the gate of MOS tube PM2b and the gate of MOS tube PM2a are interconnected, the drain of MOS tube PM1b and the drain of MOS tube PM2b are connected, the drain of MOS tube PM2a and the drain of MOS tube PM1a are connected.The current mode logic unit includes MOS tube NM2b, MOS tube NM2a, MOS tube NM1b, MOS tube NM1a, current source IB, resistance R1b, resistance R1a, MOS tube PM3b, MOS tube PM3a, MOS tube NM3b, MOS tube NM3a and first inverter.The high-voltage MOS tube NM3a or high-voltage MOS tube NM3b with gate bias at a suitable potential VBN isolates the upper and lower low-voltage devices, so that the low-voltage devices do not appear overvoltage process, solve the problem that existing level shifter uses low-voltage devices prone to overvoltage, reduce the production cost of level shifter.