47results about "Voltage/temperature variation compensation" patented technology

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

The invention discloses an AFE analog front-end circuit applied to a multi-channel high-speed optical receiver. The circuit comprises an SF-TIA, a single-ended to differential circuit and a CLTE. The SF-TIA, the single-ended to differential circuit and the CLTE are connected in sequence; the SF-TIA is used for converting an input current signal into a voltage signal and transmitting the voltage signal to the single-ended to differential circuit; wherein the current signal is obtained by converting an input optical signal; the single-ended to differential circuit is used for converting the voltage signal into a differential voltage signal and transmitting the differential voltage signal to the CLTE; and the CLTE is used for compensating the high-frequency gain of the differential voltage signal to obtain a compensated voltage signal and outputting the compensated voltage signal. The amplifier has the advantages of being high in gain, low in power consumption, low in input impedance, low in noise, low in requirement for power supply voltage and simple in structure.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

The invention relates to the technical field of transistor driving, in particular to an adaptive variable resistance transistor driving system, which comprises a data acquisition module; the driving analysis module is used for determining whether grid resistance driving needs to be carried out on the current opening process according to the abnormal reference value, and carrying out staged driving or overall driving on the grid resistance according to the Miller plateau time and the change rate fluctuation value when the grid resistance driving is carried out on the current opening process; the stage division module is used for determining whether to perform secondary division on each stage according to the stage comparison value corresponding to each stage; the stage driving module is used for determining grid resistance adjustment aiming at the characteristic pre-adjustment sections or all the pre-adjustment sections according to the number of the pre-adjustment sections and adjusting the grid resistance according to the abnormal degree of section change; and the integral driving module is used for adjusting the grid resistance according to the turn-on stage characterization value. According to the invention, the conduction loss of the transistor can be reduced.

The invention discloses a capacitor isolation load control circuit and method, and the method comprises the steps: controlling two output ends of a signal transmitting module U1 to output voltage signals with opposite levels respectively, and inputting the voltage signals to one end of a first isolation capacitor C1 and one end of a second isolation capacitor C2 respectively; the other ends of the first isolation capacitor C1 and the second isolation capacitor C2 are respectively connected with the first input end and the second input end of the signal conversion circuit; the signal conversion circuit rectifies and multiplies the voltage between the two input ends, and inputs the rectified and multiplied voltage into the load driving circuit; the load driving circuit comprises a first field effect transistor Q1 and a second field effect transistor Q2, the two field effect transistors are connected in a back-to-back mode, the two back-to-back field effect transistors are controlled to be switched on or switched off through the voltage after voltage doubling, and the output ends of the two back-to-back field effect transistors are connected to the two ends of a load M1 respectively. According to the invention, the back-to-back field effect transistors are adopted to control the load, the two back-to-back field effect transistors are ensured to only work in a cut-off or saturation conduction stage, and the method is suitable for controlling the large-current load.

The application discloses a kind of sensing transducer and its voltage signal processing circuit, belong to the field of transducer, for using analog circuit to realize for sensor voltage signal segmented calibration, solved the problem that voltage signal is difficult to maintain higher signal accuracy under strong interference environment.Considering that the way of segmented calibration can improve the accuracy of sensor output voltage signal, and analog circuit has strong anti-interference ability, the segmented identification circuit of the application can deliver voltage signal to the segmented calibration circuit corresponding to the voltage value interval to which the voltage signal belongs, so that the segmented calibration circuit can multiply the received voltage signal by a predetermined slope and add a predetermined intercept, and output after signal conditioning circuit, so as to realize the segmented calibration of voltage signal, and each part of circuit is analog circuit, has strong anti-interference ability, so that voltage signal can maintain higher signal accuracy under strong interference environment, widen the application scenario of sensing transducer.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The present disclosure relates to a method for implementing a VPTAT multiplier in a high-precision thermal sensor. A temperature sensing circuit and a switched capacitor circuit selectively sample ΔVbe and Vbe voltages and provide the sampled voltages to the input of an integrator. A quantization circuit quantizes the output of the integrator to generate a bit stream. When the latest bit of the bit stream is a logic zero, the operation includes sampling and integrating ΔVbe a first given number of times to generate a voltage proportional to the absolute temperature. When the latest bit of the bit stream is a logic one, the operation includes sampling and integrating Vbe a second given number of times to generate a voltage complementary to the absolute temperature. A low-pass filter and a decimator filter and decimate the bit stream generated by the quantization circuit to generate a signal indicating the temperature of a chip in which the temperature sensing circuit is integrated.

The present disclosure provides a device, a method and a semiconductor device for reducing current change rate, relates to the technical field of semiconductors, and particularly relates to the fields of semiconductor chips, artificial intelligence chips, power control and the like. The implementation scheme is: a virtual data generator configured to generate virtual data that changes with clock cycles; a signal injection controller configured to activate a power maintenance flag signal for providing to a dynamic power logic circuit in a first period and a second period, and control the virtual data to be provided to the dynamic power logic circuit, deactivate the power maintenance flag signal in a third period, and control the data load to be provided to the dynamic power logic circuit; and a multiplexer configured to provide the virtual data to the dynamic power logic circuit in the first period and the second period based on the control of the signal injection controller, and provide the data load to the dynamic power logic circuit in the third period.

A circuit (55) comprising: a semiconductor switch (34) having a gate terminal (G); first, second, third and fourth gate resistors (40), each having an upstream end (41) and a downstream end (42), the downstream end (42) of each gate resistor (40) being electrically connected to the gate terminal (G) of the semiconductor switch (34); first, second, third and fourth buffer switches (32), each having a gate terminal (G) and a source terminal (S), wherein the source terminal (S) of the first, second, third and fourth buffer switches (32) are each connected to the upstream end (41) of the first, second, third and fourth gate resistors (40); a plurality of sensors (21); a microcontroller (50) in conjunction with a gate driver IC (30) and arranged, to receive a set of circuit measurements from the plurality of sensors (21), and in response thereto, to: Determining, based on the set of circuit measurements, switching control values ​​and gate resistance identities; and Transmitting on / off control signals and a gate resistance selection signal (13) to the gate driver IC (30) to thereby select a respective on / off state of the individual buffer switches (32), the on / off control signals and the gate resistance selection signal (13) according to the switching control values ​​and gate resistance identities; wherein the gate driver IC (30) is connected to the gate terminals of each of the buffer switches (32); and a terminal circuit (45, 46) electrically connected to the semiconductor switch (34) and which is arranged to increase a gate voltage to the semiconductor switch (34) in response to a threshold voltage across the semiconductor switch (34), wherein the threshold voltage transmitted to the gate terminal (G) causes the semiconductor switch (34) to enter a conducting state.

The invention discloses a feedback expansion conversion device and method for an encoder, the output end of the encoder is connected with the feedback expansion conversion device, the encoder outputs a differential signal, and the feedback expansion conversion device comprises a signal buffer circuit, a signal processing circuit and a feedback expansion conversion circuit, the input end of the driver is connected with the output end of the encoder so as to perform driving enhancement on the differential signal to generate an enhanced signal; and the interface expansion circuit comprises a plurality of groups of connectors, and the input ends of the connectors are respectively connected with the signal buffer circuit so as to realize expansion output of the enhanced signal. Through the design of signal buffering, multi-path expansion, impedance matching, overcurrent protection and electrical isolation, the transmission stability, the driving capability, the system expansibility and the anti-interference capability of feedback signals of the encoder are remarkably improved, multiple pain points in the prior art are solved, and the precision, the reliability and the maintenance convenience of the shaft control system are improved.

Embodiments of the present application provide a method and system for controlling stable operation of an isolation device, comprising: obtaining a sampling value of a sampling port; adjusting a duty cycle of a pulse width signal output by a control port according to the sampling value to obtain a target pulse width signal; and controlling stable operation of the isolation device by the target pulse width signal. By the present application, the problem of power waste caused by the need for continuous high level of weak point equipment in related art is solved.

The invention discloses a frequency-voltage conversion circuit, which realizes the function of generating a two-phase switch control signal with a phase difference by multiplexing a clock input signal representing frequency information in front of a frequency dividing circuit and performing simple combinational logic on the clock input signal and a frequency dividing signal. Therefore, the influence of process, voltage or temperature fluctuation on the stability of the circuit is avoided.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

To suppress characteristic deterioration of a transistor in a driver circuit.SOLUTION: An embodiment includes: a first transistor; a second transistor to which a second signal is inputted to a gate and one of a source and a drain; a third transistor whose gate is electrically connected to the other of the source or the drain of the first transistor, for controlling whether or not to set a voltage state of an output signal by turning on or off; and a fourth transistor whose gate is electrically connected to the other of the source or the drain of the second transistor, for controlling whether or not to set a voltage state of the output signal by turning on or off.SELECTED DRAWING: Figure 6

The application discloses a kind of level shifter circuit, high-speed digital-to-analog converter and high-speed analog-to-digital converter, level shifter circuit includes MOS tube PM1b, MOS tube PM2b, MOS tube PM2a, MOS tube PM1a, current mode logic unit and clocked latch, the source of MOS tube PM1b, MOS tube PM2b, MOS tube PM2a and MOS tube PM1a is connected to voltage VDDA, the gate of MOS tube PM2b and the gate of MOS tube PM2a are interconnected, the drain of MOS tube PM1b and the drain of MOS tube PM2b are connected, the drain of MOS tube PM2a and the drain of MOS tube PM1a are connected.The current mode logic unit includes MOS tube NM2b, MOS tube NM2a, MOS tube NM1b, MOS tube NM1a, current source IB, resistance R1b, resistance R1a, MOS tube PM3b, MOS tube PM3a, MOS tube NM3b, MOS tube NM3a and first inverter.The high-voltage MOS tube NM3a or high-voltage MOS tube NM3b with gate bias at a suitable potential VBN isolates the upper and lower low-voltage devices, so that the low-voltage devices do not appear overvoltage process, solve the problem that existing level shifter uses low-voltage devices prone to overvoltage, reduce the production cost of level shifter.

The invention provides a temperature sampling isolation circuit, a sampling method and device, electronic equipment and a vehicle. The temperature sampling isolation circuit comprises a dual-channel digital isolator 101 and an RC filter circuit 102, a second input end of the dual-channel digital isolator 101 is an input end of a clock signal; a second output end of the dual-channel digital isolator 101 is an output end of a temperature detection signal; the first output end of the dual-channel digital isolator 101 is connected with the first end of the RC filter circuit 102; the second end of the RC filter circuit 102 is connected with the first input end of the dual-channel digital isolator 101; and the third end of the RC filter circuit 102 is grounded. According to the scheme, the two-channel digital isolator is connected with the RC oscillation circuit, temperature sampling of the thermistor can be achieved, the circuit connection mode is simple, the price of the two-channel digital isolator is low, and the cost of the temperature sampling isolation circuit can be effectively reduced while isolation sampling is achieved.

The invention relates to a method for implementing a VPTAT multiplier in a high-precision thermal sensor. The temperature sensing circuit and the switched capacitor circuit selectively sample delta Vbe and Vbe voltages and provide the sampled voltages to the input of the integrator. The quantization circuit quantizes an output of the integrator to generate a bitstream. When the most recent bit of the bitstream is a logic zero, the operation includes sampling and integrating [delta] Vbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, the operation includes sampling and integrating the Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and a decimator filter and decimate the bit stream generated by the quantization circuit to generate a signal indicative of the temperature of the chip integrated with the temperature sensing circuit.

To suppress characteristic deterioration of a transistor in a driver circuit.SOLUTION: An embodiment includes: a first transistor; a second transistor to which a second signal is inputted to a gate and one of a source and a drain; a third transistor whose gate is electrically connected to the other of the source or the drain of the first transistor, for controlling whether or not to set a voltage state of an output signal by turning on or off; and a fourth transistor whose gate is electrically connected to the other of the source or the drain of the second transistor, for controlling whether or not to set a voltage state of the output signal by turning on or off.SELECTED DRAWING: Figure 6

In described examples, an integrated circuit (IC) includes a differential to single ended (DSE) circuit, and first, second, third, and fourth transistors (406, 408, 436), and (442). A control terminal of the first transistor (406) is coupled to a first output of the DSE circuit. A control terminal of the second transistor (408) is coupled to a second output of the DSE circuit. A first terminal of the third transistor (436) is coupled to a first terminal of the first transistor (406) and a control terminal of the third transistor (436) is coupled to a first terminal of the second transistor (408). A first terminal of the fourth transistor (442) is coupled to the first terminal of the second transistor (408), and a control terminal of the fourth transistor (442) is coupled to the first terminal of the first transistor (406).

The application relates to the field of transistor driving technology, in particular to a transistor driving system with self-adaptive variable resistance, which comprises a data acquisition module, a driving analysis module used for determining whether gate resistance driving is needed for a current on process according to an abnormal reference value, and when the gate resistance driving is needed for the current on process, driving the gate resistance in stages or as a whole according to Miller platform time and a change rate fluctuation value, a stage division module used for determining whether each stage is divided twice according to corresponding stage comparison values of the stages, a stage driving module used for determining gate resistance adjustment for a characteristic pre-adjustment stage or all pre-adjustment stages according to a pre-adjustment stage number, and adjusting the gate resistance according to paragraph change abnormality, and a whole driving module used for adjusting the gate resistance according to on stage characteristic values. The application can reduce the on loss of the transistor.

The embodiment of the present application discloses a kind of anti-signal interference adapter, it includes: input interface;At least one EMI filter module, the EMI filter module is connected with the input interface, and is used to eliminate common-mode interference;At least one input-output module, the input-output module is connected with the EMI filter module, and is used to convert input interference signal into digital signal, while for stabilizing output signal;Voltage rise and fall module, the voltage rise and fall module is connected with the input interface, and is used to stabilize output power supply;At least one output interface, the output interface is connected with the input-output module.The present application not only can completely eliminate the problem of existing control signal interference, but also when a controller controls multiple lasers simultaneously, using the adapter provided by the present application, multiple devices can be synchronized to work, greatly improving the ability of coordinated action.

A leakage compensation circuit (1101), a crystal oscillator circuit, and a microprocessor chip (1100). The leakage compensation circuit (1101) comprises: an IO module (100); a leakage compensation module (200), which comprises a source follower transistor (210) and a leakage current mirror transistor (220), wherein the source follower transistor (210) is electrically connected to an output end of the IO module (100) and is used for receiving and outputting a leakage current of the IO module (100), and the leakage current mirror transistor (220) is electrically connected to an output end of the source follower transistor (210) and is used for outputting a leakage compensation current on the basis of the leakage current of the IO module (100); and a crystal oscillator driving module (300), which is electrically connected to the output end of the IO module (100) and an output end of the leakage compensation module (200), and is used for receiving the leakage current and the leakage compensation current, and outputting a leakage compensation result on the basis of the leakage current and the leakage compensation current. The leakage compensation circuit can perform leakage compensation on an IO circuit, thereby ensuring the normal operation of the IO circuit.

The present invention discloses an AND logic circuit based on sinusoidal frequency product and a control method thereof. The circuit includes a multiplier, a low-pass filter, a high-pass filter, and a logic judgment unit. The first input of the multiplier is used to input a first sinusoidal signal A, and the second input of the multiplier is used to input a second sinusoidal signal B. The first sinusoidal signal A and the second sinusoidal signal B are sinusoidal signals of different frequencies. The output of the multiplier is respectively connected to the input of the low-pass filter and the high-pass filter, and the output of the low-pass filter and the high-pass filter are respectively connected to the input of the logic judgment unit. The present invention introduces a sinusoidal frequency product detection mechanism. By measuring and analyzing the sum frequency and difference frequency between the two sinusoidal signals, the signal state is verified, significantly enhancing the anti-interference capability and safety during the logic operation process.

The invention discloses a digital input system with an adjustable voltage threshold, which is characterized in that the normal phase input end of a hysteresis comparator is connected with a first adjustable voltage source by connecting a first resistor in series, the inverted phase input end of the hysteresis comparator is connected with a connector, and the output end of the hysteresis comparator is connected with the normal phase input end of the hysteresis comparator by connecting a second resistor in series; the processor is used for controlling the output voltage of the first adjustable voltage source; and the buffer is connected between the output end of the hysteresis comparator and the processor and is used for transmitting the level signal of the output end of the hysteresis comparator to the processor. The method has the advantages that the upper threshold value and the lower threshold value can be adjusted according to actual conditions by arranging the adjustable voltage source so as to adapt to different level standards, compatibility and stability are achieved, and cost is reduced.

The application provides a control circuit, which comprises a first resistor, a first end of the first resistor being connected with a VCC power supply, and a second end of the first resistor being connected with a first end of a switch module; a second resistor, a first end of the second resistor being connected with a second end of the switch module, and a second end of the second resistor being grounded; a third resistor, a first end of the third resistor being connected with the first end of the switch module, and a second end of the third resistor being connected with the second end of the switch module; and the switch module, a third end of the switch module being connected with a first bus, and a fourth end of the switch module being connected with a second bus, the switch module being used for switching on the connection between the second end of the first resistor and the first bus and the connection between the first end of the second resistor and the second bus. Thus, the control circuit can reduce signal distortion as much as possible, improve anti-interference performance, and enhance the reliability of the control circuit. Meanwhile, a small number of dial switches or relays and other components are used in the control circuit, so that low cost and easy maintenance can be achieved.

This invention discloses a high-voltage isolation circuit and its usage method, as well as an impedance correction method. Utilizing the characteristic of capacitors to pass high frequencies and block low frequencies, a capacitor Cs is connected in series in the isolation circuit. Cs suppresses high-frequency power voltage without affecting the test signals sent by the BIS equipment. This achieves the goal of isolating normal high-frequency power voltage and protecting the BIS test equipment while allowing the BIS equipment test signals to be injected and returned. When a fault arc occurs, the MCU controls the series inductor matrix to adjust the inductance value so that the isolation circuit generates series resonance at the frequency corresponding to the arc signal with the highest energy, thereby achieving high-energy arc signal isolation and protecting the BIS test equipment. During testing, since the BIS is frequency-adjustable, the test signal frequency band is set to exclude the frequency corresponding to the arc signal with the highest energy. This further enables the isolation of high-frequency, high-energy arc signals, protection of the BIS test equipment, and the simultaneous injection and return of the BIS equipment test signals.

An apparatus includes a network of switch-resistor pairs connected between a voltage level and an output pad or pin, and a control circuit to enable or disable respective switches of given switch-resistor pairs of the network. A given switch-resistor pair includes a switch and a resistor connected in parallel. Enablement of the switch is to cause current to flow through the switch and the resistor in parallel. Disablement of the switch of the given switch-resistor pair is to cause current to flow through the resistor and not the switch. A resistance of the resistor is less than half of an on-resistance of the switch.

The invention provides a level conversion circuit and a chip, and belongs to the technical field of circuits. The circuit comprises a dual-path output unit which is used for providing a first output end and a second output end respectively; the voltage limiting processing unit is used for determining the on-off state of the first output end and the grounding end based on the voltage value of the first output end so as to enable the voltage value of the first output end to change within a first threshold range, and determining the on-off state of the second output end and the grounding end based on the voltage value of the second output end so as to enable the voltage value of the second output end to change within a second threshold range; the voltage value of the second output end is enabled to change within a second threshold range; the first voltage conversion unit is used for performing voltage conversion on the first input voltage and outputting a first converted voltage to a first output end; and the second voltage conversion unit is used for performing voltage conversion on the second input voltage and outputting a second converted voltage to a second output end. The level conversion circuit is used for overcoming the defects that a traditional level conversion circuit can only adapt to a very limited voltage variation range and cannot be directly connected with a differential / common mode operational amplifier.

An embodiment provides a tunable drive circuit (180) that operates by: monitoring (160) the frequency of a ring oscillator (140) of an electrical integrated circuit (110) connected to an optical modulator (121) to determine an operating characteristic of the electrical integrated circuit (110); and setting drive voltages of a plurality of tunable inverters (FIG. 1: 182, FIG. 7: 730, 760) and a plurality of fixed gain inverters (FIG. 1: 182, FIG. 7: 740, 750) based on the operating characteristic. The tuning inverter and the plurality of fixed gain inverters control an optical modulator (121), wherein each of the plurality of tunable inverters (FIG. 7: 730, 760) is connected in parallel with a corresponding fixed gain inverter (FIG. 7: 740, 750) of the plurality of fixed gain inverters on a first arm (FIG. 7: 610A) and a second arm (FIG. 7: 610B) connected to the optical modulator (121); and the amplification strength of the plurality of tunable inverters is set based on operating characteristics.