20results about "Voltage/temperature variation compensation" patented technology

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

The application discloses a kind of sensing transducer and its voltage signal processing circuit, belong to the field of transducer, for using analog circuit to realize for sensor voltage signal segmented calibration, solved the problem that voltage signal is difficult to maintain higher signal accuracy under strong interference environment.Considering that the way of segmented calibration can improve the accuracy of sensor output voltage signal, and analog circuit has strong anti-interference ability, the segmented identification circuit of the application can deliver voltage signal to the segmented calibration circuit corresponding to the voltage value interval to which the voltage signal belongs, so that the segmented calibration circuit can multiply the received voltage signal by a predetermined slope and add a predetermined intercept, and output after signal conditioning circuit, so as to realize the segmented calibration of voltage signal, and each part of circuit is analog circuit, has strong anti-interference ability, so that voltage signal can maintain higher signal accuracy under strong interference environment, widen the application scenario of sensing transducer.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The invention discloses a feedback expansion conversion device and method for an encoder, the output end of the encoder is connected with the feedback expansion conversion device, the encoder outputs a differential signal, and the feedback expansion conversion device comprises a signal buffer circuit, a signal processing circuit and a feedback expansion conversion circuit, the input end of the driver is connected with the output end of the encoder so as to perform driving enhancement on the differential signal to generate an enhanced signal; and the interface expansion circuit comprises a plurality of groups of connectors, and the input ends of the connectors are respectively connected with the signal buffer circuit so as to realize expansion output of the enhanced signal. Through the design of signal buffering, multi-path expansion, impedance matching, overcurrent protection and electrical isolation, the transmission stability, the driving capability, the system expansibility and the anti-interference capability of feedback signals of the encoder are remarkably improved, multiple pain points in the prior art are solved, and the precision, the reliability and the maintenance convenience of the shaft control system are improved.

Embodiments of the present application provide a method and system for controlling stable operation of an isolation device, comprising: obtaining a sampling value of a sampling port; adjusting a duty cycle of a pulse width signal output by a control port according to the sampling value to obtain a target pulse width signal; and controlling stable operation of the isolation device by the target pulse width signal. By the present application, the problem of power waste caused by the need for continuous high level of weak point equipment in related art is solved.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

The application discloses a kind of level shifter circuit, high-speed digital-to-analog converter and high-speed analog-to-digital converter, level shifter circuit includes MOS tube PM1b, MOS tube PM2b, MOS tube PM2a, MOS tube PM1a, current mode logic unit and clocked latch, the source of MOS tube PM1b, MOS tube PM2b, MOS tube PM2a and MOS tube PM1a is connected to voltage VDDA, the gate of MOS tube PM2b and the gate of MOS tube PM2a are interconnected, the drain of MOS tube PM1b and the drain of MOS tube PM2b are connected, the drain of MOS tube PM2a and the drain of MOS tube PM1a are connected.The current mode logic unit includes MOS tube NM2b, MOS tube NM2a, MOS tube NM1b, MOS tube NM1a, current source IB, resistance R1b, resistance R1a, MOS tube PM3b, MOS tube PM3a, MOS tube NM3b, MOS tube NM3a and first inverter.The high-voltage MOS tube NM3a or high-voltage MOS tube NM3b with gate bias at a suitable potential VBN isolates the upper and lower low-voltage devices, so that the low-voltage devices do not appear overvoltage process, solve the problem that existing level shifter uses low-voltage devices prone to overvoltage, reduce the production cost of level shifter.

The invention provides a temperature sampling isolation circuit, a sampling method and device, electronic equipment and a vehicle. The temperature sampling isolation circuit comprises a dual-channel digital isolator 101 and an RC filter circuit 102, a second input end of the dual-channel digital isolator 101 is an input end of a clock signal; a second output end of the dual-channel digital isolator 101 is an output end of a temperature detection signal; the first output end of the dual-channel digital isolator 101 is connected with the first end of the RC filter circuit 102; the second end of the RC filter circuit 102 is connected with the first input end of the dual-channel digital isolator 101; and the third end of the RC filter circuit 102 is grounded. According to the scheme, the two-channel digital isolator is connected with the RC oscillation circuit, temperature sampling of the thermistor can be achieved, the circuit connection mode is simple, the price of the two-channel digital isolator is low, and the cost of the temperature sampling isolation circuit can be effectively reduced while isolation sampling is achieved.

In described examples, an integrated circuit (IC) includes a differential to single ended (DSE) circuit, and first, second, third, and fourth transistors (406, 408, 436), and (442). A control terminal of the first transistor (406) is coupled to a first output of the DSE circuit. A control terminal of the second transistor (408) is coupled to a second output of the DSE circuit. A first terminal of the third transistor (436) is coupled to a first terminal of the first transistor (406) and a control terminal of the third transistor (436) is coupled to a first terminal of the second transistor (408). A first terminal of the fourth transistor (442) is coupled to the first terminal of the second transistor (408), and a control terminal of the fourth transistor (442) is coupled to the first terminal of the first transistor (406).

A leakage compensation circuit (1101), a crystal oscillator circuit, and a microprocessor chip (1100). The leakage compensation circuit (1101) comprises: an IO module (100); a leakage compensation module (200), which comprises a source follower transistor (210) and a leakage current mirror transistor (220), wherein the source follower transistor (210) is electrically connected to an output end of the IO module (100) and is used for receiving and outputting a leakage current of the IO module (100), and the leakage current mirror transistor (220) is electrically connected to an output end of the source follower transistor (210) and is used for outputting a leakage compensation current on the basis of the leakage current of the IO module (100); and a crystal oscillator driving module (300), which is electrically connected to the output end of the IO module (100) and an output end of the leakage compensation module (200), and is used for receiving the leakage current and the leakage compensation current, and outputting a leakage compensation result on the basis of the leakage current and the leakage compensation current. The leakage compensation circuit can perform leakage compensation on an IO circuit, thereby ensuring the normal operation of the IO circuit.

This invention discloses a high-voltage isolation circuit and its usage method, as well as an impedance correction method. Utilizing the characteristic of capacitors to pass high frequencies and block low frequencies, a capacitor Cs is connected in series in the isolation circuit. Cs suppresses high-frequency power voltage without affecting the test signals sent by the BIS equipment. This achieves the goal of isolating normal high-frequency power voltage and protecting the BIS test equipment while allowing the BIS equipment test signals to be injected and returned. When a fault arc occurs, the MCU controls the series inductor matrix to adjust the inductance value so that the isolation circuit generates series resonance at the frequency corresponding to the arc signal with the highest energy, thereby achieving high-energy arc signal isolation and protecting the BIS test equipment. During testing, since the BIS is frequency-adjustable, the test signal frequency band is set to exclude the frequency corresponding to the arc signal with the highest energy. This further enables the isolation of high-frequency, high-energy arc signals, protection of the BIS test equipment, and the simultaneous injection and return of the BIS equipment test signals.

In a semiconductor integrated circuit, a first analog circuit block operates by a voltage applied between a first node and a third node. Each of a plurality of first current sources has a first end connected to the third node and a second end connected to the first analog circuit block. The plurality of first current sources function as current sourcing or current sinking for the first analog circuit block. A first switch group is provided between the plurality of first current sources and the first analog circuit block, and in a test mode, individually switches electrical connection of the second end of each of the plurality of first current sources from the first analog circuit block to a second node.

An element array circuit (1; 1B; 1C; 2; 3; 3A; 4) includes one or more first wiring lines (A (A1 to Am)), second wiring lines (B (B1 to Bn)), impedance elements (R (R(1, 1) to R(m, n)); SC (SC(1, 1) to SC(m, n))), one or more operational amplifiers (OP (OP1 to OPn)), one or more conversion elements (CP (CP1 to CPn); RE (RE1 to REn); D (D1 to Dn)), and one or more switchers (SW (SW1 to SWn)). The second wiring lines each extend in a direction different from a direction of extension of the first wiring lines. The impedance elements are each coupled to both one of the one or more first wiring lines and one of the second wiring lines. The operational amplifiers each include a positive input terminal (T1), a negative input terminal (T2) couplable to one of the second wiring lines, and an output terminal (T3). The conversion elements are each coupled to the negative input terminal and the output terminal, and each convert a current flowing through the second wiring line coupled to the negative input terminal into a voltage. The switchers are each coupled to one of the conversion elements and come into a conducting state or a nonconducting state.

Embodiments provide for a tunable driving circuit (180) by monitoring (160) a frequency of a ring oscillator (140) of an electrical integrated circuit (110) connected to an optical modulator (121) to determine operational characteristics of the electrical integrated circuit (110); setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters (fig. 1: 182, fig. 7: 730, 760) and a plurality of fixed gain inverters (fig. 1. 182, fig. 7: 740, 750) that control the optical modulator (121), wherein each tunable inverter of the plurality of tunable inverters (fig. 7: 730, 760) is connected in parallel with a corresponding fixed gain inverter (fig. 7: 740, 750) of the plurality of fixed gain inverters on one of a first arm (fig. 7: 610A) and a second arm (fig. 7: 610B) connected to the optical modulator (121); and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

The embodiment of the invention discloses a bus voltage slew rate control circuit, a bus voltage slew rate control method, electronic equipment and a storage medium, relates to the technical field of analog integrated circuits, and can prevent a relatively large instantaneous current from being generated on a power supply. The circuit comprises a signal preprocessing module which comprises a first node and an energy storage unit and is configured to perform pre-charging or discharging operation on the energy storage unit based on a level switching state of an input signal so as to adjust a voltage change rate of the first node; the comparator array is connected with the first node and is configured to acquire real-time voltage of the first node dynamically adjusted along with the voltage change rate, compare the real-time voltage of the first node with preset threshold voltage and output a multi-stage driving control signal with a time sequence difference; and according to the multi-stage driving control signal with the time sequence difference, controlling the multi-stage driving element to be switched on or switched off step by step according to a preset time sequence. The method and the device are suitable for an application scene of controlling the slew rate of the output signal under different IO protocols.

In described examples, an integrated circuit (IC) includes a differential to single ended (DSE) circuit, and first, second, third, and fourth transistors. A control terminal of the first transistor is coupled to a first output of the DSE circuit. A control terminal of the second transistor is coupled to a second output of the DSE circuit. A first terminal of the third transistor is coupled to a first terminal of the first transistor and a control terminal of the third transistor is coupled to a first terminal of the second transistor. A first terminal of the fourth transistor is coupled to the first terminal of the second transistor, and a control terminal of the fourth transistor is coupled to the first terminal of the first transistor.

A circuit includes one or more de-skew stages. Each of the one or more de-skew stages is configured to adjust a transition edge of a signal and includes a single inverter, a header configured to couple a first supply voltage to the single inverter, a footer configured to couple a second supply voltage to the single inverter, a capacitor coupled to an output of the single inverter, and a switch circuit coupled between the output of the single inverter and the capacitor.

Embodiments provide for a tunable driving circuit by monitoring a frequency of a ring oscillator of an electrical integrated circuit connected to an optical modulator to determine operational characteristics of the electrical integrated circuit; setting, based on the operational characteristics, a driving voltage for a plurality of tunable inverters and a plurality of fixed gain inverters that control the optical modulator, wherein each tunable inverter of the plurality of tunable inverters is connected in parallel with a corresponding fixed gain inverter of the plurality of fixed gain inverters on one of a first arm and a second arm connected to the optical modulator; and setting an amplification strength for the plurality of tunable inverters based on the operational characteristics.

A gate drive circuit includes a voltage summer, a driver, a power transistor and a resistor. The voltage summer includes a first input terminal for receiving a reference voltage, a second input terminal for receiving a common source voltage, and an output terminal for generating a summed voltage according to the common source voltage and the reference voltage. The driver includes a first input terminal coupled to the output terminal of the voltage summer, a second input terminal for receiving a pulse width modulation (PWM) signal, and an output terminal for generating a gate voltage according to the summed voltage and the pulse width modulation signal. The power transistor includes a first terminal, a second terminal, and a control terminal coupled to the output terminal of the driver. The resistor is coupled between the second terminal of the power transistor and a ground terminal.

In a first switch of a latch circuit, when the voltage between an emitter (input end) and a base (control end) has increased to a threshold voltage or more, the first switch is switched from off to on. The current that flows through a first resistor and a second resistor in that order is input to a collector (input end) of a second switch and a comparator switch. The second switch is switched on when the first switch is switched on. When the second switch or the comparator switch (third switch) is on, the voltage across the first resistor is the threshold voltage or more. A voltage is input to the emitter of the first switch from a microcomputer. A voltage is output from the collector of the second switch to a driving circuit.