9results about "Programmable logic circuit arrangements" patented technology

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

The main control device comprises a processing module with a switching pin and a plurality of signal pins, a first DIP switch, a second DIP switch, an inverting module, and a first switch and a second switch. The first DIP switch and second DIP switch are respectively connected to the signal pins through first and second signal switches. One end of the inverting module is connected to the processing module. The first switch connects to the first signal switches, the switching pin, the inverting module, and the operating voltage source. The second switch is connected to the second signal switches, the inverting module, and the operating voltage source.

An I2C interface circuit (10; 30; 40) is operatable at a low pull-up voltage and at a high pull-up voltage. A first pin (12a) receives a clock signal (I2Cclk) and a second pin (12b) receives a data signal (I2Cdata). A first comparator stage (24a) compares the received clock signal to a low threshold and a high threshold to produce an internal clock signal (clk_in). A second comparator stage (24b) compares the received data signal to the low threshold and the high threshold to produce an internal data signal (data_in). The first comparator stage and the second comparator stage are programmed by default to operate in a first operating mode, wherein the low threshold is set to a first fractional value of the high pull-up voltage and the high threshold is set to a second fractional value of the low pull-up voltage. The first comparator stage and the second comparator stage are switchable, upon reception via the I2C interface of a programming frame that conveys a current value of the pull-up voltage, to a second operating mode. In the second operating mode, the low threshold is set to the first fractional value of the current pull-up voltage and the high threshold is set to the second fractional value of the current pull-up voltage.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I / O ports coupling to the set of data buses and at least one first I / O-port selection pad configured to select a first port from the plurality of first I / O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

Disclosed herein are apparatus, system, method, and computer-readable medium aspects for interfacing a MIPI transmitter with a SERDES receiver. An example method aspect includes receiving first and second MIPI signals at respective inputs and level-shifting each signal using corresponding diodes. The level-shifted signals are applied to the base terminals of first and second transistors, whose emitters are coupled together. A control current is generated via a current mirror formed by a third and fourth transistor, with the current set by a control voltage. This control current is supplied to the coupled emitters, enabling the production of differential output signals at the collector terminals of the first and second transistors for input to a SERDES receiver.

A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

The present invention provides a main control device that can improve the amount of encoding setting signals received. [Solution] The main control unit includes a processing module, a first DIP switch, a second DIP switch, an inverting module, a first switch, and a second switch. The processing module has switching pins and a plurality of signal pins. The first DIP switch has a plurality of first signal switches connected to a plurality of signal pins. The second DIP switch has a plurality of second signal switches connected to a plurality of signal pins. One end of the inverting module is connected to the processing module. The first end of the first switch is connected to the plurality of first signal switches, the second end of the first switch is connected to one end of the inverting module and to the switching pins, and the third end of the first switch is connected to an operating voltage source. The first end of the second switch is connected to a plurality of second signal switches, the second end of the second switch is connected to the other end of the inverting module, and the third end of the second switch is connected to an operating voltage source.

An arrangement includes a matrix with a plurality of programmable logic units and a plurality of first one bit clocked storage elements, the programmable logic units and first one bit clocked storage elements being arranged in an array, the arrangement being adapted for sequential execution of at least two tasks, whereby for each of the first one bit clocked storage elements a data store and restore circuit is provided for local storing or restoring the respective values as computed during the tasks per task of the first one bit clocked storage elements;a data memory, external to the matrix, wherein the data store and restore circuit is provided for pre-loading values related to one task from the data memory into the data store and restore circuit and post-storing of values related to one task in the data store and restore circuit to the data memory, whereby the pre-loading and / or post-storing can be performed while another task is executed without disturbing the task execution; andan output circuit, required to ensure safe operation in case of task switching.

The present application provides an electrostatic discharge protection circuit, which includes an internal circuit, a Schottky diode and an electrostatic discharge release element. The Schottky diode is coupled between a specific node and the internal circuit. The electrostatic discharge release element is coupled between the specific node and a power supply terminal. When an electrostatic discharge event occurs at the specific node, the electrostatic discharge release element is turned on to release an electrostatic discharge current from the specific node to the power supply terminal. The present application can protect an integrated circuit.