20results about "Programmable logic circuit arrangements" patented technology

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

The main control device comprises a processing module with a switching pin and a plurality of signal pins, a first DIP switch, a second DIP switch, an inverting module, and a first switch and a second switch. The first DIP switch and second DIP switch are respectively connected to the signal pins through first and second signal switches. One end of the inverting module is connected to the processing module. The first switch connects to the first signal switches, the switching pin, the inverting module, and the operating voltage source. The second switch is connected to the second signal switches, the inverting module, and the operating voltage source.

The embodiments of the present invention provide a turnout position detection device and system, which relate to the railway field. The turnout position detection device includes a DC power supply group, a drive circuit connected to the DC power supply group, and a position detection circuit connected to the drive circuit. Therefore, compared with the prior art method of detecting turnout position using a polarity-biased relay that relies on an AC power supply, the technical solution provided by the embodiments of the present invention uses a DC power supply group to provide a more reliable signal and higher security. This can improve the problems of low safety factors and low reliability in the prior art, thereby improving reliability and safety. In addition, the turnout position detection device uses an electronic circuit to implement the functions performed by the polarity-biased relay in a switch machine, and has the following advantages: the electronic components take up less space; they can be plugged and unplugged under power, making replacement easy.

The present disclosure relates to a configurable interface circuit supporting a plurality of different selectable operational modes. In one example the interface circuit comprises a device terminal couplable to an external field device, a digital current path coupled to the device terminal, and having a first sense resistor, and an analog current path having a second sense resistor. When the configurable interface circuit is operating in the analog mode, an analog current can flow through the analog current path and an analog signal can be measured by measuring a voltage across the first sense resistor and second sense resistor, and when the configurable interface circuit is operating in the digital mode, a digital current is controlled to flow through the digital current path and a digital signal can be measured by measuring the voltage across the first sense resistor and second sense resistor.

One or more computing devices, systems, and / or methods are provided. In an example of the techniques presented herein, a system comprises a first input terminal and a first programmable analog block configured according to a first configuration. A controller is configured to reconfigure the first programmable analog block according to a second configuration different than the first configuration based on a first signal received at the first input terminal.

An integrated circuit (100) includes an Input / Output (I / O) interface (104), first-domain circuitry (108) and second-domain circuitry (110). The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

Disclosed herein are aspects for configuring a port in an integrated circuit using a configuration state machine. An example aspect begins by determining a current state of internal pull-up and pull-down resistors of the port. The aspect then modifies resistance characteristics of the resistors from the current state. These characteristics indicate a strap configuration of a circuitry connected to the port. The aspect determines a state result based on the strap configuration and the current state. The aspect transitions to a next state based on the state result. The aspect continues by modifying resistance characteristics of the resistors from the next state, indicating a second strap configuration. A second state result is then determined based on the second strap configuration and the next state. The aspect then transitions to a resultant terminal state based on the next state and configures the port to operate in accordance with a port configuration.

An I2C interface circuit (10; 30; 40) is operatable at a low pull-up voltage and at a high pull-up voltage. A first pin (12a) receives a clock signal (I2Cclk) and a second pin (12b) receives a data signal (I2Cdata). A first comparator stage (24a) compares the received clock signal to a low threshold and a high threshold to produce an internal clock signal (clk_in). A second comparator stage (24b) compares the received data signal to the low threshold and the high threshold to produce an internal data signal (data_in). The first comparator stage and the second comparator stage are programmed by default to operate in a first operating mode, wherein the low threshold is set to a first fractional value of the high pull-up voltage and the high threshold is set to a second fractional value of the low pull-up voltage. The first comparator stage and the second comparator stage are switchable, upon reception via the I2C interface of a programming frame that conveys a current value of the pull-up voltage, to a second operating mode. In the second operating mode, the low threshold is set to the first fractional value of the current pull-up voltage and the high threshold is set to the second fractional value of the current pull-up voltage.

Provided is a data transmission circuit that includes first and second drive circuits and an operation state control circuit. The first drive circuit drives first data that transitions or does not transition in synchronization with a clock signal. The second drive circuit drives second data that transitions at a timing when the first data does not transition in synchronization with the clock signal. The operation state control circuit individually controls operation states of the first and second drive circuits.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I / O ports coupling to the set of data buses and at least one first I / O-port selection pad configured to select a first port from the plurality of first I / O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

A main control device includes a processing module, a first dial, a second dial, a reverse module, a first switch, and a second switch. The processing module has a switching pin and a plurality of signal pins. The first dial has a plurality of first signal switches respectively connected to the plurality of signal pins. The second dial has a plurality of second signal switches respectively connected to the plurality of signal pins. One end of the reverse module is connected to the processing module. The first end of the first switch is connected to the plurality of first signal switches, the second end of the first switch is connected to one end of the reverse module and the switching pin, and the third end of the first switch is connected to an operating voltage source. The first end of the second switch is connected to the plurality of second signal switches, the second end of the second switch is connected to the other end of the reverse module, and the third end of the second switch is connected to the operating voltage source.

Disclosed herein are apparatus, system, method, and computer-readable medium aspects for interfacing a MIPI transmitter with a SERDES receiver. An example method aspect includes receiving first and second MIPI signals at respective inputs and level-shifting each signal using corresponding diodes. The level-shifted signals are applied to the base terminals of first and second transistors, whose emitters are coupled together. A control current is generated via a current mirror formed by a third and fourth transistor, with the current set by a control voltage. This control current is supplied to the coupled emitters, enabling the production of differential output signals at the collector terminals of the first and second transistors for input to a SERDES receiver.

A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

A multi-modality intraoperative neurophysiological monitoring (IONM) system includes at least one amplifier integrated with a programmable switch matrix module configured to have up to 32 patient connected electrode inputs that are multiplexed to up to 24 amplifier channels. In some scenarios, a capacitor is positioned in series with electrode inputs of the at least one amplifier, such that the capacitor eliminates DC offset voltages from the electrode inputs while allowing neural AC signals to pass through to the at least one amplifier. In some scenarios, the switch matrix module includes a digital control loop configured to automatically eliminate offset voltage potential in patient connected electrodes. The switch matrix module further includes a field programmable gate array (FPGA) configured to automatically reset a plurality of control lines of one or more multiplexers of the switch matrix module.

The present invention provides a main control device that can improve the amount of encoding setting signals received. [Solution] The main control unit includes a processing module, a first DIP switch, a second DIP switch, an inverting module, a first switch, and a second switch. The processing module has switching pins and a plurality of signal pins. The first DIP switch has a plurality of first signal switches connected to a plurality of signal pins. The second DIP switch has a plurality of second signal switches connected to a plurality of signal pins. One end of the inverting module is connected to the processing module. The first end of the first switch is connected to the plurality of first signal switches, the second end of the first switch is connected to one end of the inverting module and to the switching pins, and the third end of the first switch is connected to an operating voltage source. The first end of the second switch is connected to a plurality of second signal switches, the second end of the second switch is connected to the other end of the inverting module, and the third end of the second switch is connected to an operating voltage source.

An arrangement includes a matrix with a plurality of programmable logic units and a plurality of first one bit clocked storage elements, the programmable logic units and first one bit clocked storage elements being arranged in an array, the arrangement being adapted for sequential execution of at least two tasks, whereby for each of the first one bit clocked storage elements a data store and restore circuit is provided for local storing or restoring the respective values as computed during the tasks per task of the first one bit clocked storage elements;a data memory, external to the matrix, wherein the data store and restore circuit is provided for pre-loading values related to one task from the data memory into the data store and restore circuit and post-storing of values related to one task in the data store and restore circuit to the data memory, whereby the pre-loading and / or post-storing can be performed while another task is executed without disturbing the task execution; andan output circuit, required to ensure safe operation in case of task switching.

The present application provides an electrostatic discharge protection circuit, which includes an internal circuit, a Schottky diode and an electrostatic discharge release element. The Schottky diode is coupled between a specific node and the internal circuit. The electrostatic discharge release element is coupled between the specific node and a power supply terminal. When an electrostatic discharge event occurs at the specific node, the electrostatic discharge release element is turned on to release an electrostatic discharge current from the specific node to the power supply terminal. The present application can protect an integrated circuit.

The invention applies to the context of an electric machine system where the digital control is handled with a FPCU component. This applies to application domains like but not limited to the automotive domain. The invention enables fast and safe time sliced context switching for application tasks mapped in FLU e FPGA matrix, similar as for the task context switching in a microprocessor, with the goal to maximize the usage of all computation resources of the FLU over time.

An electrical system includes an integrated circuit device that includes an input / output (I / O) pin, a reset circuit, and an I / O circuit. The I / O circuit is operably coupled to the I / O pin. The I / O circuit is configured to selectively operate the I / O pin in an electrically floating state in response to a system reset signal emitted by the reset circuit. The I / O circuit is further configured to selectively operate the I / O pin in the electrically floating state in response to a signal provided by a timer circuit that is independent of the reset circuit.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I / O ports coupling to the set of data buses and at least one first I / O-port selection pad configured to select a first port from the plurality of first I / O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.