44results about "Programmable logic circuit arrangements" patented technology

A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.

Transitioning between using write commands and read commands for data transfer between distributed storage systems, including: determining that a network connection from a first storage system to a second storage system is used by a latency-sensitive application; and transitioning, in response to the network connection being used by the latency-sensitive application, the network connection from using write commands for data transfer between the first storage system and the second storage system to using read commands for data transfer between the first storage system and the second storage system.

The present application relate to the technical field of mobile communication, and in particular to a radio frequency chip, an algorithm reconstruction method and a computer-readable storage medium. The radio frequency chip includes a configuration interface, an interconnection bus, a processor and at least two operation units. Each operation unit is provided with different operation functions. The configuration interface is connected to the processor, and is configured to transmit the received routing information and the configuration data to the processor. The routing information and the configuration data are determined according to a target operation function of the radio frequency chip. The interconnection bus is communicated with each operation unit and is connected to the processor, and is configured to adjust an input and output relationship between each operation unit.

An integrated circuit (IC) includes an Input / Output (I / O) interface, first-domain circuitry and second-domain circuitry. The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

An application specific integrated circuit (ASIC) chip includes: a systolic array of cells; and multiple controllable bus lines configured to convey data among the systolic array of cells, in which the systolic array of cells is arranged in multiple tiles, each tile of the multiple tiles including 1) a corresponding subarray of cells of the systolic array of cells, 2) a corresponding subset of controllable bus lines of the multiple controllable bus lines, and 3) memory coupled to the subarray of cells.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

The main control device comprises a processing module with a switching pin and a plurality of signal pins, a first DIP switch, a second DIP switch, an inverting module, and a first switch and a second switch. The first DIP switch and second DIP switch are respectively connected to the signal pins through first and second signal switches. One end of the inverting module is connected to the processing module. The first switch connects to the first signal switches, the switching pin, the inverting module, and the operating voltage source. The second switch is connected to the second signal switches, the inverting module, and the operating voltage source.

The embodiments of the present invention provide a turnout position detection device and system, which relate to the railway field. The turnout position detection device includes a DC power supply group, a drive circuit connected to the DC power supply group, and a position detection circuit connected to the drive circuit. Therefore, compared with the prior art method of detecting turnout position using a polarity-biased relay that relies on an AC power supply, the technical solution provided by the embodiments of the present invention uses a DC power supply group to provide a more reliable signal and higher security. This can improve the problems of low safety factors and low reliability in the prior art, thereby improving reliability and safety. In addition, the turnout position detection device uses an electronic circuit to implement the functions performed by the polarity-biased relay in a switch machine, and has the following advantages: the electronic components take up less space; they can be plugged and unplugged under power, making replacement easy.

An integrated circuit (100) includes an Input / Output (I / O) interface (104), first-domain circuitry (108) and second-domain circuitry (110). The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

The present disclosure relates to a configurable interface circuit that supports a plurality of different, selectable operating modes. In one example, the interface circuit includes a device terminal that can be coupled to an external field device; a digital current path coupled to the device terminal and having a first sense resistor; and an analog current path having a second sense resistor.When the configurable interface circuit operates in the analog mode, an analog current can flow through the analog current path and an analog signal can be measured by measuring a voltage across the first sense resistor and the second sense resistor, and when the configurable interface circuit operates in the digital mode, a digital current is controlled to flow through the digital current path and a digital signal can be measured by measuring the voltage across the first sense resistor and the second sense resistor.

The present disclosure relates to a configurable interface circuit supporting a plurality of different selectable operational modes. In one example the interface circuit comprises a device terminal couplable to an external field device, a digital current path coupled to the device terminal, and having a first sense resistor, and an analog current path having a second sense resistor. When the configurable interface circuit is operating in the analog mode, an analog current can flow through the analog current path and an analog signal can be measured by measuring a voltage across the first sense resistor and second sense resistor, and when the configurable interface circuit is operating in the digital mode, a digital current is controlled to flow through the digital current path and a digital signal can be measured by measuring the voltage across the first sense resistor and second sense resistor.

The present disclosure relates to a configurable interface circuit supporting a plurality of different selectable operational modes. In one example the interface circuit comprises a device terminal couplable to an external field device, a digital current path coupled to the device terminal, and having a first sense resistor, and an analog current path having a second sense resistor. When the configurable interface circuit is operating in the analog mode, an analog current can flow through the analog current path and an analog signal can be measured by measuring a voltage across the first sense resistor and second sense resistor, and when the configurable interface circuit is operating in the digital mode, a digital current is controlled to flow through the digital current path and a digital signal can be measured by measuring the voltage across the first sense resistor and second sense resistor.

This application is applicable to the field of terminal technologies, and provides an interface circuit, an interface circuit protection method, and a terminal device. The interface circuit includes: a switching unit, a power input end, a first function pin, a second function pin, a control signal input end, a detection port, a grounding output end, a first resistor, a second resistor, a third resistor, a fourth resistor, and an on-off apparatus. Because the first resistor, the second resistor, the third resistor, and the fourth resistor are respectively connected in series as isolation resistors on their respective paths, when a short circuit occurs, a current flowing through the switching unit is less than a burnout current of the switching unit. In addition, when the switching unit does not work, the grounding output end of the switching unit is suspended by using the on-off apparatus, so that the switching unit is in a suspended state when the switching unit does not work, and is not burned down by a voltage that is input during a short circuit, thereby ensuring normal use of the interface.

One or more computing devices, systems, and / or methods are provided. In an example of the techniques presented herein, a system comprises a first input terminal and a first programmable analog block configured according to a first configuration. A controller is configured to reconfigure the first programmable analog block according to a second configuration different than the first configuration based on a first signal received at the first input terminal.

A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale / offset block communicatively coupled to the second FFT engine and the scale / offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.

An integrated circuit (IC) may include a plurality of compute tiles in a data processing array. Each compute tile is configured to perform a data processing function. The IC may include a plurality of interface tiles in the data processing array. The plurality of interface tiles are communicatively linked to the plurality of compute tiles. The IC may include a plurality of programmable stream switches disposed in the plurality of compute tiles and the plurality of interface tiles. The IC may include a functional safety circuit. The functional safety circuit is connected to a selected programmable stream switch of the plurality of programmable stream switches. The functional safety circuit is configured to perform a functional safety function on a plurality of data streams routed to the functional safety circuit from the selected programmable stream switch.

Identification of the types of input and output cards of a PLC and proper connection of field devices to a PLC are achieved by connecting a self-learning discrete input circuit and / or a self-learning discrete output circuit between the PLC and the field device.

An integrated circuit includes a region of logic circuits, first and second selector circuits, a first interface circuit for exchanging information with a first type of device according to a first communication protocol, and a second interface circuit for exchanging information with a second type of device according to a second communication protocol. The first selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the first or second interface circuits. The second selector circuit is configurable to provide signals between the selected one of the first or second interface circuits and the first or second type of device.

Methods and apparatus relate to a bidirectional differential interface (300) having a voltage-mode transmit driver architecture (325) formed of multiple selectively enabled slices for coarse output resistance impedance matching. In examples, the transmit driver (325) may include a programmable resistance (340) for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver (325) may have programmable voltage swing on, for example, the upper and / or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied in a termination network (335), for example, through common mode resistors for receive mode operations.

An integrated circuit (100) includes an Input / Output (I / O) interface (104), first-domain circuitry (108) and second-domain circuitry (110). The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

This application is applicable to the field of terminal technologies, and provides an interface circuit, a protection method for the interface circuit, and a terminal device. The interface circuit includes: a switching unit, a power input terminal, a first functional pin, a second functional pin, a control signal input terminal, a detection port, a ground output terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, and a switching device. Since the first resistor, the second resistor, the third resistor, and the fourth resistor are respectively connected in series as isolation resistors on their respective paths, when a short circuit occurs, the current flowing through the switching unit is less than the burnout current of the switching unit. And when the switching unit is not working, the ground output terminal of the switching unit is suspended through the switching device, so that the switching unit is in a floating state when not working and will not be burned by the voltage input during a short circuit, ensuring the normal use of the interface.

Disclosed herein are aspects for configuring a port in an integrated circuit using a configuration state machine. An example aspect begins by determining a current state of internal pull-up and pull-down resistors of the port. The aspect then modifies resistance characteristics of the resistors from the current state. These characteristics indicate a strap configuration of a circuitry connected to the port. The aspect determines a state result based on the strap configuration and the current state. The aspect transitions to a next state based on the state result. The aspect continues by modifying resistance characteristics of the resistors from the next state, indicating a second strap configuration. A second state result is then determined based on the second strap configuration and the next state. The aspect then transitions to a resultant terminal state based on the next state and configures the port to operate in accordance with a port configuration.

An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

An I2C interface circuit (10; 30; 40) is operatable at a low pull-up voltage and at a high pull-up voltage. A first pin (12a) receives a clock signal (I2Cclk) and a second pin (12b) receives a data signal (I2Cdata). A first comparator stage (24a) compares the received clock signal to a low threshold and a high threshold to produce an internal clock signal (clk_in). A second comparator stage (24b) compares the received data signal to the low threshold and the high threshold to produce an internal data signal (data_in). The first comparator stage and the second comparator stage are programmed by default to operate in a first operating mode, wherein the low threshold is set to a first fractional value of the high pull-up voltage and the high threshold is set to a second fractional value of the low pull-up voltage. The first comparator stage and the second comparator stage are switchable, upon reception via the I2C interface of a programming frame that conveys a current value of the pull-up voltage, to a second operating mode. In the second operating mode, the low threshold is set to the first fractional value of the current pull-up voltage and the high threshold is set to the second fractional value of the current pull-up voltage.

Provided is a data transmission circuit that includes first and second drive circuits and an operation state control circuit. The first drive circuit drives first data that transitions or does not transition in synchronization with a clock signal. The second drive circuit drives second data that transitions at a timing when the first data does not transition in synchronization with the clock signal. The operation state control circuit individually controls operation states of the first and second drive circuits.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I / O ports coupling to the set of data buses and at least one first I / O-port selection pad configured to select a first port from the plurality of first I / O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

An I2C interface circuit (10; 30; 40) is operatable at a low pull-up voltage and at a high pull-up voltage. A first pin (12a) receives a clock signal (I2Cclk) and a second pin (12b) receives a data signal (I2Cdata). A first comparator stage (24a) compares the received clock signal to a low threshold and a high threshold to produce an internal clock signal (clk_in). A second comparator stage (24b) compares the received data signal to the low threshold and the high threshold to produce an internal data signal (data_in). The first comparator stage and the second comparator stage are programmed by default to operate in a first operating mode, wherein the low threshold is set to a first fractional value of the high pull-up voltage and the high threshold is set to a second fractional value of the low pull-up voltage. The first comparator stage and the second comparator stage are switchable, upon reception via the I2C interface of a programming frame that conveys a current value of the pull-up voltage, to a second operating mode. In the second operating mode, the low threshold is set to the first fractional value of the current pull-up voltage and the high threshold is set to the second fractional value of the current pull-up voltage.

An integrated circuit (100) includes an input / output (I / O) interface (104), a first domain circuit (108), and a second domain circuit (110). The I / O interface is coupled to a first voltage domain and configurable by a set of control bits. The second domain circuit is coupled to a second voltage domain and is configured to generate a bit value for a control bit of the control bits, generate a multi-bit identifier (ID) for the control bit, and transmit the bit value and the multi-bit ID. The first domain circuit is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, identify the control bit from the multi-bit ID, and configure the control bit of the I / O interface with the bit value.

A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale / offset block communicatively coupled to the second FFT engine and the scale / offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.

A main control device includes a processing module, a first dial, a second dial, a reverse module, a first switch, and a second switch. The processing module has a switching pin and a plurality of signal pins. The first dial has a plurality of first signal switches respectively connected to the plurality of signal pins. The second dial has a plurality of second signal switches respectively connected to the plurality of signal pins. One end of the reverse module is connected to the processing module. The first end of the first switch is connected to the plurality of first signal switches, the second end of the first switch is connected to one end of the reverse module and the switching pin, and the third end of the first switch is connected to an operating voltage source. The first end of the second switch is connected to the plurality of second signal switches, the second end of the second switch is connected to the other end of the reverse module, and the third end of the second switch is connected to the operating voltage source.