2results about "Programmable logic circuit arrangements" patented technology

Disclosed herein are apparatus, system, method, and computer-readable medium aspects for interfacing a MIPI transmitter with a SERDES receiver. An example method aspect includes receiving first and second MIPI signals at respective inputs and level-shifting each signal using corresponding diodes. The level-shifted signals are applied to the base terminals of first and second transistors, whose emitters are coupled together. A control current is generated via a current mirror formed by a third and fourth transistor, with the current set by a control voltage. This control current is supplied to the coupled emitters, enabling the production of differential output signals at the collector terminals of the first and second transistors for input to a SERDES receiver.

A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.