59results about "Logic circuits coupling/interface with bidirectional operation" patented technology

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

The present disclosure relates to a surgical instrument capable of single-wire digital communication via a differential bus. More specifically, it relates to a single-wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument incorporating the single-wire digital communication system. The single-wire digital communication system includes a first transmitter logic buffer and a first receiver logic buffer operably coupled to a first single-wire device via a first single-wire communication bus. The single-wire digital communication system further includes a first differential transceiver operational amplifier that is operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single-wire device is operably coupled to the differential bus and configured to communicate with the first single-wire device.

A device for transmitting first data to an external device and receiving second data from the external device is provided. The device includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; a current source circuit connected to a second node and including a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit, based on the first data; a receiver connected to the second node and configured to obtain the second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

An integrated circuit (IC) includes an Input / Output (I / O) interface, first-domain circuitry and second-domain circuitry. The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

A device for transmitting first data to an external device and receiving second data from the external device is provided. The apparatus includes: a voltage mode driver connected to a first node, the voltage mode driver including a pull-up resistor circuit and a pull-down resistor circuit, the pull-up resistor circuit including a plurality of pull-up resistors, and the pull-down resistor circuit including a plurality of pull-down resistors; the current source circuit is connected to the second node and comprises a first current source and a second current source; a pre-driver configured to control the voltage mode driver and the current source circuit based on first data; a receiver connected to the second node and configured to obtain second data based on a voltage level of the second node; and a hybrid resistor connected between the first node and the second node.

An integrated circuit (100) includes an Input / Output (I / O) interface (104), first-domain circuitry (108) and second-domain circuitry (110). The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

An integrated circuit includes a communication controller circuit for exchanging communications with a device external to the integrated circuit through a signal line, a current circuit coupled to the signal line, and a current controller circuit for causing the current circuit to provide a constant current to the signal line while a signal is transmitted through the signal line based on a command generated by the communication controller circuit.

A method for electrostatic discharge (ESD) protection of a chip is disclosed. The chip includes a driver, a first tri-state buffer, and a second tri-state buffer, wherein an output of the driver is coupled to a pad, an output of the first tri-state buffer is coupled to a first input of the driver, and an output of the second tri-state buffer is coupled to a second input of the driver. The method includes, during a normal mode, driving the first input of the driver with a first data signal using the first tri-state buffer and driving the second input of the driver with a second data signal using the second tri-state buffer. The method also includes detecting an ESD event on the pad, and, in response to detecting the ESD event, putting each of the first tri-state buffer and the second tri-state buffer in a high impedance output state.

A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.

Multi-bit level converter (10, 200), comprising: a plurality of level converters (10, 200), each configured to receive an input signal in a first voltage domain and to provide a corresponding output signal in a second voltage domain, each of the plurality of level converters (10, 200) comprising an enable node (240); and an enabling circuit (100) having an output terminal (104, 204, 205) connected to the enabling node (240) of each of the plurality of level converters (10, 200), and having a first network terminal configured to receive a first voltage in the first voltage domain; wherein each of the plurality of level converters (10, 200) is configured to output the corresponding output signal in response to an enable signal received by the enable circuit (100) and each has a second mains connection configured to receive a second voltage in the second voltage domain, and furthermore has: a first inverter (210) connected to the first network connection, wherein the first inverter has an input (202) connected to an input (202) of the level converter (10, 200); a first PMOS transistor (220) comprising a source connected to the second mains terminal and a gate connected to a first output (104, 204, 205, 304) of the level converter (10, 200); a second inverter (212) having an input (202) connected to an output (104, 204, 205, 304) of the first inverter (210); a first NMOS transistor (230) comprising a drain connected to a drain of the first PMOS transistor (220) and a gate connected to an output (104, 204, 205, 304) of the second inverter (212), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the first NMOS transistor (230); a second PMOS transistor (222) comprising a source connected to the second mains terminal and a gate connected to a drain of the first PMOS transistor (220) and a second output (104, 204, 205, 304) of the level shifter (10, 200); and a second NMOS transistor (232) comprising a drain connected to a drain of the second PMOS transistor (222) and a gate connected to the output (104, 204, 205, 304) of the first inverter (210), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the second NMOS transistor (232); wherein the first output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide the corresponding output signal in the second voltage domain and the second output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide a complementary output signal in the second voltage domain.

The invention discloses a level conversion circuit and a chip, and relates to the technical field of circuits. The level conversion circuit comprises a first switch, a second switch, a first step-down circuit, a second step-down circuit, a first boost circuit, a second boost circuit and a third boost circuit. A first control signal is configured to be a first voltage value or a second voltage value, and a second control signal is configured to be a third voltage value or a fourth voltage value to control the on or off of a first switch and a second switch, so that the functions of one-way level conversion, two-way level conversion and level conversion closing are realized; in practical application, the direction of level conversion can be flexibly adjusted, and the influence caused by signal connection of two ports between chips or inside the chips is avoided.

A processing chip component according to one embodiment comprises: a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit; a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; and an interconnect layer disposed between the first die and the second die. The interconnect layer may comprise a first through silicon via (TSV) connecting the first SERDES circuit and the second SERDES circuit in order to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

An integrated circuit (100) includes an Input / Output (I / O) interface (104), first-domain circuitry (108) and second-domain circuitry (110). The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second-domain circuitry is coupled to a second voltage domain and is configured to generate a bit value for a control bit among the control bits, to generate a multi-bit identifier (ID) of the control bit, and to transmit the bit value and the multi-bit ID. The first-domain circuitry is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, to identify the control bit from the multi-bit ID, and to configure the control bit of the I / O interface with the bit value.

The present invention relates to a device 30 for synchronous serial data transmission over a differential data channel 62 and a differential clock channel 60. The device comprises an interface controller 40 having a clock generator 44 and a data controller 42, a clock transmission module 50, and a data reception module 54, in which: a transmitter clock signal CLK_S comprising a periodic pulse train TP having a periodic duration T during a data transmission period can be generated by said clock generator 44; the transmitter clock signal CLK_S is supplied to the clock transmitter module 50, which converts the transmitter clock signal CLK_S into a differential clock signal C+, C− for output via the clock channel 60; the differential data signals D+, D− arriving via the differential data channel 62 are supplied to the data receiving module 54, which converts the differential data signals D+, D− into a data signal DT and supplies it to the data controller 42, The transmitter clock signal CLK_S is supplied to the data controller 42 for synchronization with the input of the data signal DT. The clock generator 44 is suitably configured to set the length of the first clock period TH1 of the first clock period T1 of the clock pulse train TP to be longer than the first clock period TH of the subsequent clock period and shorter than the period required to reach the maximum differential voltage UDmax during a data transmission period in a dynamic operating state in which the maximum differential voltage generated by the differential clock signals C+, C- is smaller than the maximum differential voltage UDmax of the clock transmission module 50. Furthermore, the present invention relates to a method for synchronously transmitting serial data (FIG. 1).

A bidirectional level shifter with fast rise and fall times and low current leakage is suitable for use with devices connected using an SPMI bus. The level shifter transfers signals between a first voltage domain and a second voltage domain operating at different voltage levels. The level shifter has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is between a first voltage source and the first terminal, and a second switch is between a second voltage source and the second terminal. The first switch and the second switch are operable to reduce current leakage of the level shifter.

According to an embodiment, a processing chip component includes a first die including first circuitry, second circuitry, and first SERDES circuitry connected to the first circuitry and the second circuitry, a second die including third circuitry, fourth circuitry and second SERDES circuitry connected to the third circuitry and the fourth circuitry, and an interconnect layer disposed between the first die and the second die. The interconnect layer includes a first through silicon via (TSV) configured to be connected between the first SERDES circuitry and the second SERDES circuitry and to provide a first signal path between the first circuitry and the third circuitry, a second signal path between the first circuitry and the fourth circuitry, a third signal path between the second circuitry and the third circuitry, and a fourth signal path between the second circuitry and the fourth circuitry.

A method for electrostatic discharge (ESD) protection of a chip is disclosed. The chip includes a driver, a first tri-state buffer, and a second tri-state buffer, wherein an output of the driver is coupled to a pad, an output of the first tri-state buffer is coupled to a first input of the driver, and an output of the second tri-state buffer is coupled to a second input of the driver. The method includes, during a normal mode, driving the first input of the driver with a first data signal using the first tri-state buffer and driving the second input of the driver with a second data signal using the second tri-state buffer. The method also includes detecting an ESD event on the pad, and, in response to detecting the ESD event, putting each of the first tri-state buffer and the second tri-state buffer in a high impedance output state.

The present disclosure relates to a bi-directional bus repeater. The present disclosure further relates to a communication bus including a bi-directional bus repeater, and to a communication system including the communication bus. The bi-directional bus repeater includes a first input terminal, a second input terminal, a first pulldown element connected to the first input terminal, and a second pulldown element connected to the second input terminal. By ensuring that the activation of the first and second pulldown elements is dependent on the state of the corresponding input terminal and the detection of a high-to-low transition of the corresponding other input terminal, the problem of self-locking can be avoided or at least minimized.

An interface circuit includes a first switching element connected to a first power supply node and an output node and controlled by a first input signal, a second switching element connected to a second power supply node and the output node and controlled by a second input signal, a first resistor connected between the first power supply node and the first switching element, a second resistor connected between the second power supply node and the second switching element, a first capacitor connected between the first resistor and the first switching element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switching element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node through a first variable resistor and to a fourth power supply node through a second variable resistor.

Electronic circuit for supplying a ramp digital signal This description relates to an electronic circuit (10) for supplying a digital signal (Sn) comprising a succession of ramps, the electronic circuit being clocked by a clock signal, the electronic circuit being configured to supply a number Nout of digital values ​​of the digital signal at each cycle of the clock signal, Nout being strictly greater than 1.The electronic circuit comprises a first memory (30) in which initial data is stored for each ramp, and a second memory (32) in which second data relating to the number of clock signal cycles over which some of the ramps span is stored, and a first circuit (40) configured to read from the first memory the initial data relating to several successive ramps and from the second memory the second data associated with said several successive ramps, and to provide said numerical values. Figure for the abstract: Fig. 9.

A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.

The present invention discloses an adaptive sampling interface circuit. When the input source is a voltage source, the back-end sampling circuit is entered through a voltage follower, and the positive and negative judgment is implemented by a comparator + MOS tube. Due to the flexible use of the voltage follower and the comparator, the input interface has a high impedance, which can effectively prevent the sampling signal from interfering with the internal signal, thereby ensuring the accuracy and reliability of the sampling circuit. When the input source is a current source, it is implemented by sampling first and then inputting. Since the implementation principles of the voltage follower and the comparator are both operational amplifiers, their input terminals are in a high-impedance state, so all voltages generated on the resistor can be regarded as the embodiment of the input current signal on the sampling resistor. In the circuit, the present invention can sample normally without distinguishing between voltage and current signals.

The present disclosure relates to a bi-directional communication-based control apparatus and system, and a bi-directional communication interface. The technical problem to be solved provides topology capable of implementing hardwired contactor control using a single port (P) of a micro controller unit, MCU, (200) without being constrained by restrictions on the number of ports of the MCU (200) which may be required depending on design specifications of an electronic control unit, ECU, and a battery management system, BMS. To this end, the present disclosure provides a processor (100) that controls a target element (200, 300) according to a control signal applied to a communication bus (B) and causes state information of the target element (200, 300) according to a result of the control to be formed on a communication bus (B), the control signal being input and a state signal for forming the state information being output through a single bi-directional port (P) provided in the processor (200); and an arbitrator (300) that arbitrates first direction transmission of the control signal from the communication bus (B) to the bi-directional port (P) and second direction transmission of the state signal from the bi-directional port (P) to the communication bus (B).

An integrated circuit (100) includes an input / output (I / O) interface (104), a first domain circuit (108), and a second domain circuit (110). The I / O interface is coupled to a first voltage domain and configurable by a set of control bits. The second domain circuit is coupled to a second voltage domain and is configured to generate a bit value for a control bit of the control bits, generate a multi-bit identifier (ID) for the control bit, and transmit the bit value and the multi-bit ID. The first domain circuit is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, identify the control bit from the multi-bit ID, and configure the control bit of the I / O interface with the bit value.

Apparatus and associated methods relate to an integrated power-on reset system (PORS) at the system-on-chip (SoC) level. In an illustrative example, an integrated circuit (215) may include a first power domain (300a) and a second power domain (300b). A level shifter circuit (300c) may be coupled to convert data from the first power domain to the second power domain. A PORS (270) including voltage detection circuits (410, 470a, 470b), glitch filter circuits (415, 475a, 475b), and logic gates (420a, 420b) may be configured to generate isolation signals (310, 320) between the first power domain (300a) and the second power domain (300b). The level shifter circuit (300c) may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on the IC (215) may be comprehensively managed during power-on to avoid unstable operation.

A semiconductor device includes a first chip and a second chip. Each chip includes a high-side pad that receives a high-side voltage, a low-side pad that receives a low-side voltage, two or more control pads, an input pad, an output pad, and a functional circuit. In each chip, the two or more control pads are each pulled down to the low-side voltage or pulled up to the high-side voltage. In each chip, the two or more control pads include a target control pad that receives an external control signal. In each chip, an internal control signal is generated on the basis of two or more signals applied to the two or more control pads, and an operation of the functional circuit is controlled on the basis of the internal control signal.

The present disclosure relates to a slave computer, a connector, a slave computer assembly, and a communication system. According to one embodiment of the present disclosure, a slave computer for connecting a device to a host computer includes a USB port having pins 1 to 5, a power switch connected to the first and fourth pins, an RS232 module configured to convert the levels of signals sent to and received from the device based on the RS232 standard, a resistor connected between the fourth and fifth pins, and a power supply having a positive terminal, the positive terminal being connected to the first pin, the RS232 module being connected to the first pin via the power switch, and the power switch being configured to open a conductive path between the positive terminal and the RS232 module in response to the potential at the fourth pin being high.

The invention relates to a control device and system based on two-way communication and a two-way communication interface. The solved technical problem provides a topology that enables hardwired contactor control using a single port of a microcontroller unit (MCU) without being constrained by limitations on the number of MCU ports that may be needed depending on design specifications of an electronic control unit (ECU) and a battery management system (BMS). To this end, the present disclosure provides: a processor that controls a target element in accordance with a control signal applied to a communication bus, and causes state information of the target element to be formed on the communication bus in accordance with a control result, the control signal being input through a single bidirectional port provided in the processor, and a state signal for forming the state information being output; and an arbiter that arbitrates a first direction transmission of the control signal from the communication bus to the bidirectional port and a second direction transmission of the status signal from the bidirectional port to the communication bus.

The present disclosure relates to a bi-directional communication-based control apparatus and system, and a bi-directional communication interface. The technical problem to be solved provides topology capable of implementing hardwired contactor control using a single port of a micro controller unit (MCU) without being constrained by restrictions on the number of ports of the MCU which may be required depending on design specifications of an electronic control unit (ECU) and a battery management system (BMS). To this end, the present disclosure provides a processor that controls a target element according to a control signal applied to a communication bus and causes state information of the target element according to a result of the control to be formed on a communication bus, the control signal being input and a state signal for forming the state information being output through a single bi-directional port provided in the processor; and an arbitrator that arbitrates first direction transmission of the control signal from the communication bus to the bi-directional port and second direction transmission of the state signal from the bi-directional port to the communication bus.