11results about "Logic circuits coupling/interface with bidirectional operation" patented technology

A method for electrostatic discharge (ESD) protection of a chip is disclosed. The chip includes a driver, a first tri-state buffer, and a second tri-state buffer, wherein an output of the driver is coupled to a pad, an output of the first tri-state buffer is coupled to a first input of the driver, and an output of the second tri-state buffer is coupled to a second input of the driver. The method includes, during a normal mode, driving the first input of the driver with a first data signal using the first tri-state buffer and driving the second input of the driver with a second data signal using the second tri-state buffer. The method also includes detecting an ESD event on the pad, and, in response to detecting the ESD event, putting each of the first tri-state buffer and the second tri-state buffer in a high impedance output state.

Multi-bit level converter (10, 200), comprising: a plurality of level converters (10, 200), each configured to receive an input signal in a first voltage domain and to provide a corresponding output signal in a second voltage domain, each of the plurality of level converters (10, 200) comprising an enable node (240); and an enabling circuit (100) having an output terminal (104, 204, 205) connected to the enabling node (240) of each of the plurality of level converters (10, 200), and having a first network terminal configured to receive a first voltage in the first voltage domain; wherein each of the plurality of level converters (10, 200) is configured to output the corresponding output signal in response to an enable signal received by the enable circuit (100) and each has a second mains connection configured to receive a second voltage in the second voltage domain, and furthermore has: a first inverter (210) connected to the first network connection, wherein the first inverter has an input (202) connected to an input (202) of the level converter (10, 200); a first PMOS transistor (220) comprising a source connected to the second mains terminal and a gate connected to a first output (104, 204, 205, 304) of the level converter (10, 200); a second inverter (212) having an input (202) connected to an output (104, 204, 205, 304) of the first inverter (210); a first NMOS transistor (230) comprising a drain connected to a drain of the first PMOS transistor (220) and a gate connected to an output (104, 204, 205, 304) of the second inverter (212), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the first NMOS transistor (230); a second PMOS transistor (222) comprising a source connected to the second mains terminal and a gate connected to a drain of the first PMOS transistor (220) and a second output (104, 204, 205, 304) of the level shifter (10, 200); and a second NMOS transistor (232) comprising a drain connected to a drain of the second PMOS transistor (222) and a gate connected to the output (104, 204, 205, 304) of the first inverter (210), wherein the enable node (240) of the level shifter (10, 200) comprises a source of the second NMOS transistor (232); wherein the first output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide the corresponding output signal in the second voltage domain and the second output (104, 204, 205, 304) of the level converter (10, 200) is configured to provide a complementary output signal in the second voltage domain.

A bidirectional level shifter with fast rise and fall times and low current leakage is suitable for use with devices connected using an SPMI bus. The level shifter transfers signals between a first voltage domain and a second voltage domain operating at different voltage levels. The level shifter has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is between a first voltage source and the first terminal, and a second switch is between a second voltage source and the second terminal. The first switch and the second switch are operable to reduce current leakage of the level shifter.

According to an embodiment, a processing chip component includes a first die including first circuitry, second circuitry, and first SERDES circuitry connected to the first circuitry and the second circuitry, a second die including third circuitry, fourth circuitry and second SERDES circuitry connected to the third circuitry and the fourth circuitry, and an interconnect layer disposed between the first die and the second die. The interconnect layer includes a first through silicon via (TSV) configured to be connected between the first SERDES circuitry and the second SERDES circuitry and to provide a first signal path between the first circuitry and the third circuitry, a second signal path between the first circuitry and the fourth circuitry, a third signal path between the second circuitry and the third circuitry, and a fourth signal path between the second circuitry and the fourth circuitry.

A method for electrostatic discharge (ESD) protection of a chip is disclosed. The chip includes a driver, a first tri-state buffer, and a second tri-state buffer, wherein an output of the driver is coupled to a pad, an output of the first tri-state buffer is coupled to a first input of the driver, and an output of the second tri-state buffer is coupled to a second input of the driver. The method includes, during a normal mode, driving the first input of the driver with a first data signal using the first tri-state buffer and driving the second input of the driver with a second data signal using the second tri-state buffer. The method also includes detecting an ESD event on the pad, and, in response to detecting the ESD event, putting each of the first tri-state buffer and the second tri-state buffer in a high impedance output state.

An interface circuit includes a first switching element connected to a first power supply node and an output node and controlled by a first input signal, a second switching element connected to a second power supply node and the output node and controlled by a second input signal, a first resistor connected between the first power supply node and the first switching element, a second resistor connected between the second power supply node and the second switching element, a first capacitor connected between the first resistor and the first switching element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switching element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node through a first variable resistor and to a fourth power supply node through a second variable resistor.

A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.

A semiconductor device includes a first chip and a second chip. Each chip includes a high-side pad that receives a high-side voltage, a low-side pad that receives a low-side voltage, two or more control pads, an input pad, an output pad, and a functional circuit. In each chip, the two or more control pads are each pulled down to the low-side voltage or pulled up to the high-side voltage. In each chip, the two or more control pads include a target control pad that receives an external control signal. In each chip, an internal control signal is generated on the basis of two or more signals applied to the two or more control pads, and an operation of the functional circuit is controlled on the basis of the internal control signal.

A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.

A processing chip assembly according to one embodiment includes: a first die including a first circuit, a second circuit, and a first SERDES circuit connected to the first circuit and the second circuit; a second die including a third circuit, a fourth circuit, and a second SERDES circuit connected to the third circuit and the fourth circuit; and an interconnection layer, wherein the interconnection layer is arranged between the first bare chip and the second bare chip. The interconnect layer may include a first through silicon via (TSV), the first TSV connecting the first SERDES circuit and the second SERDES circuit, and the second TSV connecting the first SERDES circuit and the second SERDES circuit. The second circuit is coupled to the third circuit so as to provide a first signal path between the first circuit and the third circuit, a second signal path between the first circuit and the fourth circuit, a third signal path between the second circuit and the third circuit, and a fourth signal path between the second circuit and the fourth circuit.

The invention relates to an integrated circuit for conditioning an oscillating analog signal comprising a succession of damped oscillations, the integrated circuit comprising an input / output (IO) cell having: - a first port (PAD) configured to receive said oscillating analog signal, called input signal, - a second port (ANA) configured to deliver an analog output signal from the input signal, - control means coupled between the first port and the second port and configured to suppress at least the first oscillation from the input signal so as to deliver in the output signal oscillations of the input signal having an amplitude less than a first threshold.