448results about "Logic circuit interface arrangements" patented technology

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

The invention provides an anti-common-mode transient interference circuit, a receiving circuit and a digital isolator, and the anti-common-mode transient interference circuit comprises a demodulation module which is electrically connected with an isolation capacitor of a receiving end, and demodulates a received carrier signal, so as to output an intermediate digital signal; and the filtering module is electrically connected with the demodulation module and is used for removing noise caused by the common-mode transient event in the intermediate digital signal so as to output a target digital signal. According to the invention, the filtering module is additionally arranged to remove the noise caused by the common-mode transient event and carried in the intermediate digital signal, so as to obtain the clean target digital signal, reduce the influence of the common-mode transient event on other links in the circuit system, and facilitate the subsequent function module in the circuit system to process the target digital signal.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

One example discloses a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

The present disclosure relates to a level shifter test circuit, a method of testing a level shifter test circuit, and a semiconductor chip. The circuit comprises a first level shifter for translating a signal from a first domain to a second domain. The first level shifter configured to receive the signal as an input from the first domain; and output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal. The circuit further comprises test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.

A receiver circuit is configured to generate, based on a clock signal, a first output signal by differentially amplifying an input signal and a reference voltage and to generate, based on a complementary clock signal, a second output signal by differentially amplifying the input signal and the reference voltage. The receiver circuit is configured to generate a first delay output signal and a second delay output signal by delaying the first output signal and the second output signal. The receiver circuit is configured to variably delay the first output signal based on the first output signal and the reference voltage and to variably delay the second output signal based on the second output signal and the reference voltage.

The invention belongs to the field of electronic circuits, and provides a level conversion circuit, a switching power supply chip and electronic equipment. The circuit comprises a voltage output module, a logic module and a comparison module. First ends of the voltage output module and the logic module receive output voltage. The second end of the voltage output module is connected with the second end of the logic module and the first end of the comparison module. The second end of the comparison module receives reference voltage, and the third end is connected with the third end of the logic module; the fourth end of the logic module outputs target voltage, and the fifth end and the third end of the voltage output module are both grounded. In the starting process of the boost switching power supply chip, when the output voltage is smaller than a preset value, the voltage output module outputs a first voltage. The comparison module outputs a first comparison signal according to the first voltage and a reference voltage. The logic module enables the fourth end and the fifth end of the logic module to be conducted according to the first comparison signal, the target voltage is made to be 0V, then the voltage margin is the output voltage, and compared with an existing circuit, the voltage margin is increased.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

A first circuit receives a single-ended signal and a reference voltage. The first circuit shifts a common mode of the single-ended signal based on a level-shifting current. A preamplifier receives the single-ended signal and the reference voltage from the first circuit and amplifies the single-ended signal to obtain an amplified signal. A decision feedback equalizer (DFE) system receives the amplified signal and the reference voltage from the preamplifier. The DFE system generates a first average signal height of the amplified signal above the reference voltage and a second average signal height of the amplified signal below the reference voltage. A second circuit provides the level-shifting current to the first circuit and adjusts the level-shifting current based on a linearity parameter associated with the amplified signal.

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

The invention provides a buffer circuit. The buffer circuit comprises a level shift module and a first operational amplifier, the first input end of the first operational amplifier receives an input signal; in the first stage of each sampling period, the level shift module is pre-charged with preset voltage; in the second stage of each sampling period, the input end of the level displacement module is connected with the output end of the first operational amplifier, the output end of the level displacement module is connected with the second input end of the first operational amplifier, and the level displacement module is used for translating the level of a first output signal of the first operational amplifier through a preset voltage; and obtaining a second output signal. By establishing the preset voltage in the level shift module in the first stage, the buffer circuit is closer to the working interval of the second output signal when entering the second stage, so that the establishment time of the second output signal is shortened, the transient response performance of the second output signal is improved, and the precision of the buffer circuit is improved.

Systems and methods are provided for a multiple power supply mode input / output (IO) circuit of an integrated circuit that includes a plurality of power rails, one or more supply mode power rails being associated with each supply mode of the integrated circuit, and a core power rail being associated with core circuitry of the integrated circuit. The IO circuit may further include a plurality of chip connection points, each chip connection point being connected to one or more of the power rails, the chip connection points being configured for connection to one or more package connection points.

The present application relates to the field of switch control technology, and provides a switch channel switching method, system, terminal device and storage medium. The switch channel switching method provided by the present application includes a control board, at least one function board and at least two radio frequency switch groups, wherein the control output port of the control board is connected to the control input port of the function board, and the output interface of the function board is connected to the control pin of the radio frequency switch group, including: receiving channel switching control information through the control board; processing the channel switching control information through the control board to obtain a control signal, and transmitting the control signal to the radio frequency switch group after preset processing by the function board; completing the switching of the switch channel by the radio frequency switch group according to the control signal after preset processing by the function board, which can effectively reduce the difficulty of device control and improve device stability.

A signal transmission device includes a first and a second circuit, in which the first circuit includes: a transmitter configured to generate a transmission signal according to an input signal; a first receiver configured to feed a first reception signal to a first logic circuit to generate a first single output signal; and at least one first isolating element arranged between the transmitter and the first receiver and configured to constitute a first signal transmission path for transmission of the transmission signal from the transmitter and output the first reception signal to the first receiver. The second circuit includes: a second receiver configured to generate a second single output signal; and a second isolating element arranged between the first logic circuit and the second receiver and configured to constitute a second signal transmission path, different from the first signal transmission path, for transmission of the transmission signal from the transmitter.

The invention discloses a power supply time sequence control circuit for a PCIe board card, relates to the technical field of power supply time sequence control, and aims to solve the problems of strong temperature sensitivity, insufficient precision, poor anti-interference capability and the like of a traditional power supply time sequence control scheme based on resistors and capacitors. The power supply time sequence control circuit comprises a power supply input module, a plurality of VRM modules and a control module, the control module starts a power-on process by detecting the stability of the power supply input module, monitors the state of the turned-on power supply by using a GPIO interface, and controls the enabling of the next-stage power supply according to a preset time sequence after confirming that the upper-stage power supply is stable, so that the orderly power-on of the multi-stage power supply is realized, and meanwhile, the circuit can be integrated with an electronic switch to realize the automatic switching of 12V voltage. The method is suitable for various PCIe board cards with high requirements on the power supply time sequence precision and stability, can effectively guarantee the stable operation of the board cards, and improves the reliability and adaptability of the whole power supply management.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

Certain aspects of the present disclosure generally relate to power supply circuits and techniques for load voltage drop compensation. An example power supply circuit generally includes: a power stage coupled between the power stage and an output node of the power supply circuit; a feedback circuit coupled to the output node of the power supply circuit and including a feedback node; a level-shifter circuit including an input coupled to the feedback node; and a first current source coupled between the level-shifter circuit and a node of the feedback circuit.

The invention relates to the technical field of integrated circuits and provides an impedance adjusting method based on hybrid control and a resistance network. The method comprises: connecting a target resistor between a ground terminal and the second terminal such that the target resistor and the resistor network are connected in series between the first terminal and the ground terminal; closing all binary code switches of the binary code resistor array, and then gradually changing the thermometer code control code according to a first preset step length; maintaining the first thermometer code control code, and then gradually changing the binary code control code according to a second preset step length; and determining a hybrid control code of the resistance network corresponding to the resistance value of the target resistor. Therefore, not only is the problem of an intermediate transition state effectively solved, but also the complexity caused by excessive bit control bits is reduced as much as possible under the condition that the same precision is realized.

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

The invention discloses a wetting current circuit and an interface circuit, relates to the field of integrated circuit design, and solves the problems that an interface chip cannot normally output wetting current under a specific working condition, and even the interface chip is damaged. The wetting current circuit comprises: a current port for outputting a wetting current; a first end of the first current source module is connected with a first control signal, a second end is grounded, a third end is connected with the current port, and the first current source module is used for outputting pull current according to the first control signal; one end of the first anti-reverse module is connected to the chip power supply, the other end is connected with the first current source module, and the first anti-reverse module is used for isolating a forward path from the current port to the chip power supply; one end of the second current source module is connected to a second control signal, and the other end is grounded for outputting sink current according to the second control signal; and one end of the second anti-reverse module is connected with the second current source module, the other end of the second anti-reverse module is connected with the current port and the first current source module, and the second anti-reverse module is used for isolating a forward path from the chip ground to the current port.

A circuit includes a semiconductor substrate, a first ground terminal, a second ground terminal, a driver circuit, a capacitor, a receiver circuit, and a substrate bias circuit. The driver circuit is on the semiconductor substrate. The driver circuit is coupled to the first ground terminal, and has a first output and a second output. The capacitor has a first terminal coupled to the first output of the driver circuit and a second terminal. The receiver circuit is on the semiconductor substrate. The receiver circuit is coupled to the second ground terminal, and has a first input coupled to the second terminal of the capacitor, and a second input coupled to the second output of the driver circuit. The substrate bias circuit has a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

The embodiment of the application discloses a kind of digital isolator and digital signal transmission method, the technical scheme of the embodiment of the application is by encoding circuit the rising edge and the falling edge of input digital signal are encoded into first pulse sequence and second pulse sequence respectively, by including multiple first pulse groups with time interval being first length characterizing first pulse sequence, multiple second pulse groups with time interval being second length characterizing second pulse sequence, so that more information is added in encoding signal, and the corresponding encoding information of rising edge and falling edge is transmitted through isolating element, while realizing the encoding and transmission of input digital signal, the anti-interference ability of encoding information and the anti-interference performance of digital isolator are improved.

This application provides a level shifting circuit and related electronic equipment. The circuit includes: a differential signal module, a voltage withstand module, a reset module, and a signal latch module. The first output terminal of the differential signal module is connected to the first input terminal of the voltage withstand module, and the second output terminal of the differential signal module is connected to the second input terminal of the voltage withstand module. The third input terminal of the voltage withstand module is connected to the first output terminal of the signal latch module, and the fourth input terminal of the voltage withstand module is connected to the second output terminal of the signal latch module. The first output terminal of the voltage withstand module is connected to the first input terminal of the signal latch module, and the second output terminal of the voltage withstand module is connected to the second input terminal of the signal latch module. The output terminal of the reset module is connected to the third and fourth input terminals of the signal latch module. The second output terminal of the signal latch module is the output terminal of the level shifting circuit. This application is capable of transmitting signals between two different voltage domains.

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.