239results about "Logic circuit interface arrangements" patented technology

The invention provides an anti-common-mode transient interference circuit, a receiving circuit and a digital isolator, and the anti-common-mode transient interference circuit comprises a demodulation module which is electrically connected with an isolation capacitor of a receiving end, and demodulates a received carrier signal, so as to output an intermediate digital signal; and the filtering module is electrically connected with the demodulation module and is used for removing noise caused by the common-mode transient event in the intermediate digital signal so as to output a target digital signal. According to the invention, the filtering module is additionally arranged to remove the noise caused by the common-mode transient event and carried in the intermediate digital signal, so as to obtain the clean target digital signal, reduce the influence of the common-mode transient event on other links in the circuit system, and facilitate the subsequent function module in the circuit system to process the target digital signal.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

One example discloses a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.

The present disclosure relates to a level shifter test circuit, a method of testing a level shifter test circuit, and a semiconductor chip. The circuit comprises a first level shifter for translating a signal from a first domain to a second domain. The first level shifter configured to receive the signal as an input from the first domain; and output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal. The circuit further comprises test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

A first circuit receives a single-ended signal and a reference voltage. The first circuit shifts a common mode of the single-ended signal based on a level-shifting current. A preamplifier receives the single-ended signal and the reference voltage from the first circuit and amplifies the single-ended signal to obtain an amplified signal. A decision feedback equalizer (DFE) system receives the amplified signal and the reference voltage from the preamplifier. The DFE system generates a first average signal height of the amplified signal above the reference voltage and a second average signal height of the amplified signal below the reference voltage. A second circuit provides the level-shifting current to the first circuit and adjusts the level-shifting current based on a linearity parameter associated with the amplified signal.

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

The invention provides a buffer circuit. The buffer circuit comprises a level shift module and a first operational amplifier, the first input end of the first operational amplifier receives an input signal; in the first stage of each sampling period, the level shift module is pre-charged with preset voltage; in the second stage of each sampling period, the input end of the level displacement module is connected with the output end of the first operational amplifier, the output end of the level displacement module is connected with the second input end of the first operational amplifier, and the level displacement module is used for translating the level of a first output signal of the first operational amplifier through a preset voltage; and obtaining a second output signal. By establishing the preset voltage in the level shift module in the first stage, the buffer circuit is closer to the working interval of the second output signal when entering the second stage, so that the establishment time of the second output signal is shortened, the transient response performance of the second output signal is improved, and the precision of the buffer circuit is improved.

Certain aspects of the present disclosure generally relate to power supply circuits and techniques for load voltage drop compensation. An example power supply circuit generally includes: a power stage coupled between the power stage and an output node of the power supply circuit; a feedback circuit coupled to the output node of the power supply circuit and including a feedback node; a level-shifter circuit including an input coupled to the feedback node; and a first current source coupled between the level-shifter circuit and a node of the feedback circuit.

The invention relates to the technical field of integrated circuits and provides an impedance adjusting method based on hybrid control and a resistance network. The method comprises: connecting a target resistor between a ground terminal and the second terminal such that the target resistor and the resistor network are connected in series between the first terminal and the ground terminal; closing all binary code switches of the binary code resistor array, and then gradually changing the thermometer code control code according to a first preset step length; maintaining the first thermometer code control code, and then gradually changing the binary code control code according to a second preset step length; and determining a hybrid control code of the resistance network corresponding to the resistance value of the target resistor. Therefore, not only is the problem of an intermediate transition state effectively solved, but also the complexity caused by excessive bit control bits is reduced as much as possible under the condition that the same precision is realized.

A power control circuit comprising a power supply and a load, the load being synthesized by an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped into impedance modules. The impedance elements in each impedance module have equal values, while the impedance elements between modules have a ratio uniquely defined by the number of impedance elements in the impedance module. A plurality of switches associated with the impedance elements short-circuit a selected number of impedance elements under control of a first analog signal, which can be pre-processed by an analytic function. The analog signal is converted to a digital signal by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, so that the amount of power delivered to the load can be controlled by the first analog signal. Pulse width modulation is deployed to further control the power by a second analog signal, with the additional benefit of overload protection.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

The invention discloses a wetting current circuit and an interface circuit, relates to the field of integrated circuit design, and solves the problems that an interface chip cannot normally output wetting current under a specific working condition, and even the interface chip is damaged. The wetting current circuit comprises: a current port for outputting a wetting current; a first end of the first current source module is connected with a first control signal, a second end is grounded, a third end is connected with the current port, and the first current source module is used for outputting pull current according to the first control signal; one end of the first anti-reverse module is connected to the chip power supply, the other end is connected with the first current source module, and the first anti-reverse module is used for isolating a forward path from the current port to the chip power supply; one end of the second current source module is connected to a second control signal, and the other end is grounded for outputting sink current according to the second control signal; and one end of the second anti-reverse module is connected with the second current source module, the other end of the second anti-reverse module is connected with the current port and the first current source module, and the second anti-reverse module is used for isolating a forward path from the chip ground to the current port.

The embodiment of the application discloses a kind of digital isolator and digital signal transmission method, the technical scheme of the embodiment of the application is by encoding circuit the rising edge and the falling edge of input digital signal are encoded into first pulse sequence and second pulse sequence respectively, by including multiple first pulse groups with time interval being first length characterizing first pulse sequence, multiple second pulse groups with time interval being second length characterizing second pulse sequence, so that more information is added in encoding signal, and the corresponding encoding information of rising edge and falling edge is transmitted through isolating element, while realizing the encoding and transmission of input digital signal, the anti-interference ability of encoding information and the anti-interference performance of digital isolator are improved.

The embodiment of the invention relates to a scalable arbiter for non-persistent signals. Systems and devices for signal arbitration are described. The plurality of asynchronous circuits may receive a plurality of non-persistent signals representing the plurality of requests and scrub the plurality of non-persistent signals to generate a plurality of persistent signals. The at least one logic circuit may arbitrate a plurality of persistent signals, wherein each logic circuit in the at least one logic circuit may include a mutual exclusion circuit configured to arbitrate two signals. Each logic circuit is one of a first logic circuit, a second logic circuit, and a third logic circuit that are different from each other. The plurality of copies of the first logic circuit may be implemented at an initial arbitration level, and the plurality of copies of the second and third logic circuits may be implemented at an additional arbitration level.

To provide devices, systems, and methods for routing communication from a host device to a plurality of devices by dynamic switching between an analog switch mode and a redriver mode.SOLUTION: In a system 100, a controller 106 of a device 104 can detect a communication initiated from a host device 102 to a target device between a device 110 and a device 120. The controller can identify the device 110 as a target device. The controller can, in response to identifying the device as the target device, activate a direct communication path between the host device 102 and the device 110 to allow the host device 102 to communicate with the device 110 using a direct communication mode. The controller can activate a redriver path between the host device 102 and a device 120 to allow the host device 102 to communicate with the device 120 using a redriver mode.SELECTED DRAWING: Figure 1

This description relates to a method of supplying an output potential level from among two first levels as a function of an input level from among two second levels, comprising: supplying the output level by a first node (210) connecting together first (201) and second (202) transistors electrically in series between two second nodes (VGH, VGL) of application of the first levels; supplying, by a first voltage generator (230) supplied by one of the second nodes (VGH), a first DC voltage (V1) defining an upper limit of the control voltage of the first transistor; and supplying, by a second voltage generator (240) controlled by a value representative of the first voltage and supplied between the second nodes, a second DC voltage (V2) defining an upper limit of the control voltage of the second transistor.

The invention discloses a temperature isolation sampling circuit, and relates to the field of electronic circuit design, and the circuit comprises a triangular wave circuit which generates a triangular wave with a fixed period according to a threshold value comparison result in a capacitor charging and discharging mode; the temperature sampling circuit is used for comparing the sampling voltage which is output by the thermistor voltage division circuit and changes along with the temperature with the triangular wave and outputting a PWM (Pulse Width Modulation) square wave signal of which the duty ratio changes along with the temperature; and configuring an optocoupler device to work in a switching state based on a non-linear region, and transmitting the PWM square wave signal to an isolation output circuit at a low-voltage side to realize electrical isolation transmission. The device supports electrical isolation and adapts to high-voltage occasions, and the isolation voltage range depends on selected isolation elements; according to the invention, the PWM is used for transmitting the temperature signal, when the temperature signal is interfered by an electromagnetic environment, the influence on the level amplitude does not change the duty ratio, and in addition, the cost of the device is also reduced.

The present technology relates to a data processing device and a data processing method capable of outputting appropriate multi-level signals at desired multiple levels in data transmission based on multi-level signals with a simple configuration. A first to M-th drivers to which control signals are input and that output voltages corresponding to the control signals are provided for a transmission line through which a multi-level signal representing transmission data with voltage levels as many as the number of states N is transmitted, in which an integer larger than or equal to 3 and different from a power of 2 is set as the number of states N and a power of a smallest integer that is a power of 2 larger than or equal to N is set as a control value M. The first to M-th drivers include first to M-th output resistors, respectively, and in a case where any integer larger than or equal to 1 and smaller than or equal to M is denoted by m, a resistance value of an m-th output resistor in which m is smaller than or equal to M−1 is a value obtained by dividing a predetermined resistance value by 2 raised to a power of (m−1), and a resistance value of an M-th output resistor in which m is M is a value obtained by dividing the predetermined resistance value by a value obtained by subtracting 2 raised to a power of (M−1) from N.

The application discloses an interface circuit of a MEMS gas sensor and a control method thereof, and belongs to the technical field of sensing circuit design. The interface circuit comprises a reference voltage current generating module, a gear switching module, a resistance conversion voltage module, a bias current generating module and a post-processing module. The resistance conversion voltage module is used to convert the equivalent resistance corresponding to the MEMS gas sensor into a voltage. The gear switching module is used to change the voltage amplification coefficient and the current mirror ratio by switching the state, so as to realize the voltage gear detection. Therefore, a wider resistance detection range can be realized under the same power consumption. Meanwhile, the voltage is converted into a period. In the case that the PVT is the same, the error term can be eliminated by subtracting the periods of T1 and T2. Finally, the period T corresponding to the equivalent resistance of the MEMS gas sensor is obtained, so that the detection precision of the equivalent resistance corresponding to the MEMS gas sensor is improved.

Systems, devices, and methods are provided for an improved voltage buffer. Improved voltage buffers may include an output circuit operating in a first voltage domain, and an input circuit operating in a second voltage domain and receiving a reference voltage and feedback signal. The second voltage domain may have a lower voltage than the first voltage domain. A bias circuit coupled between the input and output circuits may bias operation of the output circuit. An error signal from the input circuit may adjust the bias of the output circuit. A level shifting circuit may translate the adjusted bias signal from the second to the first voltage domain. The bias circuit may be controlled according to transistors having opposite VGS temperature curves. Advantageously, a reduced portion of the voltage buffer may be exposed to over-voltage stress, and the voltage buffer may be more resistant to temperature-based fluctuations in output voltage.

The invention provides a special amplitude limiting circuit for a PLC (Programmable Logic Controller), relates to the technical field of power line carrier communication, and aims to solve the technical problems that an AGC (Automatic Gain Control) circuit in an existing PLC communication system is limited in adjusting range, signal identification fails and the circuit burning risk is high. The system comprises a micro-control unit MCU, a current-limiting resistor, an optocoupler, a PLC signal coupling circuit and a PLC chip, and compared with a conventional PLC communication PLC chip signal path and process, a PLC amplitude limiting circuit is additionally arranged in front of the receiving ends RX + and RX-of the PLC chip; through the function that receiving ends RX + and RX-of a PLC chip identify the signal to noise ratio, the PLC chip communicates with a micro-control unit MCU through serial ports TX and RX, and through two modes of controlling and accessing different resistance values of series resistors to limit current and controlling and accessing different resistance values of divider resistors, the amplitude of a PLC signal is limited, so that the size of the PLC signal is changed, and the signal to noise ratio of the PLC signal is adjusted.

The invention discloses a level conversion circuit, the voltage of a first voltage end of the level conversion circuit is greater than that of a second voltage end, a first current branch comprises a first switching tube, a second current branch comprises a second switching tube, the width-to-length ratio of the first switching tube is greater than that of the second switching tube, the input end is connected with the first switching tube, and the output end is connected with the second switching tube. The voltage of the input end is used for controlling the on-off of the first switching tube and controlling the conduction voltage of the first switching tube to be the same as the conduction voltage of the second switching tube, so that the size relation of the first current branch and the second current branch is reversed; the current mirror circuit is used for mirroring the current of the first current branch and the current of the second current branch between the first voltage end and the voltage output end and between the voltage output end and the second voltage end respectively. Therefore, the voltage of the voltage output end can be controlled by controlling the voltage of the input end, the implementation mode is simple and rapid, and the energy consumption is low.

A level conversion circuit, a voltage measurement device and a voltage measurement method. The level conversion circuit comprises a current mirror circuit unit, an output circuit unit, a voltage dividing circuit unit, an output terminal and an input terminal, the input terminal is used for receiving an input voltage, the output terminal is used for providing an output voltage, the current mirror circuit unit comprises a first terminal connected with a first power supply voltage, a second terminal connected with the output terminal and a third terminal connected with the voltage dividing circuit unit, the current mirror circuit unit is configured to provide a mirror current at the second terminal and the third terminal, the output circuit unit is connected between a second power supply voltage and the output terminal and receives the input voltage from the input terminal, the output circuit unit is configured to provide the output voltage at the output terminal under the control of the input voltage and based on the control of the second power supply voltage, and the voltage dividing circuit is connected between the second power supply voltage and the third terminal of the current mirror circuit unit. The method can improve the precision of level conversion.

The invention relates to an anti-fuse nonvolatile memory and a driving circuit thereof. The anti-fuse nonvolatile memory comprises a memory cell array, a driving circuit, a first power supply and a second power supply. The memory cell array includes a first sub-array and a second sub-array. All memory cells of the first sub-array are connected to the first anti-fuse control line and the first following control line. All memory cells of the second sub-array are connected to the second anti-fuse control line and the second following control line. A first voltage provided by the first power supply is output to the first anti-fuse control line and the second anti-fuse control line through the first anti-fuse control line driver and the second anti-fuse control line driver of the driving circuit. A second voltage provided by the second power supply is directly output to the first following control line and the second following control line.

The main control device comprises a processing module with a switching pin and a plurality of signal pins, a first DIP switch, a second DIP switch, an inverting module, and a first switch and a second switch. The first DIP switch and second DIP switch are respectively connected to the signal pins through first and second signal switches. One end of the inverting module is connected to the processing module. The first switch connects to the first signal switches, the switching pin, the inverting module, and the operating voltage source. The second switch is connected to the second signal switches, the inverting module, and the operating voltage source.

A non-blocking crossbar switch architecture is disclosed that avoids a problem present in prior art crossbar switches where input signals may oversubscribe the available inter-die bandwidth. The novel non-blocking crossbar switch architecture is partitioned across multiple semiconductor dies containing multiple interleaved crossbar switch segments. Only one crossbar switch segment is implemented on each semiconductor die. Multiple input ports and multiple output ports are coupled to the crossbar switch. The crossbar switch is non-blocking; that is, any one output port that is not currently receiving data can receive data from any one input port.

The application provides a quantum bit interface circuit and a quantum bit computing system. The quantum bit interface circuit comprises a controller, a bit state control circuit and a bit state readout circuit. The controller is configured to generate a state control parameter and a state readout parameter according to a control instruction. The bit state control circuit is configured to output a state control signal to a quantum bit device according to the state control parameter, and the state control signal is configured to set a first state of a plurality of quantum bits. The bit state readout circuit is configured to output an excitation signal to the quantum bit device according to the state readout parameter, and receive a reflection signal of the plurality of quantum bits. The bit state readout circuit is further configured to determine a second state of the plurality of quantum bits according to the excitation signal and the reflection signal. The application communicates with a quantum computing device through the controller, obtains a control instruction, and controls the bit state control circuit and the bit state readout circuit to work according to the control instruction, so as to realize state control and state readout of the quantum bit.

A multi-branch analog multiplexer includes protection circuitry to help dissipate positive and negative injection currents without increasing the size of hardening transistors in each branch, thereby avoiding an increase in leakage current and enabling an analog-to-digital converter to operate with the required precision. The protection circuitry is attached to the bases of the hardening transistors to lower the threshold voltage of the hardening devices, thereby enabling the hardening devices to handle more injection current.