817results about "Logic circuit interface arrangements" patented technology

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

The invention provides an anti-common-mode transient interference circuit, a receiving circuit and a digital isolator, and the anti-common-mode transient interference circuit comprises a demodulation module which is electrically connected with an isolation capacitor of a receiving end, and demodulates a received carrier signal, so as to output an intermediate digital signal; and the filtering module is electrically connected with the demodulation module and is used for removing noise caused by the common-mode transient event in the intermediate digital signal so as to output a target digital signal. According to the invention, the filtering module is additionally arranged to remove the noise caused by the common-mode transient event and carried in the intermediate digital signal, so as to obtain the clean target digital signal, reduce the influence of the common-mode transient event on other links in the circuit system, and facilitate the subsequent function module in the circuit system to process the target digital signal.

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

Disclosed in the present application are a level shift circuit, a driving circuit and a half-bridge circuit. The level shift circuit comprises: a first voltage-current conversion circuit, which is used for generating a set current signal on the basis of an input signal; a second voltage-current conversion circuit, which is used for generating a reset current signal on the basis of an inverted signal of the input signal; and a latch misoperation protection circuit, which is used for generating a set driving signal and a reset driving signal in a second voltage domain on the basis of the set current signal and the reset current signal, and providing the set driving signal and the reset driving signal to a latch circuit, wherein the latch misoperation protection circuit is further used for pulling up the set driving signal and the reset driving signal when common-mode noise has occurred, and quickly pulling down one of a set end and a reset end of the latch circuit on the basis of the state of an output signal, such that the output of the latch circuit remains in an original state, and thus noise and interference in the circuit can be suppressed when the common-mode noise has occurred, thereby avoiding false triggering of the latch circuit and improving the performance and reliability of the circuit.

A low voltage differential signaling receiver includes a resistor load pair, an input stage, a current mode logic stage and a comparator circuit. The input stage includes a P-type transistor pair and a N-type transistor pair. The P-type transistor pair and the N-type transistor pair are configured to generate first differential output voltages on the resistor load pair according to differential input signals. The current mode logic stage is configured to enhance a gain of the first differential output voltages into second differential output voltages. The latch circuit is configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages. The comparator circuit is configured to compare the third differential output voltages and generate a single-ended output signal.

A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

A level conversion assembly (50), an overcurrent protection method and a display device, the level conversion assembly (50) comprising a level conversion module (51), the level conversion module (51) comprising a control unit (511), a current detection unit (512), a level conversion unit (513) and an overcurrent protection unit (514). When a control unit (511) is at a first falling edge of a digital clock signal (CPV), a first analog clock signal corresponding to the first falling edge in a plurality of analog clock signals (CLK1-CLK8) is determined based on the corresponding relation of the current display mode, and a current detection unit (512) is controlled to detect the current of the first analog clock signal. Since the moment of the falling edge of the digital clock signal (CPV) is located in the last row of the high level period or the low level period in the corresponding analog clock signal, the current detection unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not located in the current threshold range. The effect of improving the accuracy of over-current phenomenon detection is achieved.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention relates to the technical field of motor driving, and discloses a universal integrated motor driving device, which comprises an optocoupler isolation module, an integrated logic module, a power MOS (Metal Oxide Semiconductor) tube driving module, a power module and a current-limiting protection module, the optical coupler isolation module is connected with the integrated logic module; the integrated logic module is connected with the power MOS tube driving module; the power MOS tube driving module is connected with the power module; the power module is connected with a load motor; and the current-limiting protection module is connected with the power module. According to the invention, the optical coupler isolation module, the logic processing module, the MOS tube driving module and the current-limiting protection module are modularly integrated, so that the circuit design is simplified, and the reliability and maintainability of the system are improved.

An isolated gate driver has: a register that stores the adjustment data read from a non-volatile memory; a gate driving circuit that drives the gate of a switching element with a characteristic set based on a value stored in the register; a fault detector that performs fault detection for other than the non-volatile memory; an error detection-correction circuit that performs error detection and error correction on the adjustment data written to the non-volatile memory; a first external terminal for output of the result of fault detection; a second external terminal for output of the result of error detection; and a fault controller that, if a one-bit error is detected in the adjustment data, brings the second external terminal into an error-indicating output state and continues with normal operation of the gate driving circuit and, if a two-or-more-bit error is detected in the adjustment data, forcibly stops the gate driving circuit.

According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

Embodiments of the disclosure provide a level shift circuit, a chip and a display device. By setting first and second voltage clamping modules, and by adjusting first clamping voltage by controlling bias voltage input to the first voltage clamping module and adjusting second clamping voltage by controlling bias voltage and second bias voltage input to the second voltage clamping module, respective operating and output voltages of the first and the second voltage clamping modules and the shift module are within small range. Therefore, even the level shift circuit is designed by using devices with breakdown voltage lower than the difference between the first and second power supply voltages, the devices in the level shift circuit may be avoid being breakdown. Accordingly, some process platforms that cannot produce high-breakdown voltage devices may produce chips including the level shift circuit in the embodiment, and the restrictions on the process platform are reduced.

Methods and apparatuses are provided in which a level shifter of a digital control circuit for a switchable voltage supply circuit shifts a domain level of a first input. A first inverter of the digital control circuit inverts output of the first level shifter to output a first gain voltage to turn on a first switch of the switchable voltage supply circuit or output a second gain voltage to turn off the first switch. A second inverter of the digital control circuit inverts a second input to output a third gain voltage to turn on a second switch of the switchable voltage supply circuit or output a fourth gain voltage to turn off the second switch. The first gain voltage is greater than the third gain voltage.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

A memory system includes a semiconductor memory device; and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a first pin configured to receive a first signal and a second signal sent from the memory controller, the second signal having a smaller amplitude than the first signal. A first receiving circuit is connected to the first pin and is configured to output a third signal and a fourth signal having a smaller amplitude than the third signal. The first receiving circuit outputs the third signal based on a comparison between the first signal and a first voltage, and outputs the fourth signal based on a comparison between the second signal and a second voltage. A first terminating circuit is connected to the first pin and is configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal.

An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

One example discloses a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

A level shifter includes an input circuit configured to invert an input voltage to output a first inverted voltage and a second inverted voltage, wherein the input voltage swings between a first ground voltage and a first power supply voltage, a protection circuit including at least one pair of transistors sharing a gate terminal to adjust, based on the first inverted voltage and the second inverted voltage, one of a first intermediate voltage and a second intermediate voltage of the protection circuit. a cross-coupling circuit configured to adjust the other of the first intermediate voltage and the second intermediate voltage, and an output circuit configured to invert the first intermediate voltage to output an output voltage that swings between a second ground voltage and a second power supply voltage.

Circuits, devices, and systems incorporating a low-voltage common-mode transient immunity (CMTI) test. The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common-mode transient rejection, the first signal path should be the same as the second signal path. Differences in resistance, inductance, and capacitance between the two signal paths may result in common-mode noise being measured at the output terminals as a differential signal. Devices according to the techniques of this disclosure are configured to include a test mode to perform a low-voltage test that outputs a measurement of the CMTI at any stage of production or field deployment.

Disclosed structures include a single-stage and a multi-stage voltage level shifter. Each structure includes multiple transistors, which are optionally all symmetric low-voltage transistors, and the structures are configured to avoid operation outside the safe operating area (SOA) of such transistors. The single-stage voltage level shifter and the first stage of the multi-stage voltage level shifter can be essentially identical. In operation, input voltage pulses (including an input voltage pulse transitioning between a first positive voltage (V1) equal to the voltage rating of the transistors and ground) can be received at source nodes of N-type transistors and, in response, output voltage pulses (including an intermediate output voltage pulse transitioning between V1 and a second positive voltage (V2) that is higher than (e.g., double) V1 and an output voltage pulse that transitions between ground and V2) can be output.

The invention discloses a motor signal feedback control method, which comprises a step of physically connecting an optical coupler U1 between a motor and a main control board, and comprises the following steps of: setting N function relational expressions established by different motor state feedback signals and PWM frequency f in the main control board, and defining a PWM frequency range for each function relational expression, meanwhile, a sending period of the motor is set; the motor circularly outputs PWM frequency signals corresponding to the motor state feedback signals to the main control board according to the sending period time sequence; and the main control board judges the type of the motor state feedback signal according to the frequency range of the received PWM frequency signal, calculates the actual value of each motor state feedback signal according to the corresponding function relation, and adjusts the target quantity of the motor according to the actual value of each motor state feedback signal. The function that the motor can send a plurality of motor state signal feedbacks to the main control board only through one optical coupler signal is achieved, and the main control board accurately adjusts the target value of the motor according to the plurality of motor state feedback signals.

The present application provides an interlock device, an energy storage system, a control method, and a control apparatus. The interlock device comprises: a first interlock circuit, a first drive processing circuit, a first drive status feedback circuit, a second interlock circuit, a second drive processing circuit, and a second drive status feedback circuit. The first interlock circuit, the first drive processing circuit, and the first drive status feedback circuit are connected, and the second interlock circuit, the second drive processing circuit, and the second drive status feedback circuit are connected. The first interlock circuit receives an output of the second drive status feedback circuit, and the second interlock circuit receives an output of the first drive status feedback circuit, thereby forming an interlock circuit.

The invention relates to the technical field of switch control, and provides a switch channel switching method and system, terminal equipment and a storage medium. According to the switch channel switching method, a control board, at least one function board and at least two radio frequency switch groups are included, a control output port of the control board is connected with a control input port of the function board, and an output interface of the function board is connected with a control pin of the radio frequency switch group. Comprising the following steps: receiving channel switching control information through a control panel; processing the channel switching control information through the control board to obtain a control signal, and transmitting the control signal to the radio frequency switch group after the control signal is subjected to preset processing through the function board; according to the technical scheme of the invention, the radio frequency switch group completes the switching of the switch channels according to the control signal which is preset by the function board, so that the equipment control difficulty can be effectively reduced, and the equipment stability can be improved.

The invention discloses a low-delay small-area level shift circuit, which comprises a pulse generation module, an NMOS (N-channel Metal Oxide Semiconductor) tube HMN1, an NMOS tube HMN2 and a level shift module, and is characterized in that the pulse generation module is used for carrying out signal delay on an original signal to generate a first pulse signal and a second pulse signal; the grid electrode of the NMOS transistor HMN1 receives a first pulse signal, the source electrode is connected with the grounding end, and the drain electrode is connected with the first input end of the level shift module; the grid electrode of the NMOS tube HMN2 receives a second pulse signal, the source electrode is connected with the grounding end, and the drain electrode is connected with the second input end of the level shift module; the first pulse signal is used for controlling the on-off of the NMOS tube HMN1, and the second pulse signal is used for controlling the on-off of the NMOS tube HMN2, so that the level shift of the original signal is realized. According to the invention, the pulse generation module generates the pulse signal to control the opening of the NMOS tube, so that the power loss of the circuit is effectively reduced.

A complementary metal oxide semiconductor (CMOS)-to-current mode logic (CML) converter for converting a CMOS input signal into a CML output signal, including: a low-pass filter comprising a fixed resistor and a first fixed capacitor, and a swing width control circuit configured to adjust a swing width of a voltage swing of the CML output signal based on a common mode level, wherein the swing width control circuit includes: a second fixed capacitor; and a variable capacitor comprising a capacitor array.

A level conversion assembly (50), an overcurrent protection method, and a display device. The level conversion assembly (50) comprises a level conversion module (51); and the level conversion module (51) comprises a control unit (511), a current measurement unit (512), a level conversion unit (513), and an overcurrent protection unit (514). When at a first falling edge of a digital clock signal (CPV), the control unit (511) determines, on the basis of a correspondence of a current display mode, a first analog clock signal corresponding to the first falling edge among a plurality of analog clock signals (CLK1-CLK8), and controls the current measurement unit (512) to measure the current of the first analog clock signal; and the moment of a falling edge of the digital clock signal (CPV) is at the last row of a high-level period or low-level period in a corresponding analog clock signal, so that the current measurement unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not within a current threshold range, thereby achieving the effect of improving the accuracy of overcurrent detection.

The invention relates to a circuit and a method for realizing infrared receiving detection and key detection pin multiplexing, and relates to the field of chip application. An MCU is provided with a plurality of groups of pins, a first pin of an infrared receiving head is connected with a VCC, a second pin of the infrared receiving head and a second pin of the MCU are jointly connected to a GND, a first end of a key and a third pin of the infrared receiving head are jointly connected to the first pin of the MCU, a second end of the key is connected with a first end of a first resistor, and a second end of the first resistor is connected with the GND. Under the condition, through multiplexing of an infrared receiving pin and a key, when a pin receives an infrared signal, according to protocol requirements of different infrared signals, distinguishing the infrared signal from key triggering, and according to an NEC6122 protocol, through a mode of judging low level time and a key judgment program, judging whether key triggering is carried out or not; and the number of required packaging pins is reduced, so that the cost of the PCB is reduced.

The invention discloses a time sequence convergence system, method and device and a storage medium, and relates to the technical field of chips. A CP port of the convergence register is connected with a clock chip pin processing unit of the input and output module and is used for acquiring a clock signal input by the clock chip pin processing unit; a D port of the convergence register is connected with a Q port of a data register in the high-speed peripheral interface and is used for receiving a data signal sent by the data register; and a Q port of the convergence register is connected with a data chip pin processing unit in the input / output module and is used for sending the data signal to the data chip pin processing unit. According to the technical scheme provided by the embodiment of the invention, the time sequence convergence time of the chip is reduced, the clock signal delay is reduced, and the stability of data transmission of the chip is improved; and meanwhile, the high-speed peripheral interface is not limited by layout placement positions, so that the convenience of chip layout and wiring is improved, and the complexity of chip design is reduced.