581results about "Logic circuit interface arrangements" patented technology

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

The invention provides an anti-common-mode transient interference circuit, a receiving circuit and a digital isolator, and the anti-common-mode transient interference circuit comprises a demodulation module which is electrically connected with an isolation capacitor of a receiving end, and demodulates a received carrier signal, so as to output an intermediate digital signal; and the filtering module is electrically connected with the demodulation module and is used for removing noise caused by the common-mode transient event in the intermediate digital signal so as to output a target digital signal. According to the invention, the filtering module is additionally arranged to remove the noise caused by the common-mode transient event and carried in the intermediate digital signal, so as to obtain the clean target digital signal, reduce the influence of the common-mode transient event on other links in the circuit system, and facilitate the subsequent function module in the circuit system to process the target digital signal.

The invention provides a clock input buffer and electronic equipment. The clock input buffer comprises a multi-protocol input circuit, a level conversion circuit, a step-down circuit and a clock buffer circuit. The multi-protocol input circuit is adjusted to different working modes through a control signal transmitted by the control unit so as to be compatible with various input protocols, the multi-protocol input circuit processes an input signal based on a target working mode, and the level conversion circuit performs level shifting on an output signal of the multi-protocol input circuit so as to realize multi-protocol conversion. The voltage reduction circuit is used for converting the output signal into a low-voltage domain signal so as to meet the working voltage requirement of the clock buffer circuit, and meanwhile, the voltage reduction circuit is used for reducing the power supply voltage so as to provide low-voltage power supply voltage for the clock buffer circuit; therefore, the clock buffer circuit can buffer high-speed signals in different input protocols and voltage ranges by using a low-voltage domain device, and the application scenarios of the clock input buffer are greatly expanded.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

A level conversion assembly (50), an overcurrent protection method and a display device, the level conversion assembly (50) comprising a level conversion module (51), the level conversion module (51) comprising a control unit (511), a current detection unit (512), a level conversion unit (513) and an overcurrent protection unit (514). When a control unit (511) is at a first falling edge of a digital clock signal (CPV), a first analog clock signal corresponding to the first falling edge in a plurality of analog clock signals (CLK1-CLK8) is determined based on the corresponding relation of the current display mode, and a current detection unit (512) is controlled to detect the current of the first analog clock signal. Since the moment of the falling edge of the digital clock signal (CPV) is located in the last row of the high level period or the low level period in the corresponding analog clock signal, the current detection unit (512) can send an overcurrent signal to the overcurrent protection unit (514) when the current of the first analog clock signal is not located in the current threshold range. The effect of improving the accuracy of over-current phenomenon detection is achieved.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

A memory system includes a semiconductor memory device; and a memory controller configured to control the semiconductor memory device. The semiconductor memory device includes a first pin configured to receive a first signal and a second signal sent from the memory controller, the second signal having a smaller amplitude than the first signal. A first receiving circuit is connected to the first pin and is configured to output a third signal and a fourth signal having a smaller amplitude than the third signal. The first receiving circuit outputs the third signal based on a comparison between the first signal and a first voltage, and outputs the fourth signal based on a comparison between the second signal and a second voltage. A first terminating circuit is connected to the first pin and is configured to be disabled if the first pin receives the first signal and enabled if the first pin receives the second signal.

One example discloses a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

A level shifter includes an input circuit configured to invert an input voltage to output a first inverted voltage and a second inverted voltage, wherein the input voltage swings between a first ground voltage and a first power supply voltage, a protection circuit including at least one pair of transistors sharing a gate terminal to adjust, based on the first inverted voltage and the second inverted voltage, one of a first intermediate voltage and a second intermediate voltage of the protection circuit. a cross-coupling circuit configured to adjust the other of the first intermediate voltage and the second intermediate voltage, and an output circuit configured to invert the first intermediate voltage to output an output voltage that swings between a second ground voltage and a second power supply voltage.

Circuits, devices, and systems incorporating a low-voltage common-mode transient immunity (CMTI) test. The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common-mode transient rejection, the first signal path should be the same as the second signal path. Differences in resistance, inductance, and capacitance between the two signal paths may result in common-mode noise being measured at the output terminals as a differential signal. Devices according to the techniques of this disclosure are configured to include a test mode to perform a low-voltage test that outputs a measurement of the CMTI at any stage of production or field deployment.

The invention relates to the technical field of switch control, and provides a switch channel switching method and system, terminal equipment and a storage medium. According to the switch channel switching method, a control board, at least one function board and at least two radio frequency switch groups are included, a control output port of the control board is connected with a control input port of the function board, and an output interface of the function board is connected with a control pin of the radio frequency switch group. Comprising the following steps: receiving channel switching control information through a control panel; processing the channel switching control information through the control board to obtain a control signal, and transmitting the control signal to the radio frequency switch group after the control signal is subjected to preset processing through the function board; according to the technical scheme of the invention, the radio frequency switch group completes the switching of the switch channels according to the control signal which is preset by the function board, so that the equipment control difficulty can be effectively reduced, and the equipment stability can be improved.

The invention discloses a low-delay small-area level shift circuit, which comprises a pulse generation module, an NMOS (N-channel Metal Oxide Semiconductor) tube HMN1, an NMOS tube HMN2 and a level shift module, and is characterized in that the pulse generation module is used for carrying out signal delay on an original signal to generate a first pulse signal and a second pulse signal; the grid electrode of the NMOS transistor HMN1 receives a first pulse signal, the source electrode is connected with the grounding end, and the drain electrode is connected with the first input end of the level shift module; the grid electrode of the NMOS tube HMN2 receives a second pulse signal, the source electrode is connected with the grounding end, and the drain electrode is connected with the second input end of the level shift module; the first pulse signal is used for controlling the on-off of the NMOS tube HMN1, and the second pulse signal is used for controlling the on-off of the NMOS tube HMN2, so that the level shift of the original signal is realized. According to the invention, the pulse generation module generates the pulse signal to control the opening of the NMOS tube, so that the power loss of the circuit is effectively reduced.

The present disclosure relates to a level shifter test circuit, a method of testing a level shifter test circuit, and a semiconductor chip. The circuit comprises a first level shifter for translating a signal from a first domain to a second domain. The first level shifter configured to receive the signal as an input from the first domain; and output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal. The circuit further comprises test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.

A receiver circuit is configured to generate, based on a clock signal, a first output signal by differentially amplifying an input signal and a reference voltage and to generate, based on a complementary clock signal, a second output signal by differentially amplifying the input signal and the reference voltage. The receiver circuit is configured to generate a first delay output signal and a second delay output signal by delaying the first output signal and the second output signal. The receiver circuit is configured to variably delay the first output signal based on the first output signal and the reference voltage and to variably delay the second output signal based on the second output signal and the reference voltage.

The invention belongs to the technical field of electronic circuits, and provides a level safe conversion and controllable output device, which comprises a conversion circuit I, a conversion circuit II, a logic circuit A, a logic circuit B, an acquisition monitoring circuit A and an acquisition monitoring circuit B, the logic circuit A and the logic circuit B are mutually connected; the logic circuit A is connected with the conversion circuit I; the logic circuit B is connected with the conversion circuit I and the conversion circuit II; the first conversion circuit is connected with an external power supply and is connected with the second conversion circuit, and the second conversion circuit is connected with a using device and is used for converting a level provided by the external power supply into an adaptive level of the using device and outputting the adaptive level; and the acquisition monitoring circuit A and the acquisition monitoring circuit B are connected with the conversion circuit II to acquire adaptive level data and transmit the adaptive level data to the logic circuit A and the logic circuit B. According to the invention, an isolation architecture design, a hardware heterogeneous acquisition mode and dual AND logic are adopted, so that the safety and reliability of the device in the level conversion and output process are improved.

The invention belongs to the field of electronic circuits, and provides a level conversion circuit, a switching power supply chip and electronic equipment. The circuit comprises a voltage output module, a logic module and a comparison module. First ends of the voltage output module and the logic module receive output voltage. The second end of the voltage output module is connected with the second end of the logic module and the first end of the comparison module. The second end of the comparison module receives reference voltage, and the third end is connected with the third end of the logic module; the fourth end of the logic module outputs target voltage, and the fifth end and the third end of the voltage output module are both grounded. In the starting process of the boost switching power supply chip, when the output voltage is smaller than a preset value, the voltage output module outputs a first voltage. The comparison module outputs a first comparison signal according to the first voltage and a reference voltage. The logic module enables the fourth end and the fifth end of the logic module to be conducted according to the first comparison signal, the target voltage is made to be 0V, then the voltage margin is the output voltage, and compared with an existing circuit, the voltage margin is increased.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

A transmission and reception system includes a transmission circuit and a reception circuit. The transmission circuit is configured to generate a transmission signal based on an input signal. The reception circuit is configured to generate an output signal based on the transmission signal. The transmission circuit is configured to provide a duty cycle offset which is complementary with a duty cycle offset of the reception circuit.

Disclosed are a level conversion circuit and a DC / DC converter, the level conversion circuit comprising: a current bias module configured to output a bias current; the control module is configured to output a control current based on the bias current under the control of an input signal in a low voltage domain; and the level conversion module is configured to output an output signal located in the high voltage domain based on the control current, and the logic level of the output signal is the same as that of the input signal. According to the invention, rapid level conversion can be realized, and interference of a high-voltage domain power supply can be well resisted.

The invention discloses a digital-to-analog converter interface circuit supporting LVDS / CMOS dual-mode input. The digital-to-analog converter interface circuit comprises an ESD protection circuit, a DEMUX multiplexer, an MUX multiplexer, an LVDS receiver, an inverter chain and a digital logic circuit. The output end of the ESD protection circuit is connected with the DEMUX demultiplexer; the digital logic circuit is used for generating a synchronous control signal according to an external mode switching signal and coordinating the working state of each module; the DEMUX demultiplexer distributes an input signal output by the ESD protection circuit to a corresponding signal processing path under the action of a control signal output by the digital logic circuit; the LVDS receiver receives the LVDS signal, converts the LVDS signal into a single-ended CMOS signal, and outputs the single-ended CMOS signal to the MUX multiplexer; the inverter chain is used for receiving a CMOS signal; and the MUX multiplexer outputs a control signal according to the digital logic circuit, so that one of the two paths of input signals is selected to be output to the DAC core circuit. According to the invention, LVDS / CMOS dual-mode input is efficiently supported in a single chip, and meanwhile, the requirements of high speed, low power consumption and time sequence consistency are met.

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

A first circuit receives a single-ended signal and a reference voltage. The first circuit shifts a common mode of the single-ended signal based on a level-shifting current. A preamplifier receives the single-ended signal and the reference voltage from the first circuit and amplifies the single-ended signal to obtain an amplified signal. A decision feedback equalizer (DFE) system receives the amplified signal and the reference voltage from the preamplifier. The DFE system generates a first average signal height of the amplified signal above the reference voltage and a second average signal height of the amplified signal below the reference voltage. A second circuit provides the level-shifting current to the first circuit and adjusts the level-shifting current based on a linearity parameter associated with the amplified signal.

Equipping level converters: an input circuit (120) having a first input terminal (202) and a second input terminal (204) configured to receive complementary input signals at a first voltage level (VSSA) and a second voltage level (VDDA); a cross-latch circuit (110) coupled to the input circuit (120), wherein the cross-latch circuit (110) has a first output terminal (102) and a second output terminal (104) configured to provide complementary output signals at a third voltage level (VSSB) and a fourth voltage level (VDDB), wherein the input circuit (120) has a first control node (206) and a second control node (208) configured to output a first control signal and a second control signal at the first voltage level (VSSB) and the fourth voltage level (VDDB) based on the input signals; and a follow-up circuit (130) coupled to the input circuit (120) and the cross-latch circuit (110), configured to input a first tracking signal and a second tracking signal into the cross-latch circuit (110) based on the first control signal and the second control signal, wherein the first tracking signal is greater than the first control signal and the third voltage level (VSSB), and the second tracking signal is greater than the second control signal and the third voltage level (VSSB).

The invention provides a buffer circuit. The buffer circuit comprises a level shift module and a first operational amplifier, the first input end of the first operational amplifier receives an input signal; in the first stage of each sampling period, the level shift module is pre-charged with preset voltage; in the second stage of each sampling period, the input end of the level displacement module is connected with the output end of the first operational amplifier, the output end of the level displacement module is connected with the second input end of the first operational amplifier, and the level displacement module is used for translating the level of a first output signal of the first operational amplifier through a preset voltage; and obtaining a second output signal. By establishing the preset voltage in the level shift module in the first stage, the buffer circuit is closer to the working interval of the second output signal when entering the second stage, so that the establishment time of the second output signal is shortened, the transient response performance of the second output signal is improved, and the precision of the buffer circuit is improved.

Systems and methods are provided for a multiple power supply mode input / output (IO) circuit of an integrated circuit that includes a plurality of power rails, one or more supply mode power rails being associated with each supply mode of the integrated circuit, and a core power rail being associated with core circuitry of the integrated circuit. The IO circuit may further include a plurality of chip connection points, each chip connection point being connected to one or more of the power rails, the chip connection points being configured for connection to one or more package connection points.

The invention belongs to the technical field of photoelectric technologies and analog integrated circuits, and particularly relates to an optical sampling and electric quantization interface circuit applied to an optical sampling and electric quantization type ADC. According to the invention, the transmission signal type between optical sampling and electric quantization is converted from voltage to current, the input signal amplitude of the electric quantizer is improved, the level matching of optical sampling and electric quantization is realized, the signal-to-noise ratio of an optical sampling link is improved, the dynamic range of the whole analog-to-digital conversion is improved, and the analog-to-digital conversion efficiency is improved. The problems that an existing photoelectric interface scheme is high in signal loss and serious in interface mismatch are solved.

The present application relates to the field of switch control technology, and provides a switch channel switching method, system, terminal device and storage medium. The switch channel switching method provided by the present application includes a control board, at least one function board and at least two radio frequency switch groups, wherein the control output port of the control board is connected to the control input port of the function board, and the output interface of the function board is connected to the control pin of the radio frequency switch group, including: receiving channel switching control information through the control board; processing the channel switching control information through the control board to obtain a control signal, and transmitting the control signal to the radio frequency switch group after preset processing by the function board; completing the switching of the switch channel by the radio frequency switch group according to the control signal after preset processing by the function board, which can effectively reduce the difficulty of device control and improve device stability.