Digital trimming system based on pin multiplexing

Abstract

The invention discloses a digital trimming system based on pin multiplexing. The digital trimming system comprises a control circuit connected with a trimming input pulse signal. The output end of the control circuit is connected with a shift register circuit and a trimming circuit. The output end of the shift register circuit is connected with the input end of the trimming circuit. A trimming feedback circuit is connected between the output end of the trimming circuit and the input end of the control circuit. It is not required to specially use a pin of a chip as a trimming pin but to directly multiplex the function pin of the chip so that the number of the pins of the chip may decrease. The shift register circuit mainly converts the number of the pulses of the input trimming signal into a control signal to a specific bit required to be trimmed. The trimming circuit mainly receives the trimming signal of the specific bit of the shift register circuit, fuses the fuse of a corresponding bit, latches a trimming result, and outputs the trimming result to a module of which the chip is required to be trimmed. The digital trimming system may prevent erroneous trimming of the chip in a normal operating state after trimming finishes.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a trimming circuit in the field of integrated circuit design. Background technique [0002] As the requirements for integrated circuit performance indicators are getting higher and higher, integrated circuits are facing more and more high-precision requirements. Trimming technology is a necessary means to realize high-precision integrated circuits. The trimming technology in integrated circuit design is mainly for trimming the resistance network and the capacitor network. Through different trimming technologies, the resistance value and capacitance value can be increased or decreased. Trimming can be done at the wafer level during the mid-chip test, or after dicing and packaging at the chip test stage. Both methods have their own advantages and disadvantages. The former can select all unqualified products at the wafer level, but it is time-consuming and labor-intensive t...

AI Technical Summary

Problems solved by technology

This will increase the number of chip pins and cost, and may lead to false trigger trimming

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