210results about "Logic circuit coupling arrangements" patented technology

The invention provides a digital isolator with both high-speed communication and high common-mode transient immunity. The digital isolator comprises a transmitter, a coupling inductor and a receiver, the transmitter comprises an oscillator, a modulation capacitor assembly and a common-mode transient immunity enhancement module; the oscillator is configured to receive a data signal and generate a first differential signal based on the data signal; the modulation capacitor assembly is configured to modulate a code element 0 into a first frequency and modulate a code element 1 into a second frequency; the common-mode transient immunity enhancement module is configured to determine a bias control signal according to the first differential signal; the receiver is configured to receive the second differential signal and obtain a square wave signal based on the second differential signal; obtaining a triangular wave signal based on the square wave signal; obtaining the maximum value of a triangular wave signal according to the falling edge signal of the square wave signal; and obtaining a target data signal based on the maximum value, so as to solve the problem of low communication and common-mode transient immunity performance of the existing digital isolator.

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

The application provides an inhibitor circuit, a signal sending device and a communication system, and relates to the field of digital information transmission.The inhibitor circuit provided by the application comprises a first transistor and a second transistor, a first switch, a second switch and a first voltage generation module.When communication ends, the first switch and the second switch are closed, and the first transistor and the second transistor are turned on.When the signals on the first communication bus and the second communication bus reach a common mode state, the first switch and the second switch are turned off.The application further provides an inhibitor circuit which adds an additional path on the basis of the above inhibitor circuit.The application further provides a signal sending device which comprises the above inhibitor circuit.The application further provides a communication system which comprises the above signal sending device.The inhibitor circuit, the signal sending device and the communication system provided by the application can reduce the amplitude of tailing overshoot and ensure accurate decoding at the receiving end.

A reference clock signal generation system, comprising a first coupler, a selection switch control module, a selection switch, a crystal oscillator, a second coupler, a phase-locked loop module and an adjustable resistor; the input end of the crystal oscillator is connected with the output end of the selection switch, and the output end of the crystal oscillator is connected with the input end of the second coupler; the input end of the adjustable resistor is connected with the output end of the crystal oscillator, and the output end of the adjustable resistor is connected with the input end of the selection switch; the input end of the selection switch control module is connected with the output end of the first coupler, and the output end of the selection switch control module is connected with the input end of the selection switch; the input end of the phase-locked loop module is connected with the input end of the first coupler and the input end of the second coupler respectively; the output end of the phase-locked loop module is connected with the input end of the selection switch; the system can ensure that the output reference clock signal is phase coherent when the internal and external reference clock signals of different sources are switched, and can also adjust the frequency of the output signal of the internal crystal oscillator.

The invention relates to the technical field of integrated circuits and provides an impedance adjusting method based on hybrid control and a resistance network. The method comprises: connecting a target resistor between a ground terminal and the second terminal such that the target resistor and the resistor network are connected in series between the first terminal and the ground terminal; closing all binary code switches of the binary code resistor array, and then gradually changing the thermometer code control code according to a first preset step length; maintaining the first thermometer code control code, and then gradually changing the binary code control code according to a second preset step length; and determining a hybrid control code of the resistance network corresponding to the resistance value of the target resistor. Therefore, not only is the problem of an intermediate transition state effectively solved, but also the complexity caused by excessive bit control bits is reduced as much as possible under the condition that the same precision is realized.

According to some embodiments, a receiver comprises a positive terminal, a negative terminal, a first isolation capacitor connected to the positive terminal, a second isolation capacitor connected to the negative terminal, a resistor circuit connected to the first isolation capacitor and the second isolation capacitor to define a first high pass filter, an amplifier connected to the first high pass filter, a level detector connected to the amplifier, and a second high pass filter connected between the first high pass filter and the level detector.

Examples of an apparatus and method for power management are disclosed. In an example, a device includes a charge circuit, a discharge circuit, an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are couplable to a capacitor, and wherein the charge circuit includes an analog soft start circuit, and control logic configured to determine a discharge time of the capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit.

The application discloses a kind of sensing transducer and its voltage signal processing circuit, belong to the field of transducer, for using analog circuit to realize for sensor voltage signal segmented calibration, solved the problem that voltage signal is difficult to maintain higher signal accuracy under strong interference environment.Considering that the way of segmented calibration can improve the accuracy of sensor output voltage signal, and analog circuit has strong anti-interference ability, the segmented identification circuit of the application can deliver voltage signal to the segmented calibration circuit corresponding to the voltage value interval to which the voltage signal belongs, so that the segmented calibration circuit can multiply the received voltage signal by a predetermined slope and add a predetermined intercept, and output after signal conditioning circuit, so as to realize the segmented calibration of voltage signal, and each part of circuit is analog circuit, has strong anti-interference ability, so that voltage signal can maintain higher signal accuracy under strong interference environment, widen the application scenario of sensing transducer.

The application provides a kind of dual-channel low-frequency modulation intermediate frequency bipolar pulse signal generation system, it is related to integrated circuit technical field, including: power supply and signal isolation circuit, signal generation master module and signal generation slave module respectively connected with power supply and signal isolation circuit;The circuit structure in signal generation master module and signal generation slave module is identical;Signal generation master module includes the first step-down power supply circuit connected in turn, first MCU controller circuit, first intermediate frequency bipolar pulse signal generation circuit and first signal output interface, it also includes the first output current detection circuit and the first low-frequency current signal generation circuit connected with first MCU controller circuit, and first low-frequency current signal generation circuit is also connected with first intermediate frequency bipolar pulse signal generation circuit.The technical scheme of the application overcomes the problem that the medical device in the prior art cannot stimulate multiple acupoints simultaneously.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The application provides a non-immersed transmembrane pressure detection system, which is characterized in that: a liquid inlet detection module, a permeation end detection module, a backflow end detection module and a transmembrane pressure calculation module are arranged, a non-immersed transmembrane pressure detection circuit is arranged in each of the liquid inlet detection module, the permeation end detection module and the backflow end detection module, the corresponding transmembrane pressure calculation result is obtained by calculating the liquid inlet detection signal, the permeation end detection signal and the backflow end detection signal output by the circuit, a four-stage amplification and analog signal isolation circuit composed of a high-precision resistance voltage division network, a first-stage operational amplifier circuit, a second-stage operational amplifier circuit, a linear optical coupler, a third-stage operational amplifier circuit and a fourth-stage operational amplifier circuit is arranged in the non-immersed transmembrane pressure detection circuit, the detected current signal is converted into an electrical signal by using the operational amplification piezoelectric effect, and the piezoelectric type can provide an anti-interference signal electrical output after isolation chip. The application has good linearity, simple circuit calculation and effectively solves the problem of electrical signal isolation between an analog signal and a single-chip microcomputer application system.

In some examples, a circuit includes a window comparator circuit. The window comparator circuit is configured to receive a input signal and a feedback signal, determine a delayed representation of the feedback signal based on a window control signal, determine, based on the feedback signal and the delayed representation of the feedback signal, a time window, responsive to a rising edge of the input signal occurring in the time window, or responsive to a falling edge of the input signal occurring in the time window, determine that the input signal and the feedback signal are locked, and responsive to the rising edge of the input signal occurring outside of the time window, or responsive to the falling edge of the input signal occurring outside of the time window, provide a pulse signal having an asserted value for a programmed period of time.

The invention relates to a high CMTI isolator link design and a related method. Described herein are on-chip isolator devices useful for high power applications designed to enhance high common mode transient immunity (CMTI) without sacrificing isolator gain. The isolator device includes two dies. The first die supports an isolation barrier and the second die is barrier-free. The second die is barrier-free because it lacks an isolation material (e.g., polyimide) typically used to maintain an isolation barrier in an on-chip isolator device. To enhance the CMTI, the second die is equipped with a tapped impedance element having a tap coupling the impedance element to a reference potential (e.g., ground), although no further isolation barrier is formed on the second die. The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die to create a discharge path for a common mode transient.

The present description concerns a device comprising two oscillators coupled to each other so as to operate in quadrature, each oscillator comprising an inductor and a capacitive element having a value selectable from among at least two values, each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductor is lower than the quality factor of its capacitive element.

A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.

Methods, apparatus, systems, and articles of manufacture to correct non-linearity in a transmitter are described. An example system includes: an input stage (202); a driver (204), an input terminal of the driver (204) being coupled to an output terminal of the input stage (202); an output buffer (208), an input terminal of the output buffer (208) being coupled to an output terminal of the driver (204), an output terminal of the output buffer (208) being coupled to a first input terminal of the input stage (202) via a resistor (212); and a non-linear correction circuitry (218) having an input terminal and an output terminal, the input terminal of the non-linear correction circuitry (218) being coupled to the output terminal of the output buffer (208) and the first input terminal of the input stage (202) via the resistor (212), the output terminal of the non-linearity correction circuitry (218) is coupled to the output terminal of the input stage (202) and the input terminal of the driver (204).

The invention relates to an air conditioner which comprises a control end unit circuit, a fan communication unit circuit, a fan driving unit circuit, a power supply control unit circuit and a fan. Wherein the fan communication unit circuit comprises a first communication branch circuit and a second communication branch circuit, the first communication branch circuit and the second communication branch circuit are both connected between the control end unit circuit and the fan driving unit circuit, the power supply control unit circuit is further connected with the first communication branch circuit, and the first communication branch circuit comprises a first optocoupler. The second communication branch comprises a second optocoupler, the first optocoupler and the second optocoupler are both connected between the control end unit circuit and the fan driving unit circuit, and one side, connected with the fan driving unit circuit, of the first optocoupler is connected with the power supply control unit circuit. Therefore, the number of the optocouplers is reduced, the layout flexibility of the circuit board is improved, and the use reliability of the air conditioner is improved.

Methods, apparatus, systems, and articles of manufacture are described to correct non-linearity in transmitters. An example system includes an input stage, a driver, an input terminal of the driver coupled to an output terminal of the input stage; an output buffer, an input terminal of the output buffer coupled to an output terminal of the driver, an output terminal of the output terminal coupled to a first input terminal of the input stage via a resistor; and non-linear correction circuitry having an input terminal and an output terminal, the input terminal of the non-linear correction circuitry coupled to the output terminal of the output buffer and the first input terminal of the input stage via the resistor, the output terminal of the non-linear correction circuitry coupled to the output terminal of the input stage and the input terminal of the driver.

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

A coupler includes a plurality of unit circuits connected to a plurality of differential line pairs and a single-ended line; and a plurality of isolation resistors connected between the plurality of differential line pairs, wherein each unit circuit of the plurality of unit circuits includes: a transformer including a primary side connected to one differential line pair among the plurality of differential line pairs, and a secondary side connected to the single-ended line, and a secondary-side capacitor connected in parallel to the secondary side.

An electronic device may include wireless circuitry. The wireless circuitry can include first and second input transistors, a third transistor having a gate terminal coupled to a gate terminal of the first input transistor and having a drain terminal coupled to the second input transistor, a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and having a drain terminal coupled to the first input transistor, one or more tail circuits coupled to source terminals of the third and fourth transistors, and a bias circuit configured to output a bias voltage that is conveyed to the gate terminals of the first and second input transistors and to the one or more tail circuits. The bias circuit can be coupled to the input transistors via a coil and to the one or more tail circuits via a feedforward path.

The invention discloses a power failure detection circuit and an isolator circuit. The power failure detection circuit comprises a voltage detection circuit, a pulse width modulation circuit and a logic circuit, the voltage detection circuit receives power supply voltage and compares the power supply voltage with threshold voltage to generate a pre-power-off signal, and when the power supply voltage is smaller than the threshold voltage, the pre-power-off signal jumps from a first state to a second state. The pulse width modulation circuit generates a pulse width modulation signal according to an input signal, wherein a duty cycle of the pulse width modulation signal is related to a value of the input signal. The logic circuit generates a power-off control signal according to the pre-power-off signal and the pulse width modulation signal, and when a first preset edge of the pulse width modulation signal after the pre-power-off signal jumps from the first state to the second state comes, the power-off control signal controls the pulse width modulation signal to be kept in the first state.

Methods, apparatus, systems, and articles of manufacture are described corresponding to current limit circuitry with controlled current variation. An example circuit includes an amplifier having an input terminal and an output terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the input terminal of the amplifier, the second terminal of the capacitor coupled to the output terminal of the amplifier; and diode circuitry having a first terminal and a second terminal, the first terminal of the diode circuitry coupled to the first terminal of the capacitor and the input terminal of the amplifier, the second terminal of the diode circuitry coupled to the second terminal of the capacitor and the output terminal of the amplifier.

The invention discloses an analog automatic pole-zero circuit which comprises a signal input module, a first follow-up phase end test, a digital adjustable resistor, a resistor, a capacitor, a comparator module and a single chip microcomputer. The invention also discloses an automatic pole-zero method based on the analog automatic pole-zero circuit, and the method comprises the steps: adjusting the digital adjustable resistor to a maximum value, setting the adjustable level module to be highest, gradually reducing the level until the level is appropriate, reducing the adjustable resistor until the level is appropriate, and obtaining an optimal pole-zero parameter value. According to the method, pole zero is realized by adopting an analog circuit, the problem of signal dynamic range matching is avoided, pole zero of large signals and continuous stacking signals can be realized, and compared with manual pole zero simulation, the complexity of manual debugging is avoided, and pole zero can be automatically simulated in real time at any time.

Embodiments of the present disclosure relate to reverse body biasing of a transistor using a photovoltaic source. A metal-oxide-semiconductor (MOS) transistor has a source terminal, a drain terminal, a gate terminal, and a body terminal. The source terminal is connected to receive a supply voltage, and the body terminal is connected to receive a reverse body bias voltage. A photovoltaic circuit has a first terminal connected to the source terminal of the MOS transistor and a second terminal connected to the body terminal of the MOS transistor. The photovoltaic circuit converts photons received from the environment to generate the reverse body bias voltage.

The main control device comprises a processing module with a switching pin and a plurality of signal pins, a first DIP switch, a second DIP switch, an inverting module, and a first switch and a second switch. The first DIP switch and second DIP switch are respectively connected to the signal pins through first and second signal switches. One end of the inverting module is connected to the processing module. The first switch connects to the first signal switches, the switching pin, the inverting module, and the operating voltage source. The second switch is connected to the second signal switches, the inverting module, and the operating voltage source.

A circuit is disclosed. The circuit includes a gallium nitride (GaN) switch having a gate terminal, a drain terminal and a source terminal, a driver circuit having an output terminal coupled to the gate terminal, where the driver circuit is arranged to generate an output voltage at the output terminal such that: the output voltage is at a first voltage when a voltage at the drain terminal is below a predetermined voltage; the output voltage is at a second voltage when 1) the voltage at the drain terminal is above the predetermined voltage and 2) a time period during which the output voltage is at the second voltage is less than a predetermined time. In one aspect, the second voltage is greater than the first voltage.

The invention discloses a high-power radio frequency switch circuit and a control method thereof, and belongs to the technical field of radio frequency switch circuits, the high-power radio frequency switch circuit comprises a blocking capacitor C2, a matching inductor L12, a diode D1, a capacitor C9, a blocking capacitor C4, a matching inductor L6, a diode D2, a capacitor C12, a blocking capacitor C7 and a matching inductor L7, one end of the blocking capacitor C2 is connected with an input end channel Term1, the other end of the blocking capacitor C2 is connected with one end of the matching inductor L12, and the other end of the matching inductor L12 is connected with the other end of the matching inductor L12. And the other end of the matching inductor L12 is connected to two paths of the switch, namely a first path and a second path, a grounded diode D3 and a grounded diode D4 are respectively connected between the capacitor C9 and the blocking capacitor C4 in the first path and the second path and between the capacitor C12 and the blocking capacitor C7 in the first path and the second path, and the diode D3 and the diode D4 are both connected with a feed circuit. After the two output channels are connected with the grounding diode D3 and the grounding diode D4, the isolation between the channels can be improved, the working frequency range is wider, and the high-frequency insertion loss is smaller.

The invention discloses an isolation feedback circuit based on magnetic saturation self-oscillation, which is applied to a DC / DC module power supply with a preceding-stage PWM control circuit, and comprises a self-oscillation circuit, a voltage and current conversion circuit, a low-pass filter circuit and a signal acquisition circuit, the self-oscillation circuit comprises a saturation inductor and an asymmetric circuit; the input end of the voltage and current conversion circuit is connected with the output voltage end of the DC / DC module power supply, and the output end of the voltage and current conversion circuit is connected with a secondary winding of the self-oscillation circuit; the input end of the low-pass filter circuit is connected with the signal output end of the self-excited oscillation circuit, and the output end of the low-pass filter circuit outputs a feedback voltage signal; the input end of the signal acquisition circuit is connected with the output end of the low-pass filter circuit, and the output end of the signal acquisition circuit is connected with the preceding-stage PWM control circuit. The defect that an optical isolation scheme is insufficient in radiation resistance is overcome, the integration level and the response speed of the whole circuit are improved, and the reliability requirement of spaceflight long-life application is met.