359results about "Logic circuit coupling arrangements" patented technology

The invention provides a control method and device of a radio frequency power supply, the radio frequency power supply and semiconductor process equipment, and is applied to the technical field of semiconductor process equipment, the method is applied to the radio frequency power supply which provides at least one pulse signal in each work period, and in the at least one pulse signal in each work period of the radio frequency power supply, the pulse signal is transmitted to the radio frequency power supply. Wherein one pulse signal is controlled according to a first control mode, and the first control mode is as follows: according to a forward power feedback value, a reflection power feedback value, a dissipation power feedback value and a bus voltage threshold value of a current radio frequency power supply, a bus voltage output to the radio frequency power supply is adjusted, and a bias voltage output to the radio frequency power supply is kept unchanged; compared with a protection circuit built according to electronic components in the prior art, the invention provides a software protection mechanism, the execution process is not easily influenced by factors such as environment temperature and electromagnetic interference, the protection mechanism is more reliable, and the safety of the radio frequency power supply in the operation process can be ensured.

The invention relates to the technical field of industrial automation field data acquisition, in particular to an ultrahigh-precision load data implementation method and circuit and a measurement and control instrument. The method comprises the steps that an excitation signal is provided for the load sensor through the precise low-drift direct-current power supply, and the excitation signal is applied to the power input end of the sensor after high-frequency noise is eliminated through the pi-type filter network. According to the method, a temperature-load coupled multi-broken-line nonlinear regression curve cluster is constructed, and a temperature variable is introduced into dynamic interpolation calculation of segmented endpoints, so that an error nonlinear cumulative effect caused by endpoint drift under a wide-temperature working condition is effectively inhibited. In the hardware level, the background noise of a sensor signal is suppressed to a microvolt level through the collaborative design of a precise low-drift power supply and multi-stage anti-aliasing filtering, and original data with a high signal-to-noise ratio is provided for a software compensation algorithm.

A digital isolator includes a receiver configured to receive digital raw data at a primary side of the digital isolator. A digital-to-digital encoder is disposed at the primary side of the digital isolator. The digital-to-digital encoder is configured to create coded data. One or more digital isolators are configured to transmit the coded data across a transformer and an isolation barrier to create output coded data. A digital-to digital decoder is disposed at a secondary side of the digital isolator. The digital-to digital decoder is configured to decode the output coded data to create decoded data, determine error in coupling across the digital isolator based on the decoded data and the digital raw data, and provide an error signal based the error in coupling across the digital isolator.

In some examples, a method comprises communicating first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is coded via a first coding technique that comprises ON-OFF shift Keying (OOK) with a differential carrier signal. The method also includes communicating second data between the first circuit and the second circuit via the differential communication channel across the galvanic isolation barrier within the circuit package, wherein the second data is coded via a second coding technique comprises differential pulse coding.

The invention discloses a level shift circuit, a control method thereof and electronic equipment, and relates to the technical field of integrated circuits. The circuit comprises a logic control module, an AC / DC coupling module and an inverted output module, in the logic control module, a first signal input end is connected with an input signal source, and a second signal input end is connected with an enable signal source; the AC-DC coupling module comprises a DC coupling unit and an AC coupling unit; in the direct current coupling unit, a first control input end is connected with a first control output end, and a second control input end is connected with a second control output end; in the AC coupling unit, an AC coupling input end is connected with a first control output end; the AC coupling output end is connected with the DC coupling output end; the inverted input end of the inverted output module is connected with the DC coupling output end, and the inverted output end is used for outputting a target level shift signal. And a low-delay, high-speed and good-duty-ratio level shifting function can be realized for an alternating current signal and a direct current signal.

The present application discloses a digital isolator including a signal transmitting circuit, a signal receiving circuit, and an isolation circuit. The isolation circuit is coupled between the signal transmitting circuit and the signal receiving circuit. The isolation circuit includes a first isolation unit for converting a received input modulation signal into a differential signal and a second isolation unit for providing an output modulation signal in response to receiving the differential signal. The first isolation unit and the second isolation unit have symmetrical circuit structures. By using a fully differential structure and a fully symmetrical structure, the circuit has improved immunity capability, and can suppress common mode transient interference greater than 200 kv / us.

The invention provides a digital isolator with both high-speed communication and high common-mode transient immunity. The digital isolator comprises a transmitter, a coupling inductor and a receiver, the transmitter comprises an oscillator, a modulation capacitor assembly and a common-mode transient immunity enhancement module; the oscillator is configured to receive a data signal and generate a first differential signal based on the data signal; the modulation capacitor assembly is configured to modulate a code element 0 into a first frequency and modulate a code element 1 into a second frequency; the common-mode transient immunity enhancement module is configured to determine a bias control signal according to the first differential signal; the receiver is configured to receive the second differential signal and obtain a square wave signal based on the second differential signal; obtaining a triangular wave signal based on the square wave signal; obtaining the maximum value of a triangular wave signal according to the falling edge signal of the square wave signal; and obtaining a target data signal based on the maximum value, so as to solve the problem of low communication and common-mode transient immunity performance of the existing digital isolator.

The invention relates to a full duplex digital isolator. A circuit is provided. The circuit comprises: a first transmitter circuit having a first input terminal arranged to receive first input data and a first node arranged to transmit first intermediate data corresponding to the first input data; a first receiver circuit including a second node arranged to receive the first intermediate data and a first output terminal arranged to generate first output data corresponding to the first input data; comprising a second input terminal and said second node, the second input terminal arranged to receive second input data, the second node further arranged to transmit second intermediate data corresponding to the second input data; and a second receiver circuit comprising a first node and a second output terminal, the first node being further arranged to receive the second intermediate data, and the second output terminal being arranged to generate second output data corresponding to the second input data.

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

The application provides an inhibitor circuit, a signal sending device and a communication system, and relates to the field of digital information transmission.The inhibitor circuit provided by the application comprises a first transistor and a second transistor, a first switch, a second switch and a first voltage generation module.When communication ends, the first switch and the second switch are closed, and the first transistor and the second transistor are turned on.When the signals on the first communication bus and the second communication bus reach a common mode state, the first switch and the second switch are turned off.The application further provides an inhibitor circuit which adds an additional path on the basis of the above inhibitor circuit.The application further provides a signal sending device which comprises the above inhibitor circuit.The application further provides a communication system which comprises the above signal sending device.The inhibitor circuit, the signal sending device and the communication system provided by the application can reduce the amplitude of tailing overshoot and ensure accurate decoding at the receiving end.

A reference clock signal generation system, comprising a first coupler, a selection switch control module, a selection switch, a crystal oscillator, a second coupler, a phase-locked loop module and an adjustable resistor; the input end of the crystal oscillator is connected with the output end of the selection switch, and the output end of the crystal oscillator is connected with the input end of the second coupler; the input end of the adjustable resistor is connected with the output end of the crystal oscillator, and the output end of the adjustable resistor is connected with the input end of the selection switch; the input end of the selection switch control module is connected with the output end of the first coupler, and the output end of the selection switch control module is connected with the input end of the selection switch; the input end of the phase-locked loop module is connected with the input end of the first coupler and the input end of the second coupler respectively; the output end of the phase-locked loop module is connected with the input end of the selection switch; the system can ensure that the output reference clock signal is phase coherent when the internal and external reference clock signals of different sources are switched, and can also adjust the frequency of the output signal of the internal crystal oscillator.

The embodiment of the invention provides a high-performance single-pole double-throw switch, and belongs to the technical field of wireless communication. The switch comprises a first coupling coil, the first coupling coil is provided with a first port and a fourth port, the first port is in an open circuit state, and the fourth port is connected with a signal receiving unit; the second coupling coil is provided with a second port and a third port, the second port is connected with the antenna unit, the third port is connected with the first control unit, and the first control unit controls the conduction state of the third port; the third coupling coil is provided with a fifth port and an eighth port, the fifth port is in an open circuit state, and the eighth port is connected with the signal transmitting unit; and the fourth coupling coil is provided with a sixth port and a seventh port, the sixth port is electrically connected with the antenna unit, the seventh port is connected with the second control unit, and the second control unit controls the conduction state of the seventh port. According to the embodiment of the invention, low insertion loss and high isolation can be realized.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

The invention relates to runtime antenna matching for near field communication wireless power transfer. Systems and methods for runtime antenna matching of wireless power devices are presented. The integrated circuit may include a controller. The integrated circuit may also include circuitry configured to sense a voltage in the switching converter. The circuit may be further configured to determine the presence or absence of a negative voltage spike in the sensed voltage. The controller may be configured to tune a capacitance of the antenna interface circuit between the switching converter and the antenna to perform impedance matching based on the presence or absence of a negative voltage spike in the sensed voltage.

The invention is suitable for the technical field of terahertz frequency mixing, and provides a terahertz monolithic integrated harmonic mixer. The mixer comprises a substrate and devices. The radio frequency port, the local oscillator port and the first matching transition structure are respectively connected with each coupling end of the coupler; the output end of the first matching transition structure is connected with the input end of the second matching transition structure and the first end of the anti-parallel diode pair. The second end of the anti-parallel diode pair is provided with a third grounding through hole. The output end of the second matching transition structure is connected with the input end of the low-pass filter; the output end of the low-pass filter is connected with the intermediate frequency port; the radio frequency port, the local oscillator port and the intermediate frequency port are GSG interfaces with grounding through holes; and a layer of metal is integrally arranged on the back surface of the substrate to connect the grounding through holes to form a coplanar waveguide. According to the mixer, harmonic mixing is realized through a simple process, the complexity is low, and meanwhile, the problems that the mixer cannot be integrated and the working frequency is low can be solved.

The invention discloses a dynamic coupling degree adjustable electric control coupler circuit which comprises a straight-through / coupling adjusting circuit, a coupling / straight-through adjusting circuit, a capacitor C1, a resistor R1, a resistor R2, a first acquisition feedback circuit, a second acquisition feedback circuit, a biasing circuit and a third control circuit. The other end of the capacitor C1 is electrically connected with the signal input end of the straight-through / coupling adjusting circuit, the other end of the capacitor C1 is further electrically connected with the input end of the coupling / straight-through adjusting circuit, one output end of the bias circuit provides bias level for the straight-through / coupling adjusting circuit through the resistor R1, and the bias level of the straight-through / coupling adjusting circuit is controlled through the control circuit. Continuous dynamic adjustment of the coupling degree of the directional coupler is achieved, and application to communication equipment needing adjustable coupling degree is met. The electrically controlled coupler circuit capable of dynamically adjusting the coupling degree has the effect of electrically controlling and adjusting the coupling degree of the coupler.

The invention relates to the technical field of integrated circuits and provides an impedance adjusting method based on hybrid control and a resistance network. The method comprises: connecting a target resistor between a ground terminal and the second terminal such that the target resistor and the resistor network are connected in series between the first terminal and the ground terminal; closing all binary code switches of the binary code resistor array, and then gradually changing the thermometer code control code according to a first preset step length; maintaining the first thermometer code control code, and then gradually changing the binary code control code according to a second preset step length; and determining a hybrid control code of the resistance network corresponding to the resistance value of the target resistor. Therefore, not only is the problem of an intermediate transition state effectively solved, but also the complexity caused by excessive bit control bits is reduced as much as possible under the condition that the same precision is realized.

According to some embodiments, a receiver comprises a positive terminal, a negative terminal, a first isolation capacitor connected to the positive terminal, a second isolation capacitor connected to the negative terminal, a resistor circuit connected to the first isolation capacitor and the second isolation capacitor to define a first high pass filter, an amplifier connected to the first high pass filter, a level detector connected to the amplifier, and a second high pass filter connected between the first high pass filter and the level detector.

Examples of an apparatus and method for power management are disclosed. In an example, a device includes a charge circuit, a discharge circuit, an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are couplable to a capacitor, and wherein the charge circuit includes an analog soft start circuit, and control logic configured to determine a discharge time of the capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit.

The present disclosure relates to an integrated circuit and an operation method thereof. The present disclosure provides an integrated circuit including a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node and generates an initial voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitor unit at the first node and are coupled to a second capacitor unit at a second node. The first voltage generation circuit generates a first control signal to the second voltage generation circuit based on the initial voltage at the first node and a first supply voltage from a second voltage terminal. The second voltage generation circuit generates a second control signal to the first node based on the first control signal received from the first voltage generation circuit and a second supply voltage different from the first supply voltage.

The application discloses a kind of sensing transducer and its voltage signal processing circuit, belong to the field of transducer, for using analog circuit to realize for sensor voltage signal segmented calibration, solved the problem that voltage signal is difficult to maintain higher signal accuracy under strong interference environment.Considering that the way of segmented calibration can improve the accuracy of sensor output voltage signal, and analog circuit has strong anti-interference ability, the segmented identification circuit of the application can deliver voltage signal to the segmented calibration circuit corresponding to the voltage value interval to which the voltage signal belongs, so that the segmented calibration circuit can multiply the received voltage signal by a predetermined slope and add a predetermined intercept, and output after signal conditioning circuit, so as to realize the segmented calibration of voltage signal, and each part of circuit is analog circuit, has strong anti-interference ability, so that voltage signal can maintain higher signal accuracy under strong interference environment, widen the application scenario of sensing transducer.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

The present invention discloses a novel high-isolation, low-insertion-loss switch matrix chip, comprising a switch matrix circuit disposed on a gallium arsenide (GaAs) pHEMT (Phe) semiconductor circuit layer. The switch matrix circuit comprises m input terminals, m switch structures, a vertical transition structure, n power dividers, and n output terminals. The vertical transition structure is configured as a coplanar waveguide. The input terminals are electrically connected to the signal input terminals of the switch structures, the signal output terminals of the switch structures are electrically connected to the vertical transition structure and the signal input terminals of the power dividers, the signal output terminals of the vertical transition structure are electrically connected to the signal input terminals of the power dividers, and the signal output terminals of the power dividers are electrically connected to the output terminals. A highly integrated switch matrix chip is achieved using a GaAs pHEMT process. The switch matrix chip integrates multiple switches and power dividers, along with a high-isolation vertical transition structure, achieving high isolation and low loss.

The application provides a kind of dual-channel low-frequency modulation intermediate frequency bipolar pulse signal generation system, it is related to integrated circuit technical field, including: power supply and signal isolation circuit, signal generation master module and signal generation slave module respectively connected with power supply and signal isolation circuit;The circuit structure in signal generation master module and signal generation slave module is identical;Signal generation master module includes the first step-down power supply circuit connected in turn, first MCU controller circuit, first intermediate frequency bipolar pulse signal generation circuit and first signal output interface, it also includes the first output current detection circuit and the first low-frequency current signal generation circuit connected with first MCU controller circuit, and first low-frequency current signal generation circuit is also connected with first intermediate frequency bipolar pulse signal generation circuit.The technical scheme of the application overcomes the problem that the medical device in the prior art cannot stimulate multiple acupoints simultaneously.

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The application provides a non-immersed transmembrane pressure detection system, which is characterized in that: a liquid inlet detection module, a permeation end detection module, a backflow end detection module and a transmembrane pressure calculation module are arranged, a non-immersed transmembrane pressure detection circuit is arranged in each of the liquid inlet detection module, the permeation end detection module and the backflow end detection module, the corresponding transmembrane pressure calculation result is obtained by calculating the liquid inlet detection signal, the permeation end detection signal and the backflow end detection signal output by the circuit, a four-stage amplification and analog signal isolation circuit composed of a high-precision resistance voltage division network, a first-stage operational amplifier circuit, a second-stage operational amplifier circuit, a linear optical coupler, a third-stage operational amplifier circuit and a fourth-stage operational amplifier circuit is arranged in the non-immersed transmembrane pressure detection circuit, the detected current signal is converted into an electrical signal by using the operational amplification piezoelectric effect, and the piezoelectric type can provide an anti-interference signal electrical output after isolation chip. The application has good linearity, simple circuit calculation and effectively solves the problem of electrical signal isolation between an analog signal and a single-chip microcomputer application system.

In some examples, a circuit includes a window comparator circuit. The window comparator circuit is configured to receive a input signal and a feedback signal, determine a delayed representation of the feedback signal based on a window control signal, determine, based on the feedback signal and the delayed representation of the feedback signal, a time window, responsive to a rising edge of the input signal occurring in the time window, or responsive to a falling edge of the input signal occurring in the time window, determine that the input signal and the feedback signal are locked, and responsive to the rising edge of the input signal occurring outside of the time window, or responsive to the falling edge of the input signal occurring outside of the time window, provide a pulse signal having an asserted value for a programmed period of time.

The invention relates to a high CMTI isolator link design and a related method. Described herein are on-chip isolator devices useful for high power applications designed to enhance high common mode transient immunity (CMTI) without sacrificing isolator gain. The isolator device includes two dies. The first die supports an isolation barrier and the second die is barrier-free. The second die is barrier-free because it lacks an isolation material (e.g., polyimide) typically used to maintain an isolation barrier in an on-chip isolator device. To enhance the CMTI, the second die is equipped with a tapped impedance element having a tap coupling the impedance element to a reference potential (e.g., ground), although no further isolation barrier is formed on the second die. The secondary side of the isolator of the first die is coupled to the tapped impedance element of the second die to create a discharge path for a common mode transient.

The present description concerns a device comprising two oscillators coupled to each other so as to operate in quadrature, each oscillator comprising an inductor and a capacitive element having a value selectable from among at least two values, each corresponding to an operating frequency value of the oscillators, each oscillator being configured so that, for each operating frequency value of the oscillators, the quality factor of its inductor is lower than the quality factor of its capacitive element.

A retention flip flop includes a first latch, a second latch, and a retention latch. The first and second latches are powered by an interruptible primary supply voltage while the retention latch is powered by a secondary supply voltage that is not interrupted. The retention flip-flop receives a single retention control signal that controls whether the flip-flop is in a standard mode or a retention mode. In the retention mode, the flip-flop clock signal is paused.