A suppressor circuit, a signal transmitting device and a communication system

Abstract

The application provides an inhibitor circuit, a signal sending device and a communication system, and relates to the field of digital information transmission.The inhibitor circuit provided by the application comprises a first transistor and a second transistor, a first switch, a second switch and a first voltage generation module.When communication ends, the first switch and the second switch are closed, and the first transistor and the second transistor are turned on.When the signals on the first communication bus and the second communication bus reach a common mode state, the first switch and the second switch are turned off.The application further provides an inhibitor circuit which adds an additional path on the basis of the above inhibitor circuit.The application further provides a signal sending device which comprises the above inhibitor circuit.The application further provides a communication system which comprises the above signal sending device.The inhibitor circuit, the signal sending device and the communication system provided by the application can reduce the amplitude of tailing overshoot and ensure accurate decoding at the receiving end.

Description

Technical Field

[0001] This application relates to the field of digital information transmission, and in particular to a suppressor circuit, a signal transmitting device, and a communication system. Background Technology

[0002] In signal transmission through communication interfaces, the transmission lines must meet specific impedance requirements. For example, the impedance of a USB 2.0 transmission line should be 90Ω ±10%. If there is a sudden impedance change in the path, the signal will be reflected, and the reflected energy will be superimposed on the original signal to form an overshoot. If the reflection continues, a slowly decaying tail overshoot will form.

[0003] Overshoot tail is a common signal integrity problem. Essentially, it occurs when signal energy cannot be effectively absorbed or released during transmission, causing energy to "stagnate" and slowly dissipate. Overshoot tail can lead to bit errors or protocol timing errors, resulting in communication failures.

[0004] Figure 1 This is a schematic diagram of an existing differential communication bus system; Figure 2 Under ideal conditions where no tailing or overshoot occurs, Figure 1 The diagram shows a pair of communication signals transmitted by the transmitting end in the system shown. Figure 3 In the event of tailing overshoot in actual communication, Figure 1 The diagram shows a pair of communication signals transmitted by the transmitting end in the system shown.

[0005] like Figure 2 As shown, TXP and TXN are a pair of communication bus signals emitted by the transmitting end. RXP and RXN are digital signals obtained by the receiving end from decoding the communication bus signals emitted by the transmitting end. When TXP-TXN is greater than a positive threshold, RXP is high and RXN is low. When TXP-TXN is less than a negative threshold, RXN is high and RXP is low.

[0006] At the end of bus communication, a sudden impedance change occurs at the transmitting end's output port, creating a tailing overshoot. Furthermore, the transformer includes inductance; when communication ends, the current in the transformer's inductor cannot immediately drop to zero, but is gradually released through the load resistance between the communication buses. This process generates inductor current flowing through the resistor, producing voltage, which also contributes to the tailing overshoot. Figure 3 As shown, the trailing overshoot generated by signals TXP and TXN at the end of communication will cause bit errors in the digital signal decoded by the receiver, thus causing communication errors. Summary of the Invention

[0007] To address the technical problems existing in the prior art, this application proposes a suppressor circuit, characterized by comprising: a first transistor and a second transistor connected in series, the first transistor and the second transistor being of the same type and size, and their sources being electrically connected to each other and their gates being electrically connected to each other, wherein the drain of the first transistor is electrically connected to a first communication bus, and the drain of the second transistor is electrically connected to a second communication bus; a first switch, the first terminal of which is electrically connected to a first power supply, and the second terminal of which is electrically connected to the sources of the first transistor and the second transistor; a second switch, the first terminal of which is electrically connected to the gates of the first transistor and the second transistor, and the second terminal of which is electrically connected to a second power supply, wherein the voltage of the first power supply is higher or lower than the voltage of the second power supply; a first voltage generation module, the first terminal of which is electrically connected to the sources of the first transistor and the second transistor, and the second terminal of which is electrically connected to the gates of the first transistor and the second transistor; when communication ends, the first switch and the second switch close under the control of a first control signal, and the voltage difference between the first terminal and the second terminal of the first voltage generation module causes the first transistor and the second transistor to conduct; when the signals on the first communication bus and the second communication bus reach a common-mode state, the first switch and the second switch open under the control of the first control signal.

[0008] Specifically, the suppressor circuit proposed in this application is characterized by further comprising a first current source and a second current source, wherein a first end of the first current source is electrically connected to the first power supply, and a second end of the first current source is electrically connected to a first end of the first switch; a first end of the second current source is electrically connected to a second end of the second switch, and a second end of the second current source is electrically connected to the second power supply.

[0009] In particular, the suppressor circuit proposed in this application is characterized by further comprising a third transistor, the drain of which is electrically connected to the source of the first transistor and the second transistor, the source of which is electrically connected to the gate of the first transistor and the second transistor, and the gate of which is configured to receive the first control signal or a variation thereof.

[0010] Specifically, the suppressor circuit proposed in this application is characterized in that the first voltage generation module includes: a resistor electrically connected between the source and gate of the first transistor; or a Zener diode, the cathode of which is electrically connected to the second terminal of the first switch and the anode of which is electrically connected to the first terminal of the second switch; or two or more diodes, wherein the anode of the first diode is electrically connected to the second terminal of the first switch, the cathode of the last diode is electrically connected to the first terminal of the second switch, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more P-MOSFETs with their gates and drains shorted, wherein the source of the first P-MOSFET is electrically connected to the second terminal of the first switch, the drain of the last P-MOSFET is electrically connected to the first terminal of the second switch, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more N-MOSFETs with their gates and drains shorted, wherein the drain of the first N-MOSFET is electrically connected to the second terminal of the first switch, the source of the last N-MOSFET is electrically connected to the first terminal of the second switch, and the source of each of the remaining N-MOSFETs is electrically connected to the drain of the next N-MOSFET.

[0011] Specifically, the suppressor circuit proposed in this application is characterized in that the first switch includes a fourth transistor, and the second switch includes a fifth transistor, wherein the fifth transistor and the fourth transistor are of complementary types; wherein the source of the fourth transistor is electrically connected to the sources of the first transistor and the second transistor, and the drain of the fourth transistor is electrically connected to the first power supply; the drain of the fifth transistor is electrically connected to the gates of the first transistor and the second transistor, the source of the fifth transistor is electrically connected to the second power supply, the gate of the fifth transistor is configured to receive the first control signal, and the gate of the fourth transistor is electrically connected to the gates of the first transistor and the second transistor; the breakdown voltage of the first transistor, the second transistor, the fourth transistor, and the fifth transistor is higher than the breakdown voltage of the other transistors in the circuit; the suppressor circuit further includes a first protection module, which is connected in parallel with the first voltage generation module and configured to control the upper limit of the voltage across the first voltage generation module, wherein the impedance of the first protection module is less than the impedance of the first voltage generation module.

[0012] Specifically, the suppressor circuit proposed in this application is characterized in that the first protection module includes: a Zener diode, the cathode of which is electrically connected to the second terminal of the first switch, and the anode of which is electrically connected to the first terminal of the second switch; or two or more diodes, wherein the anode of the first diode is electrically connected to the second terminal of the first switch, the cathode of the last diode is electrically connected to the first terminal of the second switch, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more P-MOSFETs with their gates and drains shorted, wherein the source of the first P-MOSFET is electrically connected to the second terminal of the first switch, the drain of the last P-MOSFET is electrically connected to the first terminal of the second switch, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more N-MOSFETs with their gates and drains shorted, wherein... The drain of the first N-MOSFET is electrically connected to the second terminal of the first switch, the source of the last N-MOSFET is electrically connected to the first terminal of the second switch, and the source of each of the remaining N-MOSFETs is electrically connected to the drain of the next N-MOSFET; or one or more units in series, each unit including a first sub-transistor and a second sub-transistor, the first sub-transistor being a P-MOSFET with its gate and drain shorted, the second sub-transistor being an N-MOSFET with its gate and drain shorted, the gates and drains of the first sub-transistor and the second sub-transistor being electrically connected together, wherein the source of the P-MOSFET of the first unit is electrically connected to the second terminal of the first switch, the source of the N-MOSFET of the last unit is electrically connected to the first terminal of the second switch, and the source of the N-MOSFET of each of the remaining units is electrically connected to the source of the P-MOSFET of the next unit.

[0013] This application also proposes a suppressor circuit, characterized in that it comprises: a sixth transistor and a seventh transistor connected in series, the sixth transistor and the seventh transistor being of the same type and size, and their respective sources being electrically connected to each other and their respective gates being electrically connected to each other, wherein the drain of the sixth transistor is electrically connected to a third communication bus and the drain of the seventh transistor is electrically connected to a fourth communication bus; an eighth transistor and a ninth transistor connected in series, the eighth transistor and the ninth transistor being of the same type and size, and their respective sources being electrically connected to each other and their respective gates being electrically connected to each other, wherein the drain of the eighth transistor is electrically connected to a third communication bus and the drain of the ninth transistor is electrically connected to a fourth communication bus; a third switch, the first terminal of which is electrically connected to a third power supply and the second terminal of which is electrically connected to the gates of the sixth transistor and the seventh transistor; and a fourth switch, the first terminal of which is electrically connected to the gates of the eighth transistor and the ninth transistor and the second terminal of which is electrically connected to a fourth power supply. The system comprises: a third power supply whose voltage is higher or lower than that of the fourth power supply; a second voltage generation module, the first terminal of which is electrically connected to the gates of the sixth and seventh transistors, and the second terminal of which is electrically connected to the sources of the sixth and seventh transistors; a third voltage generation module, the first terminal of which is electrically connected to the sources of the eighth and ninth transistors, and the second terminal of which is electrically connected to the gates of the eighth and ninth transistors; when communication ends, the third and fourth switches close under the control of a second control signal, the voltage difference between the first and second terminals of the second voltage generation module causes the sixth and seventh transistors to conduct, and the voltage difference between the first and second terminals of the third voltage generation module causes the eighth and ninth transistors to conduct; when the signals on the third and fourth communication buses reach a common-mode state, the third and fourth switches open under the control of the second control signal.

[0014] Specifically, the suppressor circuit proposed in this application is characterized by further including a third current source and a fourth current source, wherein the first end of the third current source is electrically connected to the third power supply, and the second end of the third current source is electrically connected to the first end of the third switch; the first end of the fourth current source is electrically connected to the second end of the fourth switch, and the second end of the fourth current source is electrically connected to the fourth power supply.

[0015] Specifically, the suppressor circuit proposed in this application is characterized by further comprising a tenth transistor and / or an eleventh transistor, wherein the drain of the tenth transistor is electrically connected to the source of the sixth transistor and the seventh transistor, the source of the tenth transistor is electrically connected to the gate of the sixth transistor and the seventh transistor, and the gate of the tenth transistor is configured to receive the second control signal; the drain of the eleventh transistor is electrically connected to the source of the eighth transistor and the ninth transistor, the source of the eleventh transistor is electrically connected to the gate of the eighth transistor and the ninth transistor, and the gate of the eleventh transistor is configured to receive a variation of the second control signal.

[0016] Specifically, the suppressor circuit proposed in this application is characterized in that the second voltage generation module includes: a resistor electrically connected between the source and gate of the sixth transistor; or a Zener diode, the cathode of which is electrically connected to the gates of the sixth and seventh transistors, and the anode of which is electrically connected to the sources of the sixth and seventh transistors; or two or more diodes, wherein the anode of the first diode is electrically connected to the gates of the sixth and seventh transistors, the cathode of the last diode is electrically connected to the sources of the sixth and seventh transistors, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more P-MOSFETs with their gate and drain shorted. The first P-MOSFET has its source electrically connected to the gates of the sixth and seventh transistors, the last P-MOSFET has its drain electrically connected to the source of the sixth and seventh transistors, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more N-MOSFETs with their gates and drains shorted, wherein the drain of the first N-MOSFET is electrically connected to the gates of the sixth and seventh transistors, the last N-MOSFET has its source electrically connected to the gates of the sixth and seventh transistors, and the source of each of the remaining N-MOSFETs is electrically connected to the drain of the next N-MOSFET.

[0017] Specifically, the suppressor circuit proposed in this application is characterized in that the third voltage generation module includes: a resistor electrically connected between the source and gate of the eighth transistor; or a Zener diode, the cathode of which is electrically connected to the source of the eighth transistor and the ninth transistor, and the anode of which is electrically connected to the gate of the eighth transistor and the ninth transistor; or two or more diodes, wherein the anode of the first diode is electrically connected to the source of the eighth transistor and the ninth transistor, the cathode of the last diode is electrically connected to the gate of the eighth transistor and the ninth transistor, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more P-MOSFETs with their gate and drain shorted. The first P-MOSFET has its source electrically connected to the sources of the eighth and ninth transistors, the last P-MOSFET has its drain electrically connected to the gates of the eighth and ninth transistors, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more N-MOSFETs with their gates and drains shorted, wherein the drain of the first N-MOSFET is electrically connected to the sources of the eighth and ninth transistors, the last N-MOSFET has its source electrically connected to the gates of the eighth and ninth transistors, and the source of each of the remaining N-MOSFETs is electrically connected to the gate of the next N-MOSFET.

[0018] Specifically, the suppressor circuit proposed in this application is characterized in that the third switch includes a twelfth transistor, and the fourth switch includes a thirteenth transistor, wherein the twelfth transistor and the thirteenth transistor are of complementary types; wherein the drain of the twelfth transistor is electrically connected to the gates of the sixth transistor and the seventh transistor, and its source is electrically connected to the third power supply; the drain of the thirteenth transistor is electrically connected to the gates of the eighth transistor and the ninth transistor, and the source of the thirteenth transistor is electrically connected to the fourth power supply; the gate of the thirteenth transistor is configured to receive the second control signal, and the gate of the twelfth transistor is configured to receive a variation of the second control signal. The sixth, seventh, eighth, ninth, twelfth, and thirteenth transistors have a higher withstand voltage than the other transistors in the circuit. The suppressor circuit also includes a second protection module connected in parallel with the second voltage generation module, configured to control the upper limit of the voltage across the second voltage generation module, wherein the impedance of the second protection module is less than the impedance of the second voltage generation module. The suppressor circuit also includes a third protection module connected in parallel with the third voltage generation module, configured to control the upper limit of the voltage across the third voltage generation module, wherein the impedance of the third protection module is less than the impedance of the third voltage generation module.

[0019] Specifically, the suppressor circuit proposed in this application is characterized in that the second protection module comprises: a Zener diode, the cathode of which is electrically connected to the gate of the sixth transistor and the seventh transistor, and the anode of which is electrically connected to the source of the sixth transistor and the seventh transistor; or two or more diodes, wherein the anode of the first diode is electrically connected to the gate of the sixth transistor and the seventh transistor, the cathode of the last diode is electrically connected to the source of the sixth transistor and the seventh transistor, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more P-MOSFETs with their gates and drains shorted, wherein the source of the first P-MOSFET is electrically connected to the gate of the sixth transistor and the seventh transistor, the last P-MOSFET is electrically connected to the source of the sixth transistor and the seventh transistor, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more N-MOSFETs with their gates and drains shorted. FET, wherein the drain of the first N-MOSFET is electrically connected to the gates of the sixth and seventh transistors, the source of the last N-MOSFET is electrically connected to the sources of the sixth and seventh transistors, and the source of each remaining N-MOSFET is electrically connected to the drain of the next N-MOSFET; or one or more units in series, each unit including a third sub-transistor and a fourth sub-transistor, the third sub-transistor being a gate-drain short-circuited P-MOSFET, the fourth sub-transistor being a gate-drain short-circuited N-MOSFET, the gates and drains of the third and fourth sub-transistors being electrically connected together, wherein the source of the P-MOSFET of the first unit is electrically connected to the gates of the sixth and seventh transistors, the source of the N-MOSFET of the last unit is electrically connected to the sources of the sixth and seventh transistors, and the source of the N-MOSFET of each remaining unit is electrically connected to the source of the P-MOSFET of the next unit.

[0020] Specifically, the suppressor circuit proposed in this application is characterized in that the third protection module comprises: a Zener diode, the cathode of which is electrically connected to the source of the eighth transistor and the ninth transistor, and the anode of which is electrically connected to the gate of the eighth transistor and the ninth transistor; or two or more diodes, wherein the anode of the first diode is electrically connected to the source of the eighth transistor and the ninth transistor, the cathode of the last diode is electrically connected to the gate of the eighth transistor and the ninth transistor, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more P-MOSFETs with gate-drain shorted, wherein the source of the first P-MOSFET is electrically connected to the source of the eighth transistor and the ninth transistor, the drain of the last P-MOSFET is electrically connected to the gate of the eighth transistor and the ninth transistor, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more N-MOSFETs with gate-drain shorted. An OSFET, wherein the drain of the first N-MOSFET is electrically connected to the source of the eighth and ninth transistors, the source of the last N-MOSFET is electrically connected to the gate of the eighth and ninth transistors, and the source of each remaining N-MOSFET is electrically connected to the drain of the next N-MOSFET; or one or more units in series, each unit including a fifth sub-transistor and a sixth sub-transistor, the fifth sub-transistor being a P-MOSFET with its gate and drain shorted, the sixth sub-transistor being an N-MOSFET with its gate and drain shorted, the gates and drains of the fifth and sixth sub-transistors being electrically connected together, wherein the source of the P-MOSFET of the first unit is electrically connected to the source of the eighth and ninth transistors, the source of the N-MOSFET of the last unit is electrically connected to the gate of the eighth and ninth transistors, and the source of the N-MOSFET of each remaining unit is electrically connected to the source of the P-MOSFET of the next unit.

[0021] This application also proposes a signal transmitting device, characterized in that it includes a transmitter and the aforementioned suppressor circuit.

[0022] This application also proposes a communication system, characterized in that it includes a signal receiving device, an isolation network, and the aforementioned signal transmitting device. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of an existing differential communication bus system;

[0024] Figure 2 Under ideal conditions where no tailing or overshoot occurs, Figure 1 A schematic diagram of a pair of communication signals transmitted by the transmitting end in the system shown;

[0025] Figure 3 In the event of tailing overshoot in actual communication, Figure 1 A schematic diagram of a pair of communication signals transmitted by the transmitting end in the communication bus system shown.

[0026] Figure 4 This is a schematic diagram of a communication bus system according to an embodiment of this application;

[0027] Figure 5 This is a schematic diagram of a pair of communication signals transmitted by a transmitter in a communication bus system according to an embodiment of this application;

[0028] Figure 6 This is a schematic circuit diagram of a tailing overshoot suppressor according to an embodiment of this application;

[0029] Figure 7 This is a schematic circuit diagram of a tailing overshoot suppressor according to an embodiment of this application;

[0030] Figure 8 yes Figure 6 The timing diagram shown is for the tailing overshoot suppressor.

[0031] Figure 9 This is a circuit diagram of a voltage generation module according to several embodiments of this application;

[0032] Figure 10 This is a timing diagram of a tailing overshoot suppressor without a fast pull-down path according to an embodiment of this application;

[0033] Figure 11 This is a schematic circuit diagram of a tailing overshoot suppressor including a fast pull-down path according to an embodiment of this application;

[0034] Figure 12 This is a schematic circuit diagram of a tailing overshoot suppressor including a fast pull-down path according to another embodiment of this application;

[0035] Figure 13 yes Figure 11 The timing diagram shown is for the tailing overshoot suppressor.

[0036] Figure 14 This is a schematic circuit diagram of a tailing overshoot suppressor according to an embodiment of this application;

[0037] Figure 15 This is a schematic circuit diagram of a tailing overshoot suppressor including a fast pull-down path according to an embodiment of this application;

[0038] Figure 16 This is a schematic circuit diagram of a high-voltage tailing overshoot suppressor according to an embodiment of this application;

[0039] Figure 17 These are circuit diagrams of protection modules according to various embodiments of this application;

[0040] Figure 18 This is a schematic circuit diagram of a high-voltage tailing overshoot suppressor according to an embodiment of this application;

[0041] Figure 19 This is a schematic circuit diagram of a high-voltage tailing overshoot suppressor including a fast pull-down path according to an embodiment of this application;

[0042] Figure 20 This is a schematic circuit diagram of a high-voltage tailing overshoot suppressor according to an embodiment of this application;

[0043] Figure 21 This is a schematic circuit diagram of a high-voltage tailing overshoot suppressor including a fast pull-down path according to an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0046] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0047] A transistor can refer to any type of transistor, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carriers are electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode; the first electrode can be the drain or source, and the corresponding second electrode can be the source or drain. The gate or control electrode can be the control electrode. When a transistor is a bipolar junction transistor (BJT), the base is its control electrode; the first electrode can be the collector or emitter, and the corresponding second electrode can be the emitter or collector. The base or control electrode can be the control electrode. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS, or CMOS processes.

[0048] Figure 4 This is a schematic diagram of a communication bus system according to an embodiment of this application.

[0049] According to one embodiment, compared to Figure 1 The common communication bus system shown is Figure 4 The communication bus system shown adds a tailing overshoot suppressor 412 between the communication buses (TXP and TXN). At the end of communication, the tailing overshoot suppressor 412, through precise timing control, short-circuits the port between TXP and TXN, forcibly establishing a discharge path and rapidly discharging residual current within a few microseconds. The tailing overshoot suppressor 412 can greatly reduce the amplitude of the tailing overshoot, ensuring that the receiving end receives an accurate signal and performs decoding.

[0050] According to one embodiment, the communication bus system may include a control system 40 configured to generate signals TXS and TXD. Signal TXS is a control signal that controls a tail overshoot suppressor 412, controlling the activation or deactivation of the tail overshoot suppressor 412. Transmitter 411 generates communication bus signals TXP and TXN based on signal TXD.

[0051] Figure 5 This is a schematic diagram of a pair of communication signals transmitted by a transmitter in a communication bus system according to an embodiment of this application.

[0052] According to one embodiment, during the time period before t0, the communication bus system is in the communication phase, and TXP and TXN transmit differential signals (e.g., TXP is high and TXN is low, or vice versa). At this time, the control signal TXS of the tailing overshoot suppressor 412 is low, and the tailing overshoot suppressor 412 is turned off.

[0053] According to one embodiment, at time t0, data transmission is completed, and the control system 40 immediately sets TXS to a high level, activating the tailing overshoot suppressor 412. From time t0 to time t1, the communication bus system is in the suppression phase. During this period, the ports between TXP and TXN are short-circuited, allowing the residual current to dissipate rapidly within a few microseconds.

[0054] According to one embodiment, at time t1, suppression is completed, the control system 40 controls TXS to fall back to a low level, the tailing overshoot suppressor 412 is turned off, and the communication bus system re-enters the communication phase. TXP and TXN are ready to transmit new data again.

[0055] Figure 6 This is a schematic circuit diagram of a tailing overshoot suppressor according to an embodiment of this application.

[0056] Figure 7 This is a schematic circuit diagram of a tailing overshoot suppressor according to an embodiment of this application.

[0057] Figure 8 yes Figure 6 The timing diagram shown is for the tailing overshoot suppressor.

[0058] According to one embodiment, the tailing overshoot suppressor includes a switch 604, a voltage generation module 605, and a switch 606 connected in series between a power supply and ground. Alternatively, according to one embodiment, the tailing overshoot suppressor may further include a current source 603 and a current source 607 connected in series with the switch 604, voltage generation module 605, and switch 606. One end of the current source 603 is electrically connected to the power supply V. DD One end of the current source 607 is electrically connected to switch 604. One end of the current source 607 is electrically connected to switch 606, and the other end is grounded.

[0059] According to one embodiment, the tailing overshoot suppressor may further include transistors 601 and 602. Transistors 601 and 602 may be MOSFETs, both of which are large-sized MOSFETs (larger than the other transistors in the tailing overshoot suppressor), and both are of the same size and type. Figure 6In the illustrated embodiment, transistors 601 and 602 are both P-MOSFETs, connected in series between buses TXP and TXN. The sources of transistors 601 and 602 are electrically connected to the first terminal of voltage generation module 605, and their gates are electrically connected to the second terminal of voltage generation module 605. The drain of transistor 601 is configured to receive the TXP signal, and the drain of transistor 602 is configured to receive the TXN signal. The TXS signal controls the opening and closing of switches 604 and 606. When the TXS signal is high or active, switches 604 and 606 are closed; when the TXS signal is low or inactive, switches 604 and 606 are open. An active TXS signal indicates that the communication bus system is in a suppressed state. The voltage at the first terminal of the voltage generation module, i.e., point A, is V. A The voltage at the second terminal, point B, is V. B V A and V B voltage difference V ON This represents the gate-source voltage of transistors 601 and 602. When switches 604 and 606 are closed, current sources 603 and 607 provide bias currents I1 and I2 to voltage generation module 605, where I1 equals I2.

[0060] According to one embodiment, transistors 601 and 602 can also both be N-MOSFETs, such as... Figure 7 As shown. In this case, the second terminal of the voltage generation module is electrically connected between the power supply and the sources of the two transistors.

[0061] According to one embodiment, such as Figure 8 As shown, during the time period before t0, the communication bus system is in the communication phase, TXS is low, switches 604 and 606 are open, the tailing overshoot suppressor is not working, and V... A With V B The current in voltage generation module 605 is zero, and the gate-source voltages of transistors 601 and 602 are zero, indicating they are in the off state. At this time, the TXP and TXN signals are transmitted normally.

[0062] According to one embodiment, at time t0, data transmission is complete, TXS is set to high level, switches 604 and 606 are closed, and the tailing overshoot suppressor is activated. Current sources 603 and 607, together with voltage generation module 605, form a current path. The currents I1 and I2 generated by the two current sources are equal in magnitude and act on voltage generation module 605, generating a gate-source voltage that satisfies the threshold voltages of transistors 601 and 602, causing transistors 601 and 602 to conduct. During the time period from t0 to t1, TXP and TXN are adjusted to common-mode voltages. When the tailing overshoot suppressor is activated, the voltage V at point A is... A The common-mode voltages of TXP and TXN are given, and the voltage at point B is V. B It drops to a low level. At this time, the common-mode voltage, V... A This is related to the impedance of the voltage generation module 605. For example, adjusting the impedance of the voltage generation module 605 to a specific value can make the common-mode voltage equal to V. DD / 2.

[0063] According to one embodiment, at time t1, suppression is complete, TXS is set to low, switches 604 and 606 are open, and the tailing overshoot suppressor stops working. At this time, the common-mode voltage, i.e., the voltage at point A, V... A The value is (TXP + TXN) / 2. After switches 604 and 606 are opened, the voltages at points A and B will tend to be the same. Furthermore, the voltage at point A, influenced by TXP and TXN, has a stronger deterministic effect. Therefore, with the energy provided by TXP and TXN, the voltage at point B rises to be equal to that at point A, making the voltages at points A and B consistent. The communication bus system then returns to the communication phase, and the TXP and TXN signals are transmitted normally.

[0064] According to one embodiment, Figure 6 The tailing overshoot suppressor shown establishes a discharge path by shorting TXP and TXN, quickly dissipating residual charge to bring TXP and TXN into a common-mode state, thereby suppressing tailing overshoot, improving the accuracy of the signal received by the receiver of the communication system, and facilitating more accurate decoding.

[0065] Figure 9 This is a circuit diagram of a voltage generation module according to several embodiments of this application.

[0066] According to one embodiment, the voltage generation module may include a resistor electrically connected between point A and point B, such as... Figure 9 As shown.

[0067] According to other embodiments, the voltage generation module may further include a Zener diode electrically connected between points A and B, such as... Figure 9 As shown, the cathode of the Zener diode is connected to point A, and the anode is connected to point B.

[0068] According to another embodiment, the voltage generation module may further include a plurality of diodes connected in series between points A and B in the same manner, such as... Figure 9 As shown in the diagram. The anode of the first diode is connected to point A, the cathode of the last diode is connected to point B, and the cathode of each of the remaining diodes is connected to the anode of the next diode. Figure 9 The voltage generation module can include multiple diodes connected in series, such as two, three, or other numbers of diodes.

[0069] According to yet another embodiment, the voltage generation module may further include a P-MOSFET with its gate-drain shorted and connected in series between points A and B in the same manner, such as... Figure 9 As shown in the diagram, the source of the first P-MOSFET is connected to point A, the drain of the last P-MOSFET is connected to point B, and the drain of each of the remaining P-MOSFETs is connected to the source of the next P-MOSFET. Figure 9 The voltage generation module may include multiple gate-drain shorted P-MOSFETs connected in series, such as two, three or other numbers of gate-drain shorted P-MOSFETs.

[0070] According to yet another embodiment, the voltage generation module may further include an N-MOSFET that is connected in series with its gate drain shorted between points A and B in the same manner, such as... Figure 9 As shown in the diagram, the drain of the first N-MOSFET is connected to point A, the source of the last N-MOSFET is connected to point B, and the source of each of the remaining N-MOSFETs is connected to the drain of the next N-MOSFET. Figure 9 The voltage generation module may include multiple N-MOSFETs with shorted gate drains connected in series, such as two, three or other numbers of N-MOSFETs with shorted gate drains.

[0071] According to several embodiments, Figure 9 All the embodiments shown satisfy the condition that when switches 604 and 606 are closed, the voltage drop between points A and B is sufficient to turn on transistors 601 and 602, that is, at least the threshold voltages of transistors 601 and 602 are reached.

[0072] In practical applications, when the overshoot suppressor has completed its suppression and the system needs to return to the normal communication phase, the transistor cannot be turned off quickly due to the relatively high impedance of the voltage generation module. Figure 10 This is a timing diagram of a tailing overshoot suppressor that does not include a fast pull-down path, according to an embodiment of this application.

[0073] Figure 11This is a schematic circuit diagram of a tailing overshoot suppressor including a fast pull-down path according to an embodiment of this application.

[0074] Figure 12 This is a schematic circuit diagram of a tailing overshoot suppressor including a fast pull-down path according to another embodiment of this application.

[0075] Figure 13 yes Figure 11 The timing diagram shown is for the tailing overshoot suppressor.

[0076] According to one embodiment, reference Figure 6 The higher the gate-source voltage of transistors 601 and 602, the lower their on-resistance. This allows for the release of more energy from residual charge on signal lines TXP and TXN within a short time, resulting in better overshoot suppression. Increasing the gate-source voltage of transistors 601 and 602 requires a larger inter-node impedance (A / B). However, a larger A / B node impedance slows down the turn-off speed of transistors 601 and 602. Furthermore, the parasitic capacitance inherent in transistors 601 and 602 also slows down their turn-off speed, potentially affecting data transmission in the next stage.

[0077] According to one embodiment, such as Figure 10 As shown, at time t1, the TXS signal drops from high to low. Because transistors 601 and 602 have large parasitic capacitances, the turn-off time is relatively long, so the voltage difference V between points A and B is... A -V B The voltage cannot be immediately reduced to below the threshold voltages of transistors 601 and 602, but rather slowly reduced over the time interval t1 to t2. Until after time t2, V... A -V B When the voltage is reduced to below the threshold voltage of transistors 601 and 602, transistors 601 and 602 are turned off, and the tailing overshoot suppressor is turned off. That is, the tailing overshoot suppressor is not yet turned off during the time period t1 to t2. However, if the communication bus system needs to start the next stage of data transmission at time t1 or at some point during the time period t1 to t2, the data transmission in the next stage will be affected because the tailing overshoot suppressor is not yet turned off.

[0078] According to one embodiment, in order to solve the problem of slow turn-off speed of transistors 1101 and 1102, in Figure 6Based on the illustrated embodiment, this embodiment adds transistor 1103 as a fast pull-down path. The drain of transistor 1103 is electrically connected to the source of transistor 1101, and the source of transistor 1103 is electrically connected to the gate of transistor 1101. The TXS_B signal is the inverted version of the TXS signal and is configured to drive transistor 1103.

[0079] According to one embodiment, the voltage generation module 1104 may be selected as... Figure 9 Any of the implementation methods described herein.

[0080] According to one embodiment, Figure 11 In the embodiment shown, transistors 1101 and 1102 are both P-MOSFETs.

[0081] According to one embodiment, transistors 1101 and 1102 can also both be N-MOSFETs, such as... Figure 12 As shown.

[0082] According to one embodiment, the operating timing of a tailing overshoot suppressor including a fast pull-down path is as follows: Figure 13 As shown. At time t1, the TXS signal drops from high to low, and the TXS_B signal rises from low to high, turning on transistor 1103. Because the on-resistance of transistor 1103 is much smaller than the impedance of voltage generation module 1104, at time t1, the voltage difference V between points A and B is V. A -V B The gate-source voltages of transistors 1101 and 1102 are quickly pulled down to 0 by transistor 1103, thereby enabling the tailing overshoot suppressor to be turned off quickly and avoiding affecting the data transmission in the next stage.

[0083] According to one embodiment, transistor 1103 can be either an N-MOSFET or a P-MOSFET (when a P-MOSFET is selected, its gate is configured to receive the signal TXS). Using an N-MOSFET allows the voltage difference between point A and point B to be reduced to 0 more quickly.

[0084] According to one embodiment, Figure 11 The illustrated embodiment adds a fast pull-down path to the tailing overshoot suppressor, accelerating the turn-off speed of transistors 1101 and 1102, enabling the tailing overshoot suppressor to turn off quickly. This is used when the communication bus system needs to start the next stage of data transmission shortly after the previous data transmission. Figure 11 The trailing overshoot suppressor shown can meet this requirement.

[0085] Figure 14 This is a schematic circuit diagram of a tailing overshoot suppressor according to an embodiment of this application.

[0086] In this embodiment, transistors 1401 and 1402 are connected in series at their sources, and transistors 1403 and 1404 are also connected in series at their sources, further reducing the impedance of the discharge path between signals TXP and TXN. Transistors 1401 and 1402 can be N-MOSFETs, and transistors 1403 and 1404 can be P-MOSFETs.

[0087] According to one embodiment, such as Figure 14 As shown, the drains of transistors 1401 and 1403 are electrically connected to bus TXP, and the drains of transistors 1402 and 1404 are electrically connected to bus TXN. The first terminal of voltage generation module 1406 is electrically connected to switch 1405, and its output terminal is electrically connected to the sources of transistors 1403 and 1404. The input terminal of voltage generation module 1407 is electrically connected to the sources of transistors 1401 and 1402, and its output terminal is electrically connected to switch 1408.

[0088] According to one embodiment, voltage generation module 1406 and voltage generation module 1407 may be selected. Figure 9 Any of the implementation methods described herein.

[0089] exist Figure 6 In the illustrated embodiment, the common-mode voltage during operation of the overshoot suppressor can be adjusted by changing the impedance of the voltage generation module 605 to a specific value. However, in practice, adjusting the impedance of the voltage generation module 605 to a specific value is quite difficult. Figure 14 In the illustrated embodiment, the common-mode voltages of TXP and TXN during the operation of the tailing overshoot suppressor can be adjusted by regulating the impedance ratio of voltage generation module 1406 and voltage generation module 1407, thereby adapting to different common-mode voltage requirements of the receiver. This adjustment of the impedance ratio is easier to implement in practice. For example, when the impedance of voltage generation module 1406 is equal to the impedance of voltage generation module 1407, the common-mode voltage during the operation of the tailing overshoot suppressor is equal to V. DD / 2. When the impedance of voltage generation module 1406 is less than the impedance of voltage generation module 1407, the common-mode voltage of the tailing overshoot suppressor is greater than V. DD / 2 and less than V DD When the impedance of voltage generation module 1406 is greater than the impedance of voltage generation module 1407, the common-mode voltage of the tailing overshoot suppressor is greater than 0 and less than V. DD / 2.

[0090] According to one embodiment, Figure 14The tailing overshoot suppressor shown can further reduce the impedance of the discharge path, enhance the tailing overshoot suppression capability, and thus improve the robustness of the communication bus against interference from different wire harness parasites. Furthermore, Figure 14 The tailing overshoot suppressor shown can not only adjust TXP and TXN to common mode voltage during operation, but also adjust the specific value of common mode voltage by adjusting the impedance ratio of voltage generation module 1406 and voltage generation module 1407 to adapt to different common mode voltage requirements.

[0091] According to one embodiment, Figure 11 The fast pull-down path in the illustrated embodiment can also be applied to Figure 14 The specific connection method of the trailing overshoot suppressor shown is as follows: Figure 15 As shown. According to another embodiment, alternatively, a transistor 1509 electrically connected between the gate and source of transistor 1503 and / or a transistor 1510 electrically connected between the gate and source of transistor 1501 may be added. The selection is based on which transistor needs to be turned off more quickly.

[0092] Figure 16 This is a schematic circuit diagram of a high-voltage tailing overshoot suppressor according to an embodiment of this application.

[0093] According to one embodiment, in order to suppress high voltage interference signals on the bus, this application proposes a high voltage tailing overshoot suppressor.

[0094] According to one embodiment, transistors 1601, 1602, 1603, and 1604 are all high-voltage MOSFETs. Specifically, transistors 1601 and 1602 are larger than transistors 1603 and 1604.

[0095] According to one embodiment, transistors 1601, 1602, and 1603 can be high-voltage P-MOSFETs. Transistor 1604 can be a high-voltage N-MOSFET.

[0096] According to one embodiment, the source of transistor 1603 is electrically connected to the source of transistor 1601, the drain of transistor 1603 is electrically connected to current source 1605, and the gate of transistor 1603 is electrically connected to the gate of transistor 1601, i.e., node B. The source of transistor 1604 is electrically connected to current source 1606, the drain of transistor 1604 is electrically connected to the gate of transistor 1601, and the gate of transistor 1604 is configured to receive signal TXS.

[0097] According to one embodiment, the voltage generation module 1607 may be selected as... Figure 9 Any of the implementation methods described herein.

[0098] According to one embodiment, transistors 1601, 1602, 1603, and 1604 are all high-voltage MOSFETs, capable of withstanding high voltage between their source and drain, while the voltage between their source and gate is the same as that of ordinary MOSFETs. When the signal voltage transmitted on the TXP and TXN buses is high, the gate-source voltage of transistors 1601, 1602, and 1603 is high, therefore protection module 1608 is needed to limit their gate-source voltage. Furthermore, voltage generation module 1607 also requires protection module 1608 to limit the voltage across it. The source voltage of transistor 1604 is low, therefore protection module 1608 is not required to limit it.

[0099] According to one embodiment, the protection module 1608 is configured to control the gate-source voltages (V) of transistors 1601, 1602, and 1603. B -V A This is limited to a safe range. According to one embodiment, the impedance of the voltage generation module 1607 is greater than that of the protection module 1608.

[0100] According to one embodiment, the protection module 1608 has a different size design than the voltage generation module 1607. The protection module 1608 is designed to only conduct when the voltage difference between points A and B exceeds the withstand voltage range of the voltage generation module 1607, transistors 1601, 1602, and 1603. Because the protection module 1608 can quickly reduce the voltage between points A and B after conduction, it will not cause device damage. When the signal voltage transmitted on the TXP and TXN buses is high, the voltage between points A and B will exceed the withstand voltage of the voltage generation module 1607, transistors 1601, 1602, and 1603. At this time, the protection module 1608 conducts. The protection module 1608 has voltage stabilization characteristics, enabling it to stabilize the voltage across itself within a safe range. Furthermore, the protection module 1608 is connected in parallel with the voltage generation module 1607, thus maintaining the voltage between points A and B within a safe range. The protection module 1608 is also configured to share a portion of the current to prevent overcurrent caused by the current flowing entirely through the voltage generation module 1607 under high voltage conditions.

[0101] According to one embodiment, when the signal voltage transmitted on the TXP and TXN buses is high, the voltage V at point A is... A and the voltage V at point B B Both are high voltage. Transistor 1604 protects the internal current source 1606 from the high voltage node. Transistor 1603 protects V. DD The current source 1605 at the terminal is not affected by the high-voltage node.

[0102] According to another embodiment, the gate of the P-type transistor 1603 can be controlled by the inverse signal TXS-B of the signal TXS. In this case, the source of transistor 1603 is electrically connected to current source 1605, the drain is electrically connected to point A, and the gate is configured to receive signal TXS-B. (Not shown)

[0103] According to another embodiment, when the gate of the P-type transistor 1603 is controlled by the inverse signal TXS-B of the signal TXS, the source of transistor 1603 is electrically connected to current source 1605, the drain is electrically connected to point A, and the gate is configured to receive signal TXS-B. In this case, the source of transistor 1604 can be electrically connected to point B, the drain to current source 1606, and the gate to point A. (Not shown)

[0104] According to one embodiment, Figure 16 The high-voltage tailing overshoot suppressor shown can still work normally when the TXP and TXN buses are at high voltage, thus preventing high voltage backflow into the internal circuit and causing damage.

[0105] Figure 17 This is a circuit diagram of a protection module according to several embodiments of this application.

[0106] According to one embodiment, the protection module 1608 may include a Zener diode electrically connected between points A and B, such as... Figure 17 As shown.

[0107] According to other embodiments, the protection module 1608 may further include a plurality of diodes electrically connected in series between points A and B in the same manner, such as Figure 17 As shown in the diagram. The anode of the first diode is connected to point A, the cathode of the last diode is connected to point B, and the cathode of each of the remaining diodes is connected to the anode of the next diode. Figure 17 The protection module can include multiple diodes connected in series, such as two, three or other numbers of diodes.

[0108] According to another embodiment, the protection module 1608 may include a P-MOSFET that is electrically connected in series between points A and B with its gate drain shorted, such as... Figure 17 As shown in the diagram, the source of the first P-MOSFET is connected to point A, the drain of the last P-MOSFET is connected to point B, and the drain of each of the remaining P-MOSFETs is connected to the source of the next P-MOSFET. Figure 17 The protection module may include multiple gate-drain shorted P-MOSFETs connected in series, such as two, three or other numbers of gate-drain shorted P-MOSFETs.

[0109] According to another embodiment, the protection module 1608 may include an N-MOSFET that is electrically connected in series between points A and B with its gate drain shorted, such as... Figure 17 As shown in the diagram, the drain of the first N-MOSFET is connected to point A, the source of the last N-MOSFET is connected to point B, and the source of each of the remaining P-MOSFETs is connected to the drain of the next P-MOSFET. Figure 17 The protection module may include multiple gate-drain shorted N-MOSFETs, such as two, three or other numbers of gate-drain shorted N-MOSFETs.

[0110] According to another embodiment, the protection module 1608 may further include a P-MOSFET with its gate drain shorted and an N-MOSFET with its gate drain shorted, which are connected in series between points A and B in the same manner. Figure 17 As shown, a unit is defined by a P-MOSFET and an N-MOSFET connected in series. A specific connection method could include connecting the source of the P-MOSFET in the first unit to point A, connecting the source of the N-MOSFET in the last unit to point B, and connecting the sources of the N-MOSFETs in other units to the source of the P-MOSFET in the next unit. Alternatively, the connection method could also include connecting the source of the N-MOSFET in the first unit to point A, connecting the source of the P-MOSFET in the last unit to point B, and connecting the sources of the P-MOSFETs in other units to the source of the N-MOSFET in the next unit. Figure 17 The protection module can include one or more units.

[0111] According to one embodiment, Figure 16 The high-voltage tailing overshoot suppressor scheme shown can also be applied to... Figure 7 The specific connection method of the trailing overshoot suppressor shown is as follows: Figure 18 As shown.

[0112] According to one embodiment, Figure 11 The fast pull-down path in the illustrated embodiment can also be applied to Figure 16 The high-voltage tailing overshoot suppressor shown has the following specific connection method: Figure 19 As shown.

[0113] According to one embodiment, Figure 16 The high-voltage tailing overshoot suppressor scheme shown can also be applied to... Figure 14 The tailing overshoot suppressor shown has two paths, and the specific connection method is as follows: Figure 20 As shown.

[0114] According to one embodiment, Figure 11 The fast pull-down path in the illustrated embodiment can also be applied to Figure 19 The high-voltage tailing overshoot suppressor shown has the following specific connection method: Figure 21 As shown.

[0115] The tailing overshoot suppressor proposed in this application can short-circuit the TXP and TXN signals of the communication interface, forcibly establishing a discharge path and rapidly discharging residual current within a few microseconds, greatly reducing the amplitude of the tailing overshoot and ensuring accurate and error-free bit transmission at the receiving end. The tailing overshoot suppressor with an added fast pull-down path proposed in this application can achieve rapid shutdown, preventing data transmission in the next stage from being affected. The tailing overshoot suppressor with two paths proposed in this application can further reduce the impedance of the discharge path, enhancing the tailing overshoot suppression capability. Furthermore, the common-mode voltage value can be adjusted by adjusting the impedance ratio of the voltage generation modules in the two paths to adapt to different requirements. The high-voltage resistant tailing overshoot suppressor proposed in this application can still operate normally when the TXP and TXN buses are at high voltage, preventing damage to the internal circuitry caused by high voltage.

[0116] This application also proposes a signal transmitting device, including the aforementioned trailing overshoot suppressor.

[0117] This application also proposes a communication system including the signal transmitting device described above.

[0118] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A suppressor circuit for a transmitter of a differential communication bus system, characterized in that Comprise: a first transistor and a second transistor connected in series with each other, the first transistor and the second transistor being of the same type, having the same size, and having their sources and gates electrically connected to each other, wherein the drain of the first transistor is electrically connected to a first communication bus and the drain of the second transistor is electrically connected to a second communication bus; a first switch having a first end electrically connected to a first power supply and a second end electrically connected to the sources of the first transistor and the second transistor; a second switch having a first end electrically connected to the gates of the first transistor and the second transistor and a second end electrically connected to a second power supply, wherein the voltage of the first power supply is higher or lower than the voltage of the second power supply; a first voltage generating module having a first end electrically connected to the sources of the first transistor and the second transistor and a second end electrically connected to the gates of the first transistor and the second transistor; when the communication ends, the voltage on the first communication bus is a first voltage, the voltage on the second communication bus is a second voltage, there is a voltage difference between the first voltage and the second voltage, the first switch and the second switch are closed under the control of a first control signal, the voltage difference between the first end and the second end of the first voltage generating module causes the first transistor and the second transistor to conduct, when the voltage on the first communication bus and the voltage on the second communication bus both reach a first common mode voltage located between the first voltage and the second voltage, the first common mode voltage is related to the impedance value of the first voltage generating module, and the first switch and the second switch are opened under the control of the first control signal.

2. The suppressor circuit of claim 1, wherein, Further comprising a first current source and a second current source, the first end of the first current source is electrically connected to the first power supply, the second end of the first current source is electrically connected to the first end of the first switch; the first end of the second current source is electrically connected to the second end of the second switch, and the second end of the second current source is electrically connected to the second power supply.

3. The suppressor circuit of claim 1, wherein, Further comprising a third transistor having a drain electrically connected to the sources of the first transistor and the second transistor, a source electrically connected to the gates of the first transistor and the second transistor, and a gate configured to receive the first control signal or a deformation thereof.

4. The suppressor circuit of claim 1, wherein, The first voltage generating module comprises: a resistor electrically connected between the source and the gate of the first transistor; or, a Zener diode having a cathode electrically connected to the second end of the first switch and an anode electrically connected to the first end of the second switch; or, two or more diodes, wherein the anode of the first diode is electrically connected to the second end of the first switch, the cathode of the last diode is electrically connected to the first end of the second switch, and the cathode of each remaining diode is electrically connected to the anode of the next diode; or, two or more gate-drain shorted P-MOSFETs, wherein the source of the first P-MOSFET is electrically connected to the second terminal of the first switch, the drain of the last P-MOSFET is electrically connected to the first terminal of the second switch, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or, two or more gate-drain shorted N-MOSFETs, wherein the drain of the first N-MOSFET is electrically connected to the second terminal of the first switch, the source of the last N-MOSFET is electrically connected to the first terminal of the second switch, and the source of each of the remaining N-MOSFETs is electrically connected to the drain of the next N-MOSFET.

5. The suppressor circuit of any one of claims 1-3, wherein: the first switch comprises a fourth transistor, and the second switch comprises a fifth transistor, wherein the fifth transistor and the fourth transistor are complementary in type; wherein the source of the fourth transistor is electrically connected to the sources of the first transistor and the second transistor, and the drain of the fourth transistor is electrically connected to the first power supply; the drain of the fifth transistor is electrically connected to the gates of the first transistor and the second transistor, the source of the fifth transistor is electrically connected to the second power supply, and the gate of the fifth transistor is configured to receive the first control signal, and the gate of the fourth transistor is electrically connected to the gates of the first transistor and the second transistor; the first transistor, the second transistor, the fourth transistor, and the fifth transistor have a higher voltage withstand than other transistors in the circuit; the suppressor circuit further comprises a first protection module in parallel with the first voltage generation module, configured to control an upper limit of a voltage across the first voltage generation module, wherein the first protection module has a smaller impedance than the first voltage generation module.

6. The suppressor circuit of claim 5, wherein, the first protection module comprises: a Zener diode having its cathode electrically connected to the second terminal of the first switch and its anode electrically connected to the first terminal of the second switch; or two or more diodes, wherein the anode of the first diode is electrically connected to the second terminal of the first switch, the cathode of the last diode is electrically connected to the first terminal of the second switch, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or two or more gate-drain shorted P-MOSFETs, wherein the source of the first P-MOSFET is electrically connected to the second terminal of the first switch, the drain of the last P-MOSFET is electrically connected to the first terminal of the second switch, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or two or more gate-drain shorted N-MOSFETs, wherein the drain of the first N-MOSFET is electrically connected to the second terminal of the first switch, the source of the last N-MOSFET is electrically connected to the first terminal of the second switch, and the source of each of the remaining N-MOSFETs is electrically connected to the drain of the next N-MOSFET. two or more N-MOSFETs with gate-drain short, wherein the drain of the first N-MOSFET is electrically connected to the second terminal of the first switch, the source of the last N-MOSFET is electrically connected to the first terminal of the second switch, and the source of each of the rest of the N-MOSFETs is electrically connected to the drain of the next N-MOSFET; or one or more units in series, each unit comprising a first sub-transistor and a second sub-transistor, the first sub-transistor being a P-MOSFET with gate-drain short, the second sub-transistor being an N-MOSFET with gate-drain short, the gate and the drain of the first sub-transistor and the second sub-transistor being electrically connected together, wherein the source of the P-MOSFET of the first unit is electrically connected to the second terminal of the first switch, the source of the N-MOSFET of the last unit is electrically connected to the first terminal of the second switch, and the source of the N-MOSFET of each of the rest of the units is electrically connected to the source of the P-MOSFET of the next unit.

7. A suppressor circuit for a transmitting end of a differential communication bus system, characterized in that comprising: a sixth transistor and a seventh transistor in series with each other, the sixth transistor and the seventh transistor being of the same type and of the same size, and the source of each being electrically connected to each other, and the gate of each being electrically connected to each other, wherein the drain of the sixth transistor is electrically connected to a third communication bus, and the drain of the seventh transistor is electrically connected to a fourth communication bus; an eighth transistor and a ninth transistor in series with each other, the eighth transistor and the ninth transistor being of the same type and of the same size, and the source of each being electrically connected to each other, and the gate of each being electrically connected to each other, wherein the drain of the eighth transistor is electrically connected to the third communication bus, and the drain of the ninth transistor is electrically connected to the fourth communication bus; a third switch, a first terminal of which is electrically connected to a third power supply, and a second terminal of which is electrically connected to the gate of the sixth transistor and the seventh transistor; a fourth switch, a first terminal of which is electrically connected to the gate of the eighth transistor and the ninth transistor, and a second terminal of which is electrically connected to a fourth power supply, wherein the voltage of the third power supply is higher or lower than the voltage of the fourth power supply; a second voltage generating module, a first terminal of which is electrically connected to the gate of the sixth transistor and the seventh transistor, and a second terminal of which is electrically connected to the source of the sixth transistor and the seventh transistor; a third voltage generating module, a first terminal of which is electrically connected to the source of the eighth transistor and the ninth transistor, and a second terminal of which is electrically connected to the gate of the eighth transistor and the ninth transistor; When the communication ends, the voltage on the third communication bus is a third voltage, the voltage on the fourth communication bus is a fourth voltage, there is a voltage difference between the third voltage and the fourth voltage, the third switch and the fourth switch are closed under the control of a second control signal, and the voltage difference between the first end and the second end of the second voltage generation module causes the sixth transistor and the seventh transistor to be turned on, and the voltage difference between the first end and the second end of the third voltage generation module causes the eighth transistor and the ninth transistor to be turned on; when the voltage on the third communication bus and the voltage on the fourth communication bus both reach a second common-mode voltage located between the third voltage and the fourth voltage, the second common-mode voltage is related to the impedance ratio of the second voltage generation module and the third voltage generation module, and the third switch and the fourth switch are opened under the control of the second control signal.

8. The suppressor circuit of claim 7, wherein, Further comprising a third current source and a fourth current source, a first end of the third current source is electrically connected to the third power supply, and a second end of the third current source is electrically connected to a first end of the third switch; a first end of the fourth current source is electrically connected to a second end of the fourth switch, and a second end of the fourth current source is electrically connected to the fourth power supply.

9. The suppressor circuit of claim 7, wherein, Further comprising a tenth transistor and / or an eleventh transistor, a drain of the tenth transistor is electrically connected to a source of the sixth transistor and the seventh transistor, a source of the tenth transistor is electrically connected to a gate of the sixth transistor and the seventh transistor, and a gate of the tenth transistor is configured to receive the second control signal; a drain of the eleventh transistor is electrically connected to a source of the eighth transistor and the ninth transistor, a source of the eleventh transistor is electrically connected to a gate of the eighth transistor and the ninth transistor, and a gate of the eleventh transistor is configured to receive a deformation of the second control signal.

10. The suppressor circuit of claim 7, wherein, The second voltage generation module comprises: a resistor electrically connected between the source and the gate of the sixth transistor; or, a Zener diode, a cathode of which is electrically connected to the gates of the sixth transistor and the seventh transistor, and an anode of which is electrically connected to the sources of the sixth transistor and the seventh transistor; or, two or more diodes, an anode of a first diode of which is electrically connected to the gates of the sixth transistor and the seventh transistor, a cathode of a last diode of which is electrically connected to the sources of the sixth transistor and the seventh transistor, and a cathode of each remaining diode of which is electrically connected to an anode of a next diode; or, two or more P-MOSFETs with gate-drain short, a source of a first P-MOSFET of which is electrically connected to the gates of the sixth transistor and the seventh transistor, a drain of a last P-MOSFET of which is electrically connected to the sources of the sixth transistor and the seventh transistor, and a drain of each remaining P-MOSFET of which is electrically connected to a source of a next P-MOSFET; or two or more N-MOSFETs with gate-drain short, wherein the drain of the first N-MOSFET is electrically connected to the gates of the sixth transistor and the seventh transistor, the source of the last N-MOSFET is electrically connected to the gates of the sixth transistor and the seventh transistor, and the source of each of the rest of the N-MOSFETs is electrically connected to the drain of the next N-MOSFET.

11. The suppressor circuit of claim 7, wherein, the third voltage generating module comprises: a resistor electrically connected between the source and the gate of the eighth transistor; or, a Zener diode, the cathode of which is electrically connected to the sources of the eighth transistor and the ninth transistor, and the anode of which is electrically connected to the gates of the eighth transistor and the ninth transistor; or, two or more diodes, the anode of the first diode is electrically connected to the sources of the eighth transistor and the ninth transistor, the cathode of the last diode is electrically connected to the gates of the eighth transistor and the ninth transistor, and the cathode of each of the rest of the diodes is electrically connected to the anode of the next diode; or, two or more P-MOSFETs with gate-drain short, wherein the source of the first P-MOSFET is electrically connected to the sources of the eighth transistor and the ninth transistor, the drain of the last P-MOSFET is electrically connected to the gates of the eighth transistor and the ninth transistor, and the drain of each of the rest of the P-MOSFETs is electrically connected to the source of the next P-MOSFET; or, two or more N-MOSFETs with gate-drain short, wherein the drain of the first N-MOSFET is electrically connected to the sources of the eighth transistor and the ninth transistor, the source of the last N-MOSFET is electrically connected to the gates of the eighth transistor and the ninth transistor, and the source of each of the rest of the N-MOSFETs is electrically connected to the gate of the next N-MOSFET.

12. The suppressor circuit according to any one of claims 7-9, wherein, the third switch comprises a twelfth transistor, and the fourth switch comprises a thirteenth transistor, wherein the twelfth transistor and the thirteenth transistor are complementary in type; wherein the drain of the twelfth transistor is electrically connected to the gates of the sixth transistor and the seventh transistor, and the source of the twelfth transistor is electrically connected to the third power supply; the drain of the thirteenth transistor is electrically connected to the gates of the eighth transistor and the ninth transistor, the source of the thirteenth transistor is electrically connected to the fourth power supply, and the gate of the thirteenth transistor is configured to receive the second control signal, and the gate of the twelfth transistor is configured to receive a variation of the second control signal; the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the twelfth transistor and the thirteenth transistor have a higher withstand voltage than other transistors in the circuit; The suppressor circuit further comprises a second protection module connected in parallel with the second voltage generation module, configured to control the upper limit of the voltage across the second voltage generation module, wherein the impedance of the second protection module is smaller than the impedance of the second voltage generation module; The suppressor circuit further comprises a third protection module connected in parallel with the third voltage generation module, configured to control the upper limit of the voltage across the third voltage generation module, wherein the impedance of the third protection module is smaller than the impedance of the third voltage generation module.

13. The suppressor circuit of claim 12, wherein, The second protection module comprises: a Zener diode, the cathode of which is electrically connected to the gate of the sixth transistor and the seventh transistor, and the anode of which is electrically connected to the source of the sixth transistor and the seventh transistor; or, two or more diodes, the anode of the first diode is electrically connected to the gate of the sixth transistor and the seventh transistor, the cathode of the last diode is electrically connected to the source of the sixth transistor and the seventh transistor, and the cathode of each of the remaining diodes is electrically connected to the anode of the next diode; or, two or more gate-drain shorted P-MOSFETs, the source of the first P-MOSFET is electrically connected to the gate of the sixth transistor and the seventh transistor, the last P-MOSFET is electrically connected to the source of the sixth transistor and the seventh transistor, and the drain of each of the remaining P-MOSFETs is electrically connected to the source of the next P-MOSFET; or, two or more gate-drain shorted N-MOSFETs, the drain of the first N-MOSFET is electrically connected to the gate of the sixth transistor and the seventh transistor, the source of the last N-MOSFET is electrically connected to the source of the sixth transistor and the seventh transistor, and the source of each of the remaining N-MOSFETs is electrically connected to the drain of the next N-MOSFET; or, one or more series-connected units, each unit comprising a third sub-transistor and a fourth sub-transistor, the third sub-transistor being a gate-drain shorted P-MOSFET, and the fourth sub-transistor being a gate-drain shorted N-MOSFET, the gate and the drain of the third sub-transistor and the fourth sub-transistor being electrically connected together, wherein the source of the P-MOSFET of the first unit is electrically connected to the gate of the sixth transistor and the seventh transistor, the source of the N-MOSFET of the last unit is electrically connected to the source of the sixth transistor and the seventh transistor, and the source of the N-MOSFET of each of the remaining units is electrically connected to the source of the P-MOSFET of the next unit.

14. The suppressor circuit of claim 12, wherein, The third protection module comprises: a Zener diode, the cathode of which is electrically connected to the source of the eighth transistor and the ninth transistor, and the anode of which is electrically connected to the gate of the eighth transistor and the ninth transistor; or, two or more diodes, an anode of a first diode electrically connected to the source of the eighth transistor and the ninth transistor, a cathode of a last diode electrically connected to the gate of the eighth transistor and the ninth transistor, and a cathode of each of the rest electrically connected to an anode of the next diode; or two or more gate-drain shorted P-MOSFETs, a source of a first P-MOSFET electrically connected to the source of the eighth transistor and the ninth transistor, a drain of a last P-MOSFET electrically connected to the gate of the eighth transistor and the ninth transistor, and a drain of each of the rest electrically connected to a source of the next P-MOSFET; or two or more gate-drain shorted N-MOSFETs, a drain of a first N-MOSFET electrically connected to the source of the eighth transistor and the ninth transistor, a source of a last N-MOSFET electrically connected to the gate of the eighth transistor and the ninth transistor, and a source of each of the rest electrically connected to a drain of the next N-MOSFET; or one or more series connected cells, each cell comprising a fifth sub-transistor and a sixth sub-transistor, the fifth sub-transistor being a gate-drain shorted P-MOSFET, the sixth sub-transistor being a gate-drain shorted N-MOSFET, the gates and the drains of the fifth sub-transistor and the sixth sub-transistor electrically connected together, wherein a source of a P-MOSFET of a first cell is electrically connected to the source of the eighth transistor and the ninth transistor, a source of a N-MOSFET of a last cell is electrically connected to the gate of the eighth transistor and the ninth transistor, and a source of a N-MOSFET of each of the rest is electrically connected to a source of a P-MOSFET of the next cell.

15. A signal transmitting device, characterized in that, A transmitter circuit comprising a transmitter and a suppressor circuit as claimed in any of claims 1-14.

16. A communication system, characterized by A signal receiving apparatus comprising a signal receiving device, an isolation network, and a signal transmitting device as claimed in claim 15. A signal receiving apparatus comprising a signal receiving device, an isolation network, and a signal transmitting device as claimed in claim 15.

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