Time series generation device

Abstract

The invention relates to a time sequence generation device. The present specification relates to an apparatus comprising a ring oscillator comprising a plurality of gates, each gate transmitting a fast clock signal. The first shift register includes successive first flip-flops, each of which is synchronized with a same first clock signal corresponding to one of the fast clock signals. The first shift register is looped back on itself and implements a second oscillator in which each first flip-flop transmits a slow clock signal. The second shift register includes successive second flip-flops, each of which is synchronized with a same second clock signal corresponding to one of the slow clock signals.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority benefit of French patent application No. 24 / 04687 entitled "Time sequence generation device", filed on May 3, 2024, which is hereby incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic circuits for generating digital time signals. Background Technology

[0004] Many types of devices, such as memory or arithmetic units, require digital signals with a given time sequence to control the actions to be performed by these devices at specific times.

[0005] Those skilled in the art know that time series with timescales of approximately several hundred picoseconds can be generated using microprocessors operating at frequencies of several GHz. Such microprocessors typically employ high-frequency phase-locked loop (PLL) systems, implying the use of advanced technology and high manufacturing costs and power consumption. Furthermore, it is currently difficult to generate such tunable time series without introducing significant development complexity.

[0006] To generate such an adjustable time series, documents FR 3133458, US 2023291396 and CN116760392 describe an apparatus that includes a ring oscillator and a shift register synchronized with a clock signal transmitted to one of the logic gates of the ring oscillator.

[0007] Figure 1 For the above documents Figure 1 A copy. Figure 1 An example of a time series edge generation circuit 100 is schematically shown.

[0008] according to Figure 1 For example, the time series generation circuit 100 includes a ring oscillator 102. The ring oscillator 102 is formed by a plurality of logic gates 101, 103, 105, 107, and 109, which are series-coupled and coupled to the output of logic gate 109, whose output is coupled to the input of logic gate 101. The respective output nodes of these logic gates are designated CK1, CK2, CK3, CKN-1, and CKN. Using the number N (which represents the number of logic gates in the oscillator), those skilled in the art will be able to adjust its operation according to an appropriate number of gates. Figure 1In the example of Fig. 1, the logic gates are for example inverters. However, the oscillator 102 can be formed based on other types of logic gates, such as for example NOR gates or NAND gates.

[0009] The oscillator 102 is for example implemented by a loop of an odd number of inverting logic gates. Although in the example of Fig. 1 five gates are illustrated, the oscillator can for example be implemented by three logic gates, or also by an odd number of logic gates greater than five. Each logic gate delivers an output clock signal: CK1, CK2, CK3, CKN-1 and CKN. Figure 1

[0010] The output clock signals CK1 to CKN have edges that are presented with a time shift relative to each other, and by selecting one of these signals, an edge with a given time shift can thus be generated. For example, with signal CK1 as first signal, signal CK3 is delayed relative to signal CK1, signal CKN (i.e. signal CK5 in the example of Fig. 1) is delayed relative to signal CK3, signal CK2 is delayed relative to signal CKN, and signal CKN-1 (i.e. signal CK4 in the example of Fig. 1) is delayed relative to signal CK2. Figure 1 Figure 1

[0011] For example, the clock signals CK1, CK2, CK3, CKN-1 and CKN are coupled to inputs of a multiplexer 104, which is configured to select one or more signals from among these clock signals. The multiplexer 104 is controlled by a selection signal SEL1 generated by a control unit CMD111. The output of the multiplexer 104 feeds a clock signal CK(i) selected from among the clock signals CK1 to CKN to a clock signal input of a first shift register 110, where i is an integer index ranging from 0 to N-1. In other words, the shift register 110 is synchronized with one of the signals CK(i).

[0012] According to the example of Fig. 1, the first shift register 110 comprises three flip-flops SR1_FLIP_FLOP_1, SR1_FLIP_FLOP_2, SR1_FLIP_FLOP_3 coupled in series. However, depending on the desired time shift, it is conceivable that the shift register 110 comprises a single flip-flop or two flip-flops, or a number of flip-flops coupled in series greater than three. In the example of Fig. 1, the first shift register 110 is implemented by three flip-flops coupled in series, and the second shift register 112 is implemented by three flip-flops coupled in series. Figure 1 Figure 1 ​​​​In the examples, the flip-flop is, for example, type D. The remainder of this disclosure describes examples of flip-flops enabled by a rising edge. However, those skilled in the art will be able to adapt the teachings of this disclosure to flip-flops enabled by a falling edge. The term "series coupling" means that the output of the flip-flop (denoted as Q) is coupled to the data input D of the next flip-flop in the series. Those skilled in the art will also be able to understand this by considering the output of the flip-flop. To adjust the circuit, the output of the flip-flop This corresponds to the two's complement of the Q output of the flip-flop. The data input D of the first flip-flop SR1_FLIP_FLOP_1 in the series of flip-flops is, for example, powered by a voltage in a high state and marked as "1".

[0013] The clock signal input of the first shift register 110 is, for example, coupled to the clock input CK of each of the series-connected flip-flops.

[0014] For example, the output signal of each of the flip-flops is coupled to multiplexer 120, which enables the selection of one of the Q output signals of the flip-flops to form the output signal SR1_OUTPUT of shift register 110. Figure 1 In the example, the rising edge of the output signal selected by multiplexer 120 forms the rising edge of the time series to be obtained. Multiplexer 120 is controlled, for example, by signal SEL2 generated by control unit CMD. This makes it possible to generate a time series that is easily adjustable. In other embodiments, multiplexer 120 is omitted.

[0015] In some embodiments, the output signal of the first flip-flop (labeled S1FP1Q) points to the secondary circuit 122.

[0016] For example, the reset input (RESET) (labeled R) of each of the triggers SR1_FLIP_FLOP_1, SR1_FLIP_FLOP_2, and SR1_FLIP_FLOP_3 is controlled by the control unit CMD. The control unit CMD is configured, for example, to control these reset inputs such that the triggers are reset before the start of the time series generation cycle.

[0017] use Figure 1The multiplexer 104 of the circuit selects one of the clock signals to generate an edge within a time range equal to or close to the edge of the desired time series. Additionally, the edge generated when the multiplexer 104 selects the desired clock signal can potentially be offset by a number of clock cycles, which is at most equal to the number of flip-flops in the first shift register 110. Therefore, the number of flip-flops will be determined based on the duration of the desired time series. In some embodiments, within the device, multiple time series edge generation circuits 100, for example, each implement a number of flip-flops in the first register, which is the same, or different for at least some circuits relative to others, with the number of flip-flops selected, for example, to be equal to the maximum edge offset. The multiplexer 104 and / or 120 make it possible to program this offset to generate time series of different durations.

[0018] Figure 1 Circuit 100 enables the generation of time series with edges using fewer flip-flops than other solutions. The power-to-area ratio can be reduced by more than half compared to existing solutions. Furthermore, Figure 1 The example demonstrates that the complexity of the design does not increase exponentially with the duration of the time series to be generated. In fact, the generation of time series with additional offsets can be achieved by adding an additional circuit 100 with a certain number of triggers selected according to the desired time shift.

[0019] More specifically, in Figure 1 In device 100, where N equals 5, signals CK1 to CKN are renamed according to their time-shifted order. Therefore, CK(0) = CK1, CK(1) = CK3, CK(2) = CK5, CK(3) = CK2 and CK(4) = CK4. Thus, the delay between the edge of signal CK(i) and the corresponding edge (time-shifted) of the next signal CK(i+1) is equal to T / N, where T is the period of oscillator 102. Taking time t0 corresponding to, for example, the edge (e.g., rising edge) of signal CK(0) as a reference, the corresponding edge of signal CK(1) is delayed by T / N seconds relative to time t0, the corresponding edge of signal CK(2) is delayed by 2*T / N seconds relative to time t0, the corresponding edge of signal CK(3) is delayed by 3*T / N seconds relative to time t0, and the corresponding edge of signal CK(4) is delayed by 4*T / N seconds relative to time t0.

[0020] Thus, with respect to, for example, an edge (e.g., a rising edge) corresponding to the signal CK(0), and, for example, a time t0 corresponding to a reset of the Q output of the register 110, an edge (e.g., a rising edge) on the Q output of the flip-flop SR1 FLIP FLOP 1 is shifted by i*T / N when the shift register 110 is synchronized with the signal CK(i) selected by the multiplexer 104, with i ranging from 0 to N-1.

[0021] Moreover, with respect to the time t0, a corresponding edge (e.g., a rising edge) on the Q output of the flip-flop SR1 FLIP FLOP2 is shifted by one period T with respect to the edge on the Q output of the flip-flop SR1 FLIP FLOP1, and a corresponding edge (e.g., a rising edge) on the Q output of the flip-flop SR1 FLIP FLOP3 is shifted by two periods T with respect to the edge on the Q output of the flip-flop SR1 FLIP FLOP1.

[0022] Thus, Figure 1 The device 100 of the makes it possible to generate an edge having a delay with respect to the time t0 which is at most equal to (N-1)*T / N + (P-1)*T, with P being the number of flip-flops of the register 110, in Figure 1 In the example of the device 100 of the, P is equal to 3. The step T / N represents the time precision of such a delay between the time t0 and the generated edge.

[0023] As an example, for an oscillator 102 operating at a frequency of 800 MHz and comprising N = 5 inverters in series, and for a shift register 110 comprising M = 3 flip-flops, it is possible to generate a given delay between the time t0 and the output edge of the multiplexer 120 having a time resolution equal to 250 ps. Moreover, for this example, the delay between the time t0 and the output edge of the multiplexer 120 is at most equal to 4*250.10 -12 + 2*1.25.10 -9 = 3.5 ns.

[0024] Figure 1 The device of the makes it possible to generate an edge having a delay with respect to the time t0 which is at most equal to (N-1)*T / N + (P-1)*T, with P being the number of flip-flops of the register 110, in

[0025] It is conceivable to modify the frequency of the oscillator 102. However, this is difficult to implement, especially taking into account the frequency stability of the oscillator 102 with respect to temperature variations. Moreover, reducing the frequency of the oscillator 102 to reduce the number of flip-flops in the register 110 means reducing the time precision with which the delays can be generated by the device 100, because the adjustment step of the delays is equal to T / N, where T is the period of the oscillator 102. Finally, a device 100 in which the frequency of the oscillator 102 is modifiable would be complex to implement. SUMMARY

[0026] There is a need for a circuit for generating a time sequence, preferably easily adjustable, which can be manufactured at moderate cost while limiting power consumption and circuit surface area.

[0027] The embodiments overcome all or part of the shortcomings of known time sequence generation circuits.

[0028] The embodiments provide a device comprising:

[0029] a ring oscillator comprising a plurality of inverting logic gates coupled one after the other and each delivering a fast clock signal;

[0030] a first shift register comprising successive first flip-flops, preferably successive first flip-flops of the D type, each first flip-flop being synchronized with a same first clock signal corresponding to one of the fast clock signals whose frequency is divided by a positive integer M, the first shift register being looped back on itself to implement a second oscillator in which each first flip-flop delivers a slow clock signal; and

[0031] a second shift register comprising a single second flip-flop or successive second flip-flops, each second flip-flop being synchronized with a same second clock signal corresponding to one of the slow clock signals.

[0032] According to an embodiment, the data input of a first one of the successive first flip-flops receives a signal determined at least in part by a first binary signal equal to a logical OR between a logical NOT of a logical OR between the output of a last one of the successive first flip-flops and the output of at least two last ones of the successive first flip-flops.

[0033] According to an embodiment, the signal received by the data input of the first one of the first flip-flops is equal to a logical OR between a first signal and a NOT of an enabling signal, or is equal to a logical AND between the first signal and the enabling signal.

[0034] According to an embodiment, the fast clock signals are offset in time with respect to each other.

[0035] According to an embodiment, the slow clock signals are time-shifted relative to each other.

[0036] According to an embodiment, the apparatus comprises a first selection circuit configured to select the first clock signal from among the fast clock signal whose frequency is divided by the integer M and at least another one of the fast clock signals.

[0037] According to an embodiment, the first selection circuit is configured to deliver the first clock signal to the synchronous input of each of said first flip-flops.

[0038] According to an embodiment, the apparatus comprises a second selection circuit configured to select the second clock signal from among all or a part of the slow clock signals.

[0039] According to an embodiment, the second selection circuit is configured to deliver the second clock signal to the synchronous input of each of said second flip-flops.

[0040] According to an embodiment, the apparatus comprises a third shift register comprising a single third flip-flop or successive third flip-flops, preferably a single D-type third flip-flop or successive D-type third flip-flops, each of which is synchronized with the same third clock signal corresponding to one of the fast clock signals.

[0041] According to an embodiment, the apparatus comprises a third selection circuit configured to receive all or a part of the fast clock signals and configured to deliver the third clock signal to the synchronous input of each third flip-flop.

[0042] According to an embodiment, the data input of the third shift register receives a signal determined by the output of the second shift register.

[0043] According to an embodiment, the second shift register comprises said successive second flip-flops, and the apparatus comprises a fourth selection circuit configured to select the output signal of one of said second flip-flops from among all or a part of the output signals of said second flip-flops, and configured to deliver the selected signal to the data input of the third shift register.

[0044] According to an embodiment, the output of the third register is the output of the single third flip-flop, or the output of one of said successive third flip-flops, for example selected by a selection circuit from among all or a part of the outputs of said successive third flip-flops.

[0045] According to an embodiment, the apparatus comprises a circuit configured to:

[0046] controlling the setting of the flip-flop; and / or

[0047] controlling the enabling of the first oscillator. BRIEF DESCRIPTION OF DRAWINGS

[0048] The above features and advantages and other features and advantages are more fully described in the disclosure of specific embodiments, made with reference to the drawings, in which:

[0049] The above-described Figure 1 is a copy of the Figure 1 above-mentioned patent application; and

[0050] Figure 2 An example illustrating an embodiment of a time series generation apparatus is shown. DETAILED DESCRIPTION

[0051] Identical features in the various figures are denoted by identical reference numerals. In particular, structural and / or functional features common among the various embodiments can have identical reference numerals and can be deployed with identical structural, dimensional, and material properties.

[0052] For the sake of clarity, only those steps and elements that are helpful in understanding the embodiments are shown and described in detail.

[0053] Unless otherwise stated, when two elements are referred to as being connected together, this means that they are directly connected without any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0054] In the following description, when referring to absolute position qualifiers such as "front", "back / backward", "top", "bottom", "left", "right", or relative position qualifiers such as "top", "bottom", "upper", "lower", or orientation qualifiers such as "horizontal", "vertical", etc., unless otherwise indicated, these refer to the orientation of the drawing or the orientation in the normal position of use.

[0055] Unless otherwise indicated, the expressions "about", "approximately", "substantially", and "on the order of" mean within a positive or negative ten percent or ten degrees, preferably within a positive or negative five percent or five degrees.

[0056] To overcome Figure 1 the drawbacks of time series generation circuits of that type, there is provided a circuit for generating a time series, for example, for generating a delay between an initial time of the sequence and a first edge of the time series. The provided circuit comprises a similar circuit as Figure 1the device 100 in the figure. The first shift register is synchronized with a fast clock signal delivered by one of the inverters of the ring oscillator. The second shift register is synchronized with a slower clock signal with respect to the fast clock signal, the slow clock signal being delivered by one of the flip-flops of the first shift register.

[0057] Preferably, the third shift register has a data input coupled to the output of the second shift register and is synchronized with a fast clock signal delivered by one of the inverters of the ring oscillator.

[0058] In such a device, the fast clock signal delivered by the inverters of the ring oscillator allows a delay adjustment precision equal to Tf / Nf, where Tf is the period of the ring oscillator and Nf is the number of inverters in series in the ring oscillator. Moreover, the first shift register configured as a ring oscillator generates a slow clock signal with a period equal to Ts=Ns*Tf, where Ns is the number of flip-flops in series in the first shift register. Thus, the second shift register makes it possible to generate a delay with a maximum value equal to (Nd1-1)*Ts+(Ns-1)*(Ts / Ns), where Nd1 is the number of flip-flops of the second shift register, with a time precision equal to Ts / Ns, and thus equal to Tf.

[0059] Preferably, when the device comprises a third shift register, the device makes it possible to generate a delay corresponding to the sum of a first delay provided by the second shift register and a second delay provided by the third shift register and starting from the end of the first delay. In this case, the precision of the delay generated by the device is equal to Tf / Nf. Moreover, the delay generated by the device has a maximum value at least equal to (Nd1-1)*Ts+(Ns-1)*(Ts / Ns)+(Nd2-1)*Tf, where Nd2 is the number of flip-flops in the third shift register.

[0060] Figure 2 An example of such a time sequence generation circuit or device 200 is shown.

[0061] The device 200 comprises a ring oscillator RO. The ring oscillator RO is formed of a plurality of inverters Ii with i being an index from 1 to Nf and Nf being an odd number greater than or equal to 3. The inverters Ii are coupled in series, or in other words one after the other, for example in Figure 2 I1, I2, I3,..., INf-1 and INf in the figure. The first shift register is synchronized with a fast clock signal delivered by one of the inverters of the ring oscillator. The second shift register is synchronized with a slower clock signal with respect to the fast clock signal, the slow clock signal being delivered by one of the flip-flops of the first shift register. Figure 2the outputs of the Nf gates INi are coupled (e.g., connected) to the inputs of the Nf gates Ii. In other words, the inputs of the first Nf gates Ii in the series connection of Nf gates Ii are coupled (e.g., connected) to the outputs of the last Nf gates INi in the series connection of Nf gates Ii.

[0062] For example, in the example of Fig. 1, the outputs of the Nf gates INi are coupled (e.g., connected) to the inputs of the Nf gates Ii. In other words, the inputs of the first Nf gates Ii in the series connection of Nf gates Ii are coupled (e.g., connected) to the outputs of the last Nf gates INi in the series connection of Nf gates Ii. Figure 2 In the example of Fig. 1, the output of the gate INf is coupled to the input of the gate Ii by a circuit 202 configured to selectively enable and disable the oscillator RO depending on the state of a control signal ENRO. For example, the circuit 202 comprises a transistor coupling the output of the gate INf connected to the input of the gate Ii to the ground GND, the transistor being controlled by the signal ENRO. As an example, the signal ENRO is delivered by a control circuit 204, for example delivered by the control circuit 204 in the form of a block CMD. Figure 2 In the example of Fig. 1, the output of the gate INf is coupled to the input of the gate Ii by a circuit 202 configured to selectively enable and disable the oscillator RO depending on the state of a control signal ENRO. For example, the circuit 202 comprises a transistor coupling the output of the gate INf connected to the input of the gate Ii to the ground GND, the transistor being controlled by the signal ENRO. As an example, the signal ENRO is delivered by a control circuit 204, for example delivered by the control circuit 204 in the form of a block CMD.

[0063] In another example (not shown), the circuit 202 is omitted. Then, for example, the output of the gate INf is connected to the input of the gate In1.

[0064] The logic gates Ii deliver respective output signals CKfi (CKf1, CKf2, CKf3,..., CKfNf-1, CKfNf in the example of Fig. 1). The signals CKfi are fast clock signals. Like the clock signals CK1 to CKN of Fig. 1, the fast clock signals CKfi have edges exhibiting a time shift with respect to each other. In the example of Fig. 1, the considered edges are rising edges. The skilled person will be able to adapt the description to the case where the considered edges are falling edges. Figure 2 Figure 1 Like the clock signals CK1 to CKN of Fig. 1, the fast clock signals CKfi have edges exhibiting a time shift with respect to each other. In the example of Fig. 1, the considered edges are rising edges. The skilled person will be able to adapt the description to the case where the considered edges are falling edges. Figure 2 In the example of Fig. 1, the logic gates Ii are inverters. However, the oscillator RO can be formed based on other types of logic gates Ii, such as NOR-type gates Ii or NAND-type gates Ii.

[0065] Figure 2 The device 200 further comprises a shift register OSC configured as an oscillator. The oscillator OCS comprises a number Ns of D flip-flops FFsj (FFs1, FFs2, FFsNs-1 and FFsNs in the example of Fig. 1), where j is an integer ranging from 1 to Nf, and Nf is an integer greater than or equal to 1, for example greater than or equal to 3. The flip-flops FFsj are coupled in series, i.e., one after the other, for example in an order increasing with the index j.

[0066] The term “coupled in series” means that the output Q of a flip-flop is coupled to the data input (labeled D) of the next flip-flop in the series. In the example of Fig. 1, the output Q of the flip-flop FFs1 is coupled to the data input D of the flip-flop FFs2, the output Q of the flip-flop FFs2 is coupled to the data input D of the flip-flop FFsNs-1, and the output Q of the flip-flop FFsNs-1 is coupled to the data input D of the flip-flop FFsNs. Figure 2 Figure 2 The term “coupled in series” means that the output Q of a flip-flop is coupled to the data input (labeled D) of the next flip-flop in the series. In the example of Fig. 1, the output Q of the flip-flop FFs1 is coupled to the data input D of the flip-flop FFs2, the output Q of the flip-flop FFs2 is coupled to the data input D of the flip-flop FFsNs-1, and the output Q of the flip-flop FFsNs-1 is coupled to the data input D of the flip-flop FFsNs.

[0067] The term “coupled in series” means that the output Q of a flip-flop is coupled to the data input (labeled D) of the next flip-flop in the series. In the example of Fig. 1, the output Q of the flip-flop FFs1 is coupled to the data input D of the flip-flop FFs2, the output Q of the flip-flop FFs2 is coupled to the data input D of the flip-flop FFsNs-1, and the output Q of the flip-flop FFsNs-1 is coupled to the data input D of the flip-flop FFsNs.​​​Figure 2 In one example, the Q output of the flip-flop is connected to the D data input of the next flip-flop in series. In another example, the Q output of each flip-flop is coupled to the D input of the next flip-flop via a circuit that introduces a delay to avoid metastability issues in the register OSC.

[0068] Each flip-flop FFsj transmits the signal CKsj to its Q output. Figure 2 (CKs1, CKs2, ..., CKsNs-2, CKsNS-1 and CKsNs).

[0069] Each flip-flop FFsj has a synchronous input that receives the same clock signal CK1. Figure 2 The symbol is CK. For example, the register OSC has a synchronization input CKOSC, which is configured to receive the signal CK1, and the input CKOSC is coupled (preferably connected) to the CK input of each flip-flop FFsj. In the remainder of this disclosure, examples of flip-flops enabled by a rising edge are described. However, those skilled in the art will be able to adapt the teachings of this disclosure to flip-flops enabled by a falling edge. Those skilled in the art will also be able to consider the flip-flops… The output is used to adjust the circuit, the trigger. The output corresponds to the two's complement of the Q output of the flip-flop.

[0070] According to the embodiment, signal CK1 corresponds to one of the fast clock signals CKfi.

[0071] For example, device 200 includes a selection circuit MUX1, such as a multiplexer, configured to receive all or part of the signal CKfi, and configured to select signal CK1 from the received signal CKfi based on control signal SEL1. As an example, signal SEL1 is transmitted by control circuitry (e.g., circuit 204).

[0072] As an alternative example, circuit MUX1 is omitted, and the CKOSC input of oscillator OSC is connected to the output of gate Ii, which transmits the signal CKfi with its corresponding signal CK1.

[0073] Preferably, signal CK1 corresponds to signal CKf1.

[0074] Furthermore, the shift register OCS loops back on itself, enabling it to operate as an oscillator. More specifically, the register OSC is configured to simulate operation at a frequency Fs = 1 / (Tf*Ns), that is, an oscillator operating at a frequency Ns slower than the frequency of oscillator RO. Therefore, the signal CKsj is a clock signal slower than the fast clock signal CKfi.

[0075] In an example not shown, the Q output of flip-flop FFsNs is coupled to the D input of flip-flop FFs1 via an inverter. For example, the inverter receives the signal CKsNs and transmits the signal D1, which is applied (i.e. transmitted) to the D input of flip-flop FFs1.

[0076] exist Figure 2 In the example, the Q output of flip-flop FFsNs is fed to combinational logic circuit C1, which is configured to feed signal D1 to the D input of flip-flop FFs1.

[0077] More specifically, in Figure 2 In the example, circuit C1 receives the signal ENOSC, which enables selective enabling and disabling of the oscillator OSC, and all or part of the signal CKsj.

[0078] For example, when the high levels of signals CKsj and ENOSC correspond to logic "1", signal D1 is equal to the logical OR of the following:

[0079] -Signal CKsNs;

[0080] - The logical OR of the signals CKsj of the last Ns-K flip-flops in the series connection, and their logical NOT (or two's complement); and

[0081] - When the signal ENOSC is configured to set all signals CKsj to "1" if ENOSC is in a low state corresponding to logic "0", the inverse (or complement) of the signal ENOSC is used.

[0082] As another example, when the high levels of signals Cksj and ENOSC correspond to logic "1", signal D1 is equal to the logical AND of the following:

[0083] - Signal ENOSC; and

[0084] - Logical OR between the following items:

[0085] *Signal CKsNs; and

[0086] * The logical OR of the signal CKsj of the last Ns-K flip-flops in the series, and its logical NOT (or two's complement). In this example, the signal ENOSC is configured to set all logic signals CKsj to "1" if ENOSC is in a low state corresponding to logic "0".

[0087] In another example, circuit C1 does not receive the signal ENOSC, and when the high level of signal CKsj corresponds to logic "1", signal D1 is equal to the logical OR of the following:

[0088] -Signal CKsNs;

[0089] - the logical NOT (or the complement) of the logical OR of the signals CKsj of the last Ns-K flip-flops in series.

[0090] In the last three examples above, K is an integer in the range from 1 to Ns-1 and the signals CKsj have the same duty cycle equal to K / Ns.

[0091] Similarly to the fast clock signals CKj, the slow clock signals CKsj have edges that are offset in time, for example Figure 2 the rising edge in the example of Fig. 1. The offset between the two corresponding edges of two respective signals CKsj and CKj+1 is equal to the period of the signal CK1, i.e. the period Tf of the oscillator RO. For example, the corresponding edge of the signal CKs2 is delayed by one period of the signal CK1 compared to the edge of the signal CKs1, the corresponding edge of the signal CKs3 is delayed by two periods of the signal CK1, and so on.

[0092] Although Figure 2 not shown in Fig. 1, the reset inputs (labeled R) of the flip-flops FFsj all receive the same control signal, for example a control signal delivered by a control circuit (for example, the circuit 204).

[0093] As an example, when the oscillator OSC is set or reset before a rising edge of one of the signals CKfi, which can be the initial time to generate a delay Del1 in the time series to be generated, the rising edge on the output CKs1 of the flip-flop FF1 will arrive with a delay Del11 equal to q*Tf / Nf compared to this initial time, where q is an integer between 0 and Nf-1 and is determined by the signal CKfi used as the signal CK1. Moreover, the corresponding rising edge on the signal CKsj will arrive with a delay Del12 equal to (j-1)*Tf compared to this rising edge of the signal CKs1. In other words, the selection of the signal CK1 among the signals CKfi and the selection of one of the output signals CKsj enable to generate a delay Del1 having any value equal to Del11+Del12, i.e. equal to q*Tf / Nf + (j-1)*Tf. In practice, the above operation is similar to the operation of the device of Fig. 1. Figure 1

[0094] The device 200 further comprises a shift register SR. This shift register is similar to the shift register 110 of Fig. 1, except that its synchronous input CLKSR receives the clock signal CKs corresponding to one of the slow clock signals CKsj. Figure 2

[0095] ​​For example, the apparatus 200 comprises a selection circuit MUX2, e.g. a multiplexer, configured to receive all or a part of the signals CKsj, and configured to select a signal CKs from the received signals CKsj based on a control signal SEL2. As an example, the signal SEL2 is conveyed by a control circuit, e.g. the circuit 204.

[0096] As an alternative example, the circuit MUX2 is omitted, and the input CKSR of the register SR is connected to the output of a flip-flop FFsj, which outputs a signal CKsj having the signal CKs corresponding thereto.

[0097] The register SR comprises a number Nd1 of D-type flip-flops FFl, where l is an integer index ranging from 1 to Nd1, and Nd1 is a positive integer. In Figure 2 the example, Nd1 is greater than 1, but in other examples not shown, Nd1 can be equal to 1. The flip-flops FFl, Figure 2 FF1, FF2, FFNd1-1, FFNd1 in FFl, are coupled in series, i.e. one after the other, e.g. in Figure 2 increasing order of the index l in FFl.

[0098] The definition of the term "coupled in series" given above applies to the flip-flops FFl of the shift register SR. In Figure 2 the example, the Q output of each flip-flop FFl is connected to the D input of the next flip-flop FFl+1 in the series. In another example, the Q output of each flip-flop FFl is coupled to the D input of the next flip-flop FFl+1 by a circuit introducing a delay, to avoid metastability problems in the shift register SR.

[0099] Each flip-flop FFl conveys a signal Ql( Figure 2 Q1, Q2, QNd1-2, QNd1-1 and QNd1 in FFl.

[0100] Each flip-flop FFl has a synchronous input receiving a clock signal CKs, in Figure 2 denoted CK in FFl. For example, the input CKSR is coupled, preferably connected, to the CK input of each flip-flop FFl. In the remainder of the present disclosure, examples are described in which the flip-flops are enabled by a rising edge. However, the person skilled in the art will be able to adapt the teachings of the present disclosure to flip-flops enabled by a falling edge. The person skilled in the art will also be able to adapt the circuits by taking into account the output of the flip-flops, which output of the flip-flops corresponds to the binary complement of the Q output of that flip-flop.

[0101] For example, the D data input of the first flip-flop FF1 in a flip-flop series is powered by a high voltage, which, in this example where the edge under consideration is a rising edge, corresponds to the logic state "1".

[0102] The reset inputs (R) of all flip-flops FF1 receive the same control signal, such as a control signal transmitted by a control circuit (e.g., circuit 204). For example, this control signal is configured to perform a reset of flip-flops FF1 before the start of the time series generation cycle.

[0103] As an example, when the register SR is set or reset, for example, before the rising edge of one of the signals CKsj, that rising edge can be the initial time of the delay Del2 to be generated in the time sequence to be generated. Depending on the signal CKsj used as the signal CKs, the rising edge on the output Q1 of the flip-flop FF1 will arrive with a delay Del21 equal to o*Ts / Ns = o*Tf relative to the initial time of the delay Del2, where o is an integer in the range from 0 to Ns-1 and is determined by the signal CKsj used as the signal CKs. Furthermore, the corresponding rising edge on the signal Qp (where p is an integer from 1 to Nd1) will arrive with a delay Del22 equal to (p-1)*Ts relative to this rising edge of the signal Q1. In other words, selecting the signal CKs from the signals CKsj and selecting one of the output signals Ql makes it possible to generate a delay Del2, which has any value equal to Del21+Del22 (i.e., o*(Ts / Ns)+(p-1)*Ts).

[0104] As a supplementary example, a delay Del3 equal to the sum of delays Del1 and Del2 can be generated relative to the initial time corresponding to the initial time of delay Del1, for example by specifying that delay Del2 begins at the end of delay Del1. The Del3 delay will have an adjustment step size equal to Tf / Ns.

[0105] More generally, device 200 enables the generation of a delay between the two edges of the time series to be generated by first dividing the delay to be generated into a number of oscillator OSC periods Ts, then dividing the remaining duration into a number of oscillator RO periods Tf, and subsequently dividing the remaining duration into a number of fine-tuning steps Tf / Nf. In other words, the delay to be generated can be decomposed into a sum of a number of periods Ts, a number of periods Tf, and a number of fine-tuning steps Tf / Nf. This is consistent with... Figure 2 The devices are different, in Figure 2 The delay to be generated in the device is decomposed into only a certain number of oscillators 102 (corresponding to Figure 2 The oscillator RO in the device has a period and a certain number of fine-tuning steps T / N (equivalent toFigure 1 The sum of Tf / Nf in the device.

[0106] In addition, in order to generate greater than or equal to Figure 2 The oscillator 102 (or RO in the attached diagram) has a period delay of 10 times, and the device 200 needs to be more than Figure 2 The device 200 uses fewer flip-flops while maintaining the same adjustment accuracy, i.e., the same time resolution. Therefore, the device 200 is smaller in size than the corresponding device 100. Furthermore, since the flip-flops in the OSC and SR registers switch at a lower frequency than the flip-flops in device 100, the power consumption of device 200 is also lower than that of the equivalent device 100.

[0107] As a comparative example, consider device 100, where N = 5 and T = 1.25 ns. In this case, the time resolution of the delay generated by device 100 is equal to T / N = 1.25 / 5 = 250 ps. To generate a delay of 12.5 ns (which is therefore equal to 10 times the period T of oscillator 102), register 110 would have to include at least ten successive cascaded flip-flops. Now consider... Figure 2 Device 200, where Nf = 5 and Tf = 1.25 ns. In this case, like device 100, the time resolution of the delay generated by device 200 is equal to Tf / Nf = 250 ps. However, to generate a delay of 12.5 ns, in the example case where register OSC has Ns = 5 flip-flops and therefore operates with a period Ts = Ns * Tf = 6.25 ns, Nd1 = 2 flip-flops in register SR is sufficient. Therefore, device 200 may include 3 fewer flip-flops than device 100.

[0108] The output signal OUT1 of register SR corresponds to one of the output signals Q1 of flip-flop FF1.

[0109] exist Figure 2 In the example, the output signal Q1 of the flip-flop FF1 is coupled to a selection circuit MUX3, such as a multiplexer. The multiplexer MUX3 is configured to select one of its received signals Q1 based on a control signal SEL3 to form the output signal OUT1 of the shift register SR. As an example, signal SEL2 is transmitted by a control circuit (e.g., circuit 204). The circuit MUX3 is provided to allow adjustment of the delay ending with an edge on signal OUT1.

[0110] In other examples not shown, circuit MUX3 is omitted, and the output of register SR, on which signal OUT1 is obtained, is directly connected to the output of one of the flip-flops FF1.

[0111] exist Figure 2In an embodiment of the device 200, the device 200 further comprises a shift register SR'. The shift register SR' is synchronized with the clock signal CKf corresponding to one of the fast clock signals CKfi. The synchronization input CKSR' of the register SR' receives the signal CKf.

[0112] For example, the device 200 comprises a selection circuit MUX4, e.g. a multiplexer, configured to receive all or a part of the signals CKfi and configured to select a signal CKf from the received signals CKfi based on a control signal SEL4. The circuit MUX4 conveys the selected signal CKf to the input CKSR' of the register SR'. As an example, the signal SEL4 is conveyed by a control circuit, e.g. the circuit 204.

[0113] As an alternative example, the circuit MUX4 is omitted and the input CKSR' of the register SR' is connected to the output of a gate Ii conveying the signal CKfi having the signal CKf corresponding thereto.

[0114] The shift register SR' comprises a number Nd2 of D-type flip-flops FF'u, where u is an integer index ranging from 1 to Nd2 and Nd2 is a positive integer. In Figure 2 In the example of Fig. 2, Nd2 is greater than 1, but in other examples not shown, Nd2 can be equal to 1. The flip-flops FF'u Figure 2 FF'1, FF'2, FF'Nd2-1, FF'Nd2 in Fig. 2 are coupled in series, i.e. one after the other, e.g. in increasing order of the index u. Figure 2 FF'1, FF'2, FF'Nd2-1, FF'Nd2 in Fig. 2 are coupled in series, i.e. one after the other, e.g. in increasing order of the index u.

[0115] The definition of the term "coupled in series" given above applies to the flip-flops FF'u of the shift register SR'. In Figure 2 In the example of Fig. 2, the Q output of each flip-flop FF'u is connected to the D input of the next flip-flop FF'u+1 in the series. In another example, the Q output of each flip-flop FF'u is coupled to the D input of the next flip-flop FF'u+1 through a circuit introducing a delay to avoid metastability issues in the shift register SR'.

[0116] Each flip-flop FF'u conveys a signal Q'u Figure 2 Q'1, Q'2, Q'Nd2-1 and Q'Nd2 in Fig. 2.

[0117] Each flip-flop FF'u has a synchronization input receiving the clock signal CKf, in Figure 1The signal CK is denoted CK. For example, the input CKS is coupled (preferably connected) to the CK input of each flip-flop FF'u. In the rest of the disclosure, an example is described in which the flip-flops are enabled by a rising edge. However, the skilled person will be able to adapt the teachings of the disclosure to flip-flops enabled by a falling edge. The skilled person will also be able to adapt the circuit by considering the output of the flip-flop, the output of the flip-flop corresponds to the binary complement of the Q output of this flip-flop.

[0118] The D data input of the first flip-flop FF'1 in the series of flip-flops FF'u is coupled (for example, connected) to the data input DSR' of the register RS', the input DSR' receiving the output signal OUT1 from the register SR. In the example shown in Figure 2 In the example shown in Fig. 2, the D input of the flip-flop FF'1 is connected to the input DSR' of the register, so as to receive the signal OUT1.

[0119] The reset inputs (denoted R) of the flip-flops FF'u all receive the same control signal, for example a control signal from a control circuit (for example, the circuit 204).

[0120] The register SR' delivers an output signal OUT2, for example corresponding to an output signal of the device 200.

[0121] As an example, the register SR' is configured to generate an edge on the signal OUT2 of the register, this edge having a delay Del4 with respect to an edge on the output signal OUT1 of the register SR, this edge on the output OUT1 forming the initial time of the delay Del4. As an example, the register SR' is reset before the initial time of this delay Del4. The initial time of the delay Del4 is synchronized with the signal CKs, which itself is synchronized with the CK1 signal corresponding to one of the signals CKfi. In this example, depending on the signal CKfi used as the signal CKf, the rising edge on the output Q'1 of the flip-flop FF'1 will arrive with a delay Del41 equal to k*Tf / Nf, where k is an integer in the range from 0 to Nf-1 and is determined by the signal CKfi used as the signal CK1 and CKs, respectively. Furthermore, with respect to this rising edge of the signal Q'1, the corresponding rising edge on the signal Q'u will arrive with a delay Del42 equal to (u-1)*Tf. In other words, the choice of the signal CKf from among the signals CKfi and the choice of one of the output signals Q'u as the signal OUT2 produce a delay Del4 having any value equal to Del41 + Del42, i.e. equal to k*Tf / Nf + (u-1)*Tf.

[0122] ​In practice, the above operation of the register SR' generating a delay Del4 between an edge on the signal OUT1 and an edge on the signal OUT2 is similar to Figure 2 the operation of the register 122 of the device of Fig. 1 generating a delay between an edge on the output SR1_OUTPUT of the register 104 and an edge on the output of another shift register forming part of the circuit 122. The methods described in the patent applications FR 3133458, US2023291396 and CN 116760392 are suitable for selecting the signal Ckf from among the signals CKfi and the output signal OUT2 from among the signals Q'u, so as to achieve a delay Del4 between an edge on the signal OUT1 and an edge on the signal OUT2. In particular, the person skilled in the art will be able to avoid possible metastability problems, for example by selecting the signal CKf based on the methods described in connection with Figs. 4, 5a, 5b and 5c of the above-mentioned applications.

[0123] In the example of Fig. 1, ​ the output signal Q'u of the flip-flop FF'u is coupled, for example, to a selection circuit MUX5, for example a multiplexer. The multiplexer MUX5 is configured to select one of the signals Q'u it receives based on a control signal SEL5 to form the output signal OUT2 of the shift register SR'. As an example, the signal SEL5 is delivered by a control circuit, for example the circuit 204. The provision of the circuit MUX5 makes it possible to adjust the delay ending with an edge on the signal OUT2.

[0124] In other examples not illustrated, the circuit MUX5 is omitted and the output of the register SR' on which the signal OUT2 is available is directly connected to the output of one of the flip-flops FF'u.

[0125] Returning to the example of calculating the delays Del1 and Del3, when the initial time of the delay Del1 is synchronized with an edge of the signal CK1, the delay Del11 has a zero value and the delay Del1 then has a value equal to 0 + Del12, i.e. equal to (j-1)*Tf. The time resolution of the delay Del3 is therefore equal to Tf and is no longer equal to Tf / Nf. The provision of the register then makes it possible to generate a delay Del3' between the initial time of the delay Del1 and the edge ending the marked delay Del3' on the output OUT2, which has a value equal to Del3 + Del4 and therefore a time resolution equal to Tf / Nf.

[0126] As a comparative example, consider a device 100 in which N = 5 and T = 1.25 ns. To generate a delay of 12.5 ns, which is therefore equal to 10 times the period T of the oscillator 102, the register 110 would have to comprise at least ten flip-flops in series. Now consider ​The device 200 can be used to generate a sequence of edges between the rising edge of the signal CK1 and the falling edge of the signal OUT2, the sequence of edges being generated by the device 200 in the same way as the sequence of edges between the rising edge of the signal CK1 and the rising edge of the signal OUT1. In this case, the device 200 can be used to generate a delay between the rising edge of the signal CK1 and the falling edge of the signal OUT2, the delay being generated by the device 200 in the same way as the delay between the rising edge of the signal CK1 and the rising edge of the signal OUT1. In this case, for Nd1 equal to 2, for Nd2 equal to 1, for OUT1 = Q2, for CKf = CK4 and for OUT2 = Q'1, it is sufficient to generate a delay of 12.5 ns between the edge of the signal CK1 and the edge of the signal OUT2, with a resolution of Tf / Nf. Then, the device 200 can comprise 2 fewer flip-flops than the device 100.

[0127] The above has described an example of an embodiment in which the register SR' is synchronized with a signal CKf corresponding to one of the fast clock signals CKfi. In other embodiments, the register SR' can be synchronized with a clock signal corresponding to one of the slow clock signals CKsj.

[0128] Furthermore, a time sequence comprising more edges can be generated by adding shift registers one after the other in the same way as the register SR' follows the register SR, each of these additional registers being synchronized with a respective clock signal corresponding to one of the slow clock signals CKsj or one of the fast clock signals CKfi.

[0129] Furthermore, the above has described an example of an embodiment in which the signal CK1 corresponds to one of the fast clock signals CKfi. In alternative embodiments, in order to generate longer delays in the time sequence, the signal CK1 can be provided to correspond to one of the signals CKfi which has previously undergone a division of its frequency by a positive integer M. Indeed, in this case, the period of the oscillator OSC is multiplied by M. It should be noted that the case where M is equal to 1 corresponds to making the signal CK1 correspond to one of the fast clock signals CKfi, as in the case of the example described above.

[0130] Furthermore, as indicated previously, while examples of sequences and delays generated using the device 200 have been described with reference to rising edges, the person skilled in the art will be able to generate, on the basis of the present disclosure, delays and / or time sequences between rising and falling edges or only between falling edges using the device 200. For example, in the case where the edge of interest generated at the output OUT1 of the register SR is a falling edge, the first flip-flop FF1 of the register SR can have its D data input receive a voltage in the low state, for example corresponding to the logic state "0".

[0131] In particular, while this is not indicated in connection with the above description of the oscillator OSC, it is advantageous to provide a given duty cycle K / Ns when the time sequence generated by the device 200 is a sequence between rising and falling edges, for example when the sequence generated is a control sequence of a power device configured to deliver an average power equal to a setpoint value.

[0132] As an example, the device 200 can be used to generate control sequences for power devices or memories, for example in electronic systems corresponding to power applications (for example, industrial) and / or applications in the transport sector and / or Internet of Things (loT) type applications.

[0133] Various embodiments and variant examples have been described. The person skilled in the art will understand that certain features of these various embodiments and variant examples can be combined and that other variant examples will occur to the person skilled in the art. In particular, the signals generated at the output of one or more registers controlled by the oscillators RO and OSC in the device 200 can be recombined with logic gates to construct more complex signals. Moreover, in examples not shown, the circuit MUX1 can receive only a portion of the signal CKfi and / or the circuit MUX2 can receive only a portion of the signal CKsj and / or the circuit MUX3 can receive only a portion of the signal Ql and / or the circuit MUX4 can receive only a portion of the signal CKfi and / or the circuit MUX5 can receive only a portion of the signal Q'u. Conversely, in other examples, the circuit MUX2 can receive all or a portion of the signal Ckfi in addition to one or more signals CKsj and / or the circuit MUX4 can receive all or a portion of the signal CKsj in addition to one or more signals CKfi. In other words, in these other examples, the signal CKs is selected from among all or a portion of the signal CKfi and all or a portion of the signal CKsj and / or the signal CKf is selected from among all or a portion of the signal CKfi and all or a portion of the signal CKsj.

[0134] Finally, the actual implementation of the described embodiments and variant examples is within the capabilities of the person skilled in the art on the basis of the functional indications given above. In particular, the person skilled in the art will be able to implement the reset steps of the oscillators RO and OSC and of the registers SR and SR' according to the time sequence to be generated on the basis of the functional description given above, to obtain the operations described above, i.e. to generate a delay decomposed into a number of periods Ts, a number of periods Tf and a number of steps Tf / Nf. As an example, these resets of the various elements RO, OSC, SR and SR' of the device are controlled by the circuit 204.

Claims

1. An apparatus comprising: A ring oscillator includes multiple inverting logic gates, which are coupled one after another and each transmits a fast clock signal; A first shift register includes successive first flip-flops, each of which is synchronized with the same first clock signal, which corresponds to one of the fast clock signals whose frequency is divided by a positive integer M. The first shift register is looped back onto itself to implement a second oscillator in which each of the first flip-flops transmits a slow clock signal. as well as The second shift register includes a single second flip-flop or a series of second flip-flops, each of which is synchronized with the same second clock signal, which corresponds to one of the slow clock signals.

2. The apparatus of claim 1, wherein the data input of the first first flip-flop in the successive first flip-flops receives a signal at least partially determined by a first binary signal, the first binary signal being equal to a logical OR between the output of the last first flip-flop in the successive first flip-flops and the logical NOT between the logical OR of the outputs of the last at least two first flip-flops in the successive first flip-flops.

3. The apparatus of claim 2, wherein the signal received by the data input of the first first flip-flop is equal to a logical OR between the first signal and the NOT of the enable signal, or equal to a logical AND between the first binary signal and the enable signal.

4. The apparatus of claim 1, wherein the fast clock signals are time-shifted relative to each other.

5. The apparatus of claim 1, wherein the slow clock signals are time-shifted relative to each other.

6. The apparatus of claim 1, further comprising a first selection circuit configured to select a first clock signal from at least one of a fast clock signal whose frequency is divided by an integer M and a fast clock signal.

7. The apparatus of claim 6, wherein the first selection circuit is configured to transmit a first clock signal to the synchronization input of each of the first flip-flops in the first flip-flops.

8. The apparatus of claim 1, further comprising a second selection circuit configured to select a second clock signal from all or a portion of the slow clock signals.

9. The apparatus of claim 8, wherein the second selection circuit is configured to transmit a second clock signal to the synchronization input of each of the second flip-flops.

10. The apparatus of claim 1, further comprising a third shift register, the third shift register comprising a single third flip-flop or a succession of third flip-flops, preferably comprising a single D-type third flip-flop or a succession of D-type third flip-flops, each third flip-flop being synchronized with the same third clock signal corresponding to one of the fast clock signals.

11. The apparatus of claim 10, further comprising a third selection circuit configured to receive all or part of a fast clock signal and configured to transmit the third clock signal to the synchronization input of each third flip-flop.

12. The apparatus of claim 10, wherein the data input of the third shift register receives a signal determined by the output of the second shift register.

13. The apparatus of claim 12, wherein the second shift register includes the successive second flip-flops, and the apparatus further includes a fourth selection circuit configured to select an output signal of one of the second flip-flops from all or a portion of the output signals of the second flip-flops, and configured to transmit the selected signal to a data input of the third shift register.

14. The apparatus of claim 10, wherein the output of the third register is the output of the single third flip-flop, or the output of one of the successive third flip-flops selected by the selection circuit from all or a portion of the outputs of the successive third flip-flops.

15. The apparatus of claim 1, further comprising a circuit configured to: Controlling the settings of the first trigger and the second trigger; and / or Enable the ring oscillator.

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