Serial communication system

Abstract

A serial communication system (1) comprises: n slave devices (21-28) having the same address; a master device (10); n switch ICs (41-48); and shift registers (31-32) capable of individually controlling ON / OFF of the n switch ICs (41-48). One clock signal line and one data signal line connected to the master device (10) respectively branch into n clock signal lines and n data signal lines, and are respectively connected to the n slave devices (21-28) via the n switch ICs (41-48). Said one clock signal line and one data signal line connected to the master device (10) further branch into and are connected to shift registers (31-32).

Description

Serial communication system

[0001] The present disclosure relates to a serial communication system used for communication between one master device and a plurality of slave devices.

[0002] In a power storage system equipped with a plurality of series-connected lithium-ion battery cells, it is necessary to measure and monitor the voltage of each lithium-ion battery cell. Since a general AFE (Analog Front End) IC can only handle voltage measurements of up to 16 cells, in a power storage system with a series number exceeding 16 cells, a plurality of AFE ICs are used. The plurality of AFE ICs transmit the measured cell voltage, temperature, and current to a microcontroller via a serial communication interface.

[0003] As a serial communication interface between an AFE IC and a microcontroller, I2C (Inter-Integrated Circuit) with the microcontroller as the master device and the AFE IC as the slave device is often used. In the I2C bus line, two signal lines, a serial clock line SCL and a serial data line SDA, are used (see, for example, Patent Document 1).

[0004] Many inexpensive AFE ICs have a fixed I2C slave address. In a system using a plurality of AFE ICs such as a power storage system, there is a need to use a plurality of AFE ICs with the same slave address. When connecting a plurality of slave devices with the same address and one master device, it is conceivable to connect each of the plurality of slave devices to the I2C bus line (see Fig. 1). However, since the number of I2C bus lines increases, the cost increases. Also, slave devices exceeding the number of I2C ports of the master device cannot be connected.

[0005] Alternatively, an I2C switch IC could be installed between the master device and multiple slave devices, with a single I2C bus line connecting the master device and the I2C switch IC (see Figure 2). Even with this configuration, it's not possible to connect more slave devices than the number of I2C ports on the I2C switch IC. Adding more I2C switch ICs by daisy-chaining is also not easy. Furthermore, it's necessary to configure the I2C switch IC with a management slave address used by the master device, which involves a cumbersome process.

[0006] Japanese Patent Publication No. 2000-165421

[0007] This disclosure is made in light of these circumstances, and its purpose is to provide a serial communication system that can be easily expanded with additional slave devices and built at low cost.

[0008] To solve the above problems, a serial communication system in one aspect of the present disclosure comprises n (where n is an integer of 2 or more) slave devices having the same address, a master device that communicates serially with the n slave devices, n switch ICs that turn on / off the connections between the n slave devices and the master device, respectively, and a shift register capable of individually controlling the on / off states of the n switch ICs. One clock signal line and one data signal line connected to the master device branch into n clock signal lines and n data signal lines, respectively, and are connected to the n slave devices via the n switch ICs, and the one clock signal line and one data signal line connected to the master device further branch and are connected to the shift register.

[0009] According to this disclosure, it is possible to easily add slave devices and build a serial communication system at low cost.

[0010] This figure shows an example configuration of a serial communication system according to Comparative Example 1. This figure shows an example configuration of a serial communication system according to Comparative Example 2. This figure shows an example configuration of a serial communication system according to Comparative Example 3. This figure shows an example configuration of a serial communication system according to an embodiment. This figure shows an example of a timing chart for a serial communication system according to an embodiment.

[0011] Figure 1 shows an example configuration of serial communication system 1 according to Comparative Example 1. The serial communication system 1 according to Comparative Example 1 comprises a microcontroller 10 which is an I2C master device and n (n is an integer of 2 or more) I2C slave devices having the same address. Figure 1 shows an example where n=4, and the serial communication system 1 comprises a first slave device 21 to a fourth slave device 24.

[0012] The microcontroller 10 and the first slave device 21 to the fourth slave device 24 are connected by I2C bus lines. Each I2C bus line consists of two signal lines: a serial clock line SCL and a serial data line SDA. The microcontroller 10 has I2C ports: SCL0 pin, SDA0 pin, SCL1 pin, SDA1 pin, SCL2 pin, SDA2 pin, SCL3 pin, and SDA3 pin, which are connected to the first slave device 21 to the fourth slave device 24 via four I2C bus lines.

[0013] In I2C, both the serial clock line (SCL) and the serial data line (SDA) use an open-drain or open-collector output method for the connected devices. Therefore, pull-up resistors must be connected to each serial clock line (SCL) and each serial data line (SDA). In the example shown in Figure 1, pull-up resistors R11-R14 are connected to each serial clock line (SCL), and pull-up resistors R21-R24 are connected to each serial data line (SDA). In this configuration, when not communicating, the serial clock line (SCL) and serial data line (SDA) are in a high-level state.

[0014] As described above, in the configuration of Comparative Example 1, an I2C bus line must be installed for each slave device. Therefore, as the number of slave devices increases, the number of I2C bus lines also increases, leading to increased costs. Furthermore, since it is not possible to connect more slave devices than the number of I2C ports on the microcontroller 10, there is a limit to the number of slave devices that can be added.

[0015] Figure 2 shows an example configuration of serial communication system 1 according to Comparative Example 2. Serial communication system 1 according to Comparative Example 2 includes a microcontroller 10 which is an I2C master device, an I2C switch IC 60, and I2C first slave devices 21 to fourth slave devices 24 having the same address.

[0016] The microcontroller 10 has SCL0 and SDA0 pins as I2C ports and is connected to the I2C switch IC 60 by one I2C bus line. The I2C switch IC 60 has SCL1, SDA1, SCL2, SDA2, SCL3, SDA3, SCL4, and SDA4 pins as slave connection I2C ports and is connected to the first slave device 21 through the fourth slave device 24 by four I2C bus lines, respectively.

[0017] The I2C switch IC 60 includes a path switching switch internally and switches paths according to the slave address received from the microcontroller 10. In the serial communication system 1, in addition to the slave addresses specific to the first slave device 21 to the fourth slave device 24, each is uniquely assigned a management slave address. The I2C switch IC 60 assigns a management slave address to each of the I2C ports on the slave connection side and selects the I2C port corresponding to the slave address received from the microcontroller 10.

[0018] As described above, even with the configuration of Comparative Example 2, it is not possible to connect more slave devices than the number of I2C ports on the I2C switch IC 60. Adding more I2C switch IC 60s by daisy-chaining them is also not easy. Furthermore, it is necessary to set a management slave address for the I2C switch IC 60, which involves a complicated process.

[0019] Figure 3 shows an example configuration of serial communication system 1 according to Comparative Example 3. The serial communication system 1 according to Comparative Example 3 includes a microcontroller 10 which is an I2C master device, a first address translation IC 71 to an eighth address translation IC 78, and first to eighth I2C slave devices 21 to 28 which have the same address.

[0020] The microcontroller 10 has an SCL0 pin and an SDA0 pin as I2C ports, to which one I2C bus line is connected. This single I2C bus line is then branched into eight lines, each connected to the first address translation IC 71 through the eighth address translation IC 78. The first address translation IC 71 through the eighth address translation IC 78 are connected to the first slave device 21 through the eighth slave device 28 via their respective I2C bus lines.

[0021] In the serial communication system 1, each of the first slave devices 21 to the eighth slave device 28 is uniquely assigned a management slave address in addition to its own unique slave address. The first address translation IC 71 to the eighth address translation IC 78 translate the management slave addresses assigned to each of the first slave devices 21 to the eighth slave device 28 and their respective unique slave devices. This allows a communication channel to be established between the microcontroller 10 and the slave device corresponding to the management slave address specified by the microcontroller 10.

[0022] In the configuration of Comparative Example 3, only one I2C port is needed for the microcontroller 10, and slave devices can be easily added. However, each I2C address translation IC needs to be assigned a unique slave address for management purposes. Assigning a unique slave address for management purposes to each address translation IC requires circuit configuration such as pull-up resistors / pull-down resistors to the address setting terminal of the address translation IC. It is not possible to add address translation ICs with the same circuit configuration; the circuit configuration must be changed each time an address translation IC is added to ensure a unique address. Furthermore, address translation ICs are relatively expensive. In particular, as the number of slave devices increases, the number of address translation ICs also increases, and so does the cost.

[0023] Figure 4 shows an example configuration of a serial communication system 1 according to an embodiment. The serial communication system 1 according to the embodiment includes a microcontroller 10 which is an I2C master device, n I2C slave devices having the same address, n switch ICs, m (m is a natural number) shift registers, and m one-shot circuits. In Figure 4, an example with n=8 and m=2 is shown, and the serial communication system 1 shown in Figure 4 includes a first slave device 21 to an eighth slave device 28, a first switch IC 41 to an eighth switch IC 48, a first shift register 31 to a second shift register 32, and a first one-shot circuit 51 to a second one-shot circuit 52.

[0024] The first switch IC 41 to the eighth switch IC 48 switch the first slave device 21 to the eighth slave device 28 and the microcontroller 10 on and off, respectively. The first shift register 31 to the second shift register 32 can individually control the on / off states of the first switch IC 41 to the eighth switch IC 48.

[0025] More specifically, the first shift register 31 controls the on / off state of the first switch IC 41 to the fourth switch IC 44, and the second shift register 32 controls the on / off state of the fifth switch IC 45 to the eighth switch IC 48. When m = 1, one shift register controls the on / off state of all the switch ICs. When m ≥ 2, each shift register controls the on / off state of a subset of the n switch ICs.

[0026] The microcontroller 10 supports both I2C serial communication and SPI (Serial Peripheral Interface) serial communication. Generally, SPI uses four signal lines: the serial clock line SCK, the master output / slave input data line MOSI, the master input / slave output data line MISO, and the chip select line CS.

[0027] In this embodiment, SPI is used for serial communication between the microcontroller 10 and m shift registers, with the microcontroller 10 as the master device and the m shift registers as slave devices. In this embodiment, since no data is transmitted from the m shift registers to the microcontroller 10, the master input / slave output data line MISO is unnecessary. Since data is transmitted between the microcontroller 10 and the m shift registers via daisy-chain connection, the chip select line CS is also unnecessary.

[0028] In SPI, the output method of the devices connected to each signal line is a push-pull output method, so the microcontroller 10 drives the signal levels of the serial clock line SCK and the data line MOSI to high level and low level, respectively.

[0029] The microcontroller 10 has SCL0 / SCK pins and SDA0 / MOSI pins as common I2C and SPI ports. One I2C bus line is connected to the SCL0 / SCK pins and SDA0 / MOSI pins. The I2C bus line consists of one serial clock line SCL and one serial data line SDA. A high level potential is supplied to the serial clock line SCL via a pull-up resistor R1, and a high level potential is supplied to the serial data line SDA via a pull-up resistor R2.

[0030] One serial clock line SCL and one serial data line SDA each branch into eight serial clock lines SCL and eight serial data lines SDA, respectively, and are connected to the first slave device 21 and the eighth slave device 28 via the first switch IC 41 and the eighth switch IC 48.

[0031] Each switch IC includes a switch for turning the serial clock line SCL on and off, and a switch for turning the serial data line SDA on and off. Each switch can be, for example, a CMOS (Complementary Metal-Oxide-Semiconductor) analog switch. A CMOS analog switch consists of a combination of P-channel MOSFETs and N-channel MOSFETs.

[0032] Each of the first shift register 31 and the second shift register 32 is a series-input, parallel-output shift register containing multiple cascaded flip-flop circuits (four flip-flop circuits in Figure 4). The first shift register 31 and the second shift register 32 and the microcontroller 10 are daisy-chained together by a single data line MOSI branched from a single serial data line SDA.

[0033] Specifically, a single data line MOSI, branched from a serial data line SDA connected to the microcontroller 10, is connected to the SER pin of the first shift register 31. The Q' pin, which outputs the output data of the final stage flip-flop circuit of the first shift register 31, is connected to the SER pin of the second shift register 32 by a single data line MOSI.

[0034] The single serial clock line SCL connected to the microcontroller 10 is further branched into two, and connected to the SRCLK pin of the first shift register 31 and the SRCLK pin of the second shift register 32, respectively.

[0035] A single storage register clock line RCLK is connected to the GPIO (General Purpose Input / Output) pin of the microcontroller 10. This single storage register clock line RCLK is then split into two, each connected to the RCLK pin of the first shift register 31 and the RCLK pin of the second shift register 32, respectively.

[0036] The storage register clock line RCLK, which is connected to the RCLK pin of the first shift register 31, is further branched before being connected to the RCLK pin, and the branched storage register clock line RCLK is connected to the input pin of the first one-shot circuit 51. The output pin of the first one-shot circuit 51 is a reset signal line and is connected to the Reset pin of the first shift register 31.

[0037] The storage register clock line RCLK, which is connected to the RCLK pin of the second shift register 32, is further branched before being connected to the RCLK pin, and the branched storage register clock line RCLK is connected to the input pin of the second one-shot circuit 52. The output pin of the second one-shot circuit 52 is a reset signal line and is connected to the Reset pin of the second shift register 32.

[0038] The four parallel output pins of the first shift register 31 are connected to the control pins of the first switch IC 41 through the fourth switch IC 44 via drive signal lines. The four parallel output pins of the second shift register 32 are connected to the control pins of the fifth switch IC 45 through the eighth switch IC 48 via drive signal lines.

[0039] When the serial communication system 1 according to this embodiment is used in a battery pack equipped with multiple battery modules, each containing multiple lithium-ion battery cells, one shift register, one one-shot circuit, multiple slave devices, and multiple switch ICs are installed in each battery module. The same circuit configuration can be used for the one shift register, one one-shot circuit, multiple slave devices, and multiple switch ICs installed in each battery module. As the number of battery modules increases, the same circuit configuration can be daisy-chained using three signal lines (serial clock line SCL, serial data line SDA, and storage register clock line RCLK).

[0040] In the example shown in Figure 4, the first battery module is equipped with a first shift register 31, a first one-shot circuit 51, a first slave device 21 to a fourth slave device 24, and a first switch IC 41 to a fourth switch IC 44. The second battery module is equipped with a second shift register 32, a second one-shot circuit 52, a fifth slave device 25 to an eighth slave device 28, and a fifth switch IC 45 to an eighth switch IC 48.

[0041] In the serial communication system 1 according to this embodiment, the parallel output of m shift registers controls the on / off state of n switch ICs, thereby individually turning on / off each I2C bus line between the microcontroller 10 and the slave device.

[0042] As described above, the serial communication port of the microcontroller 10 is shared by I2C and SPI. A common signal line is used for the serial clock line SCL of I2C and the serial clock line SCK of SPI. A common signal line is used for the serial data line SDA of I2C and the data line MOSI of the master output slave input of SPI. Note that the serial data line SDA of I2C and the data line MISO of the master input slave output of SPI may be shared.

[0043] The microcontroller 10 sets the serial communication port to the SPI mode and outputs a selection signal for selecting a specific switch IC among n switch ICs using the serial clock line SCK and the data line MOSI. To control m shift registers from the microcontroller 10, it is necessary to control them in a push-pull output method. After outputting the selection signal, the microcontroller 10 transitions the storage register clock line RCLK from inactive to active.

[0044] The m shift registers latch the selection signal output from the microcontroller 10 at the timing when the storage register clock line RCLK transitions from inactive to active. The m shift registers control a specific switch IC to be in an on state according to the latched selection signal.

[0045] After a specific switch IC is controlled to be in an on state, the microcontroller 10 sets the serial communication port to the I2C mode and communicates with a specific slave device in the I2C mode via the specific switch IC using the serial clock line SCL (shared with the serial clock line SCK) and the serial data line SDA (shared with the data line MOSI).

[0046] When the communication with a specific slave device ends, the microcontroller 10 transitions the storage register clock line RCLK from active to inactive. The m shift registers reset the latched selection signal at the timing when the storage register clock line RCLK transitions from active to inactive, and turn off a specific switch IC. Hereinafter, a specific example will be given for explanation.

[0047] FIG. 5 is a diagram showing an example of a timing chart of the serial communication system 1 according to the embodiment. First, the microcontroller 10 sets the SCL0 / SCK pin and the SDA0 / MOSI pin to the SPI mode, and enables the transmission of the SCK signal and the MOSI signal. Next, the microcontroller 10 uses the SCK signal and the MOSI signal to shift the active bits. In the example shown in FIG. 5, the active bits are shifted by 8 bits, and the MOSI signal of 0x01 is transmitted to the first shift register 31 - the second shift register 32.

[0048] Next, the microcontroller 10 latches the first shift register 31 - the second shift register 32 by transitioning the RCLK signal output from the GPIO pin to a high level. As a result, among the enable signals EN1 - EN8 output from the parallel output pins of the first shift register 31 - the second shift register 32 to the first switch IC 41 - the eighth switch IC 48, the enable signal EN1 output to the first switch IC 41 transitions to a high level and is maintained at the high level. Thereby, the first switch IC 41 is turned on, and the microcontroller 10 and the first slave device 21 are connected by the I2C bus line.

[0049] Next, the microcontroller 10 sets the SCL0 / SCK pin and the SDA0 / MOSI pin to the I2C mode, enables the transmission of the SCL signal, and enables the transmission and reception of the SDA signal. The microcontroller 10 communicates with the first slave device 21 in the I2C mode using the SCL signal and the SDA signal.

[0050] The SER pin and SRCLK pin of the first shift register 31 and the second shift register 32 are connected to the I2C bus line communicating in I2C mode, and the input data of the first shift register 31 and the second shift register 32 changes according to the SDA signal. However, when the RCLK signal is at a high level, the enable signals EN1-EN8 output from the first shift register 31 and the second shift register 32 do not change, so the first switch IC 41 and the eighth switch IC 48 do not malfunction.

[0051] Next, the microcontroller 10 transitions the RCLK signal output from the GPIO pin to a low level in order to switch the slave device to communicate with. When the RCLK signal transitions to a low level, the first one-shot circuit 51 and the second one-shot circuit 52 emit a one-shot low-level pulse and output it to the Reset pins of the first shift register 31 and the second shift register 32, respectively. This resets the first shift register 31 and the second shift register 32.

[0052] When the first shift register 31 and the second shift register 32 are reset, the enable signals EN1-EN8 output from the first shift register 31 and the second shift register 32 all go to a low level, and the first switch IC 41-8th switch IC 48 all turn off. This prevents a collision between the MOSI signal transmitted from the microcontroller 10 in SPI mode and the SDA signal transmitted from the slave device in I2C mode.

[0053] Next, the microcontroller 10 sets the SCL0 / SCK pin and SDA0 / MOSI pin to SPI mode, making them ready to transmit the SCK signal and MOSI signal. Then, the microcontroller 10 uses the SCK signal and MOSI signal to data shift the active bits. In the example shown in Figure 5, the active bits are shifted by 8 bits, and a MOSI signal of 0x02 is sent from the first shift register 31 to the second shift register 32.

[0054] Next, the microcontroller 10 latches the first shift register 31 and the second shift register 32 by transitioning the RCLK signal output from the GPIO pin to a high level. As a result, of the enable signals EN1-EN8 output from the parallel output pins of the first shift register 31-2 shift register 32 to the first switch IC 41-8th switch IC 48, the enable signal EN2 output to the second switch IC 42 is transitioned to a high level and maintained at a high level. This turns on the second switch IC 42, and the microcontroller 10 and the second slave device 22 are connected by an I2C bus line.

[0055] As described above, according to this embodiment, it is possible to easily add slave devices and construct a low-cost serial communication system 1. Using m shift registers, n switch ICs, and three signal lines—a serial clock line SCL (shared with the serial clock line SCK), a serial data line SDA (shared with the data line MOSI), and a storage register clock line RCLK—any slave device from among multiple slave devices having the same address can be selected as the connection destination for the microcontroller 10.

[0056] Since general-purpose components can be used for the shift register and switch IC, the serial communication system 1 can be built inexpensively. In this respect, the I2C address translation IC shown in Comparative Example 3 is an expensive component compared to the shift register and switch IC.

[0057] Since only three signal lines are needed to connect to the microcontroller 10, the number of wire harnesses can be reduced. In this embodiment, since a shift register is installed in each of the multiple battery modules that make up the battery pack, the main board on which the microcontroller 10 is mounted and the boards of each battery module can be connected with three wire harnesses.

[0058] In this respect, in Comparative Example 2, since the I2C switch IC 60 is installed on the main board, it is necessary to connect each of the multiple slave devices installed on each battery module to the I2C switch IC 60 with a wire harness. If the number of slave devices is large, the number of wire harnesses increases, and the cost increases. In this respect, in this embodiment, even if the number of battery modules and the number of slave devices are large, the main board and the boards of each battery module can be connected with three wire harnesses, thereby suppressing the increase in cost.

[0059] Furthermore, by installing multiple switch ICs and shift registers in a single battery module and cascading them, multiple slave devices can be easily added. In this case, multiple shift registers can be daisy-chained using a total of four wire harnesses: three wire harnesses connecting the main board and the boards of each battery module, and one wire harness connecting the two shift registers installed in two adjacent battery modules.

[0060] Because multiple switch ICs and a shift register allow only specific switch ICs to be turned on, multiple slave devices with overlapping I2C addresses can be connected to a single I2C bus line connected to the microcontroller 10. Even slave devices whose I2C addresses can be arbitrarily changed can have their addresses fixed and be used multiple times in the same serial communication system 1. In other words, there is no need to change the I2C address for each slave device in the same serial communication system 1.

[0061] The present disclosure has been described above based on embodiments. The embodiments are illustrative, and it will be understood by those skilled in the art that various modifications are possible in combinations of their components and processing processes, and that such modifications are also within the scope of the present disclosure.

[0062] For example, if there is a spare output pin on a shift register, that pin can be used as a general-purpose output port. An I2C port can also be used as an I / O expander.

[0063] In the above description, we assumed an example in which the serial communication system 1 according to the embodiment is used in a battery pack having multiple battery modules. However, it can be applied to applications other than battery packs as long as it involves serial communication between a single microcontroller and multiple slave devices.

[0064] The embodiments may be specified by the following items.

[0065] [Item 1] A serial communication system (1) comprising: n (where n is an integer of 2 or more) slave devices (21-28) having the same address; a master device (10) that communicates serially with the n slave devices (21-28); n switch ICs (41-48) that turn on / off the connections between the n slave devices (21-28) and the master device (10); and a shift register (31-32) capable of individually controlling the on / off states of the n switch ICs (41-48); wherein one clock signal line and one data signal line connected to the master device (10) branch into n clock signal lines and n data signal lines, respectively, and are connected to the n slave devices (21-28) via the n switch ICs (41-48); and the one clock signal line and one data signal line connected to the master device (10) further branch and are connected to the shift register (31-32). According to this, it is possible to easily add slave devices and construct a low-cost serial communication system (1). [Item 2] The serial communication system (1) described in Item 1, wherein the master device (10) and the shift registers (31-32) are further connected by a register clock signal line. According to this, the on / off state of n switch ICs (41-48) can be maintained in any state. [Item 3] The serial communication system (1) described in Item 2, wherein the shift registers (31-32) consist of m (where m is an integer of 2 or more) shift registers (31-32), each of the m shift registers (31-32) controls the on / off state of some of the switch ICs of the n switch ICs (41-48), the one clock signal line and the one register clock signal line connected to the master device (10) branch into m clock signal lines and m data signal lines, respectively, and are connected to each of the m shift registers (31-32), and the master device (10) and the m shift registers (31-32) are daisy-chained by the branched data signal line.According to this, multiple slave devices, multiple switch ICs, and one shift register can be added using the same circuit configuration. [Item 4] The master device (10) uses one clock signal line and one data signal line to output a selection signal for selecting a specific switch IC (41) among the n switch ICs (41-48) in a first serial communication method, the shift registers (31-32) control the specific switch IC (41) to an ON state according to the selection signal, and after the specific switch IC (41) is controlled to an ON state, the master device (10) uses one clock signal line and one data signal line to communicate with a specific slave device (21) via the specific switch IC (41) in a second serial communication method, as described in Item 1. According to this, channel selection of any slave device by a shift register and serial communication with the selected slave device can be realized with a low-cost circuit configuration.[Item 5] The master device (10) uses the one clock signal line and the one data signal line to output a selection signal for selecting a specific switch IC (41) among the n switch ICs (41-48) in a first serial communication method, and transitions the register clock signal line from inactive to active. The shift registers (31-32) latch the selection signal at the timing when the register clock signal line transitions from inactive to active, and control the specific switch IC (41) to an ON state in accordance with the latched selection signal. After the specific switch IC (41) is controlled to an ON state, the master device (10) uses the one clock signal line and the one data signal line to communicate with a specific slave device (21) via the specific switch IC (41) in a second serial communication method, and when communication with the specific slave device (21) is completed, transitions the register clock signal line from active to inactive. The serial communication system (1) described in item 2, wherein the shift registers (31-32) reset the latched selection signal and turn off the specific switch IC (41) when the register clock signal line transitions from active to inactive. This allows for channel selection of any slave device using a shift register and serial communication with the selected slave device with a low-cost circuit configuration. [Item 6] The serial communication system (1) described in item 4 or 5, wherein the first serial communication method is SPI (Serial Peripheral Interface) and the second serial communication method is I2C (Inter-Integrated Circuit). This allows for channel selection of any slave device using a shift register compatible with SPI mode, and enables serial communication with the selected slave device in I2C mode.

[0066] This disclosure can be used for serial communication between an AFEIC and a microcontroller.

[0067] 1 serial communication system, 10 microcontrollers, 21-28 slave devices, 31-32 shift registers, 41-48 switch ICs, 51-52 one-shot circuits, 60 I2C switch ICs, 71-78 address translation ICs, R1-R2, R11-R18, R21-R28 pull-up resistors.

Claims

1. A serial communication system comprising: n (where n is an integer of 2 or more) slave devices having the same address; a master device that communicates serially with the n slave devices; n switch ICs that turn on / off the connections between the n slave devices and the master device, respectively; and a shift register capable of individually controlling the on / off states of the n switch ICs, wherein one clock signal line and one data signal line connected to the master device branch into n clock signal lines and n data signal lines, respectively, and are connected to the n slave devices via the n switch ICs, and the one clock signal line and one data signal line connected to the master device further branch and are connected to the shift register.

2. The serial communication system according to claim 1, wherein the master device and the shift register are further connected by a register clock signal line.

3. The serial communication system according to claim 2, wherein the shift register comprises m (where m is an integer of 2 or more) shift registers, each of the m shift registers controls the on / off state of some of the switch ICs of the n switch ICs, the one clock signal line and the one register clock signal line connected to the master device are each branched into m clock signal lines and m data signal lines, respectively, and connected to the m shift registers, and the master device and the m shift registers are daisy-chained by the branched data signal line.

4. The serial communication system according to claim 1, wherein the master device outputs a selection signal for selecting a specific switch IC from the n switch ICs using the one clock signal line and the one data signal line in a first serial communication method, the shift register controls the specific switch IC to an ON state in accordance with the selection signal, and after the specific switch IC has been controlled to an ON state, the master device communicates with a specific slave device via the specific switch IC using the one clock signal line and the one data signal line in a second serial communication method.

5. The serial communication system according to claim 2, wherein the master device outputs a selection signal for selecting a specific switch IC from the n switch ICs using the one clock signal line and the one data signal line in a first serial communication method, transitions the register clock signal line from inactive to active, the shift register latches the selection signal at the timing when the register clock signal line transitions from inactive to active, and controls the specific switch IC to an ON state according to the latched selection signal, the master device communicates with a specific slave device via the specific switch IC in a second serial communication method using the one clock signal line and the one data signal line after the specific switch IC has been controlled to an ON state, transitions the register clock signal line from active to inactive when communication with the specific slave device is completed, and the shift register resets the latched selection signal and turns off the specific switch IC at the timing when the register clock signal line transitions from active to inactive.

6. The serial communication system according to claim 4 or 5, wherein the first serial communication method is SPI (Serial Peripheral Interface) and the second serial communication method is I2C (Inter-Integrated Circuit).

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