A gate driving circuit and display device

Abstract

This disclosure provides a gate driving circuit and a display device, belonging to the field of display technology. The gate driving circuit includes multiple cascaded shift registers. Each shift register includes: a gate signal generation module configured to output a gate driving signal through a signal output terminal; and a voltage regulator module configured to, when the gate driving signal is at a working level, stabilize the output of the shift register at this stage by using a first power supply voltage output from a first power supply voltage terminal, stabilize the outputs of the previous and next stage shift registers by using a second power supply voltage output from a second power supply voltage terminal, and stabilize the output of the shift register at this stage by using a second power supply voltage output from a second power supply voltage terminal when the gate driving signal is not at a working level.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a gate driving circuit and a display device. Background Technology

[0002] Gate Drive on Array (GOA) technology is a commonly used technique in display panels that integrates the row scan drive signal circuitry onto the array substrate to drive the gate rows sequentially. Compared to traditional technologies, GOA eliminates the need for separate gate row drive chips by integrating the row scan drive signal circuitry onto the array substrate, resulting in significant cost savings. Furthermore, the absence of side row drive chips allows for narrower bezels in the display panel, better meeting aesthetic preferences.

[0003] Thin-film transistors (TFTs) are crucial components in display panels. They enable active control of individual pixels on the screen, precisely achieving the desired colors and grayscale levels, playing a vital role in the display panel. Since GOAs (Graphics On-Grid) are composed of numerous TFTs, unstable horizontal drive voltages due to TFT characteristic abnormalities are unavoidable. This problem becomes more pronounced during reliability testing (high temperature and humidity) and when process fluctuations occur. Summary of the Invention

[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a gate driving circuit and a display device.

[0005] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a gate driving circuit, including multiple cascaded shift registers, each of which includes:

[0006] A gate signal generation module is configured to output a gate drive signal through a signal output terminal;

[0007] A voltage regulator module is configured to, when the gate drive signal is at a working level, stabilize the output of the signal output terminal of the shift register in the same stage by outputting a first power supply voltage from a first power supply voltage terminal, stabilize the output of the signal output terminals of the shift register in the previous stage and the shift register in the next stage by outputting a second power supply voltage from a second power supply voltage terminal, and stabilize the output of the signal output terminal of the shift register in the same stage by outputting a second power supply voltage from a second power supply voltage terminal when the gate drive signal is at a non-working level.

[0008] In some embodiments, the voltage regulator module includes:

[0009] The first subunit is configured to stabilize the output of the signal output terminal of the shift register of this stage by the second power supply voltage output from the second power supply voltage terminal when the gate drive signal is at a non-working level.

[0010] The second subunit is configured to stabilize the output of the signal output terminal of the shift register of this stage by the first power supply voltage output from the first power supply voltage terminal when the gate drive signal is at the working level.

[0011] The third subunit is configured to stabilize the output of the signal output terminal of the previous stage shift register and the output of the signal output terminal of the next stage shift register by the second power supply voltage output from the second power supply voltage terminal when the gate drive signal is at the working level.

[0012] In some embodiments, the first sub-unit includes a first transistor; the control electrode of the first transistor is electrically connected to the signal output terminal of the shift register of this stage, the second sub-unit, and the third sub-unit; the first electrode of the first transistor is electrically connected to a second power supply voltage terminal; and the second electrode of the first transistor is electrically connected to the signal output terminal of the shift register of this stage.

[0013] In some embodiments, the second sub-unit includes a second transistor; the control electrode of the second transistor is electrically connected to the signal output terminal of the shift register of this stage, the first sub-unit, and the third sub-unit; the first electrode of the second transistor is electrically connected to the signal output terminal of the shift register of this stage; and the second electrode of the second transistor is electrically connected to the first power supply voltage terminal.

[0014] In some embodiments, the third sub-unit includes a third transistor; the control electrode of the third transistor is electrically connected to the signal output terminal of the shift register of this stage, the first sub-unit, and the second sub-unit; the first electrode of the third transistor is electrically connected to the signal output terminal of the shift register of the previous stage and the signal output terminal of the shift register of the next stage; and the second electrode of the third transistor is electrically connected to a second power supply voltage terminal.

[0015] In some embodiments, the gate signal generation module includes:

[0016] A pre-charge sub-circuit, connected to the pull-up node, is configured to pre-charge the pull-up node according to the input signal input to the signal input terminal;

[0017] A first reset sub-circuit is configured to reset the pull-up node according to a reset signal input to the reset signal input terminal;

[0018] The output sub-circuit, which is connected to the precharge sub-circuit at the pull-up node, is configured to send the clock control signal in the corresponding clock control signal line to the signal output terminal of the shift register at this stage under the control of the pull-up node potential, so that the signal output terminal can output the gate drive signal.

[0019] The second reset sub-circuit is configured to reset the signal output terminal of the shift register of this stage according to the reset signal input terminal.

[0020] In some embodiments, the precharge sub-circuit includes a fourth transistor; the control electrode and the second electrode of the fourth transistor are electrically connected to the signal input terminal, and the first electrode of the fourth transistor is connected to the output sub-circuit at a pull-up node.

[0021] In some embodiments, the first reset sub-circuit includes a fifth transistor; the control electrode of the fifth transistor is electrically connected to the reset signal input terminal, the first electrode of the fifth transistor is electrically connected to the third power supply voltage terminal, and the second electrode of the fifth transistor is connected to the precharge sub-circuit and the output sub-circuit at a pull-up node.

[0022] In some embodiments, the output sub-circuit includes a sixth transistor and a first capacitor; the control electrode of the sixth transistor is connected to the first plate of the first capacitor, the precharge sub-circuit, and the first reset sub-circuit at a pull-up node; the second electrode of the sixth transistor is electrically connected to a clock control signal line; and the first electrode of the sixth transistor is electrically connected to the second plate of the first capacitor and the second reset sub-circuit.

[0023] In some embodiments, the second reset sub-circuit includes a seventh transistor; the control electrode of the seventh transistor is electrically connected to the reset signal input terminal, the second electrode of the seventh transistor is electrically connected to the output sub-circuit, and the first electrode of the seventh transistor is electrically connected to the third power supply voltage terminal.

[0024] Secondly, embodiments of this disclosure also provide a display device, including a gate driving circuit as described in any of the above embodiments. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a gate drive circuit structure provided in an embodiment of the present disclosure;

[0026] Figure 2 for Figure 1 Schematic diagram of the middle gate drive circuit;

[0027] Figure 3 This is a schematic diagram of the circuit structure of the gate signal generation module in an embodiment of this disclosure;

[0028] Figure 4 for Figure 3 Timing diagram of the gate signal generation module;

[0029] Figure 5 This is a schematic diagram of a display device provided in an embodiment of the present disclosure.

[0030] The attached diagram is labeled as follows: GOA, shift register; 10, gate signal generation module; 11, pre-charge sub-circuit; 12, first reset sub-circuit; 13, output sub-circuit; 14, second reset sub-circuit; 20, voltage regulator module; 21, first sub-unit; 22, second sub-unit; 23, third sub-unit; VGH, first power supply voltage terminal; VGL, second power supply voltage terminal; CLK, clock control signal; Gate, gate line; Data, data line; PU, pull-up node; 01, driving transistor; VSS, third power supply voltage terminal; STV, signal input terminal; OUT, signal output terminal; RESET, reset signal input terminal; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; C1, first capacitor; LC, liquid crystal; C2, storage capacitor. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0033] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0034] The inventors discovered that since GOA is composed of a large number of TFTs, it is inevitable that there will be problems such as unstable line drive voltage due to abnormal TFT characteristics. This problem is more prominent during the reliability process (high temperature and high humidity) and when there are fluctuations in the process, which ultimately causes problems such as crosstalk and abnormal startup.

[0035] TFT characteristics are key parameters for evaluating the performance of a TFT and are important indicators for evaluating TFT devices. Ion (representing the turn-on current of the TFT, the higher the Ion, the better the turn-on characteristics of the TFT) and Ioff (representing the leakage current of the TFT, the lower the Ioff, the better the turn-off characteristics of the TFT) are the two most important parameters among TFT characteristics.

[0036] When a TFT is turned on, if its characteristics shift, it can easily lead to insufficient Ion, resulting in an excessively low horizontal turn-on voltage, ultimately preventing the TFT in that row from turning on properly. Conversely, when a TFT is turned off, if its characteristics shift, it can easily lead to excessive Ioff, resulting in an excessively high horizontal turn-off voltage, ultimately preventing the TFT in that row from turning off properly. For example, a rightward shift in the characteristic curve reduces the Ion of the TFTs in the display panel, and insufficient Ion can lead to poor low-temperature startup, or even poor startup at room temperature. Conversely, a leftward shift in the characteristic curve increases the Ioff of the TFTs in the display panel, and excessive Ioff can cause vertical crosstalk, flickering, and other problems in the display panel. Both of these abnormalities can lead to varying degrees of display abnormalities in the display panel.

[0037] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a gate drive circuit. Figure 1 This is a schematic diagram of a gate drive circuit structure provided in an embodiment of the present disclosure, as shown below. Figure 1 As shown, the gate drive circuit includes multiple cascaded shift registers (GOA_1 to GOA_N). For each shift register stage, there is a gate signal generation module 10 and a voltage regulator module 20. The gate signal generation module 10 is configured to output a gate drive signal through the signal output terminal OUT. The voltage regulator module 20 is configured to stabilize the output of the signal output terminal OUT of the shift register at this stage by outputting a first power supply voltage through the first power supply voltage terminal VGH when the gate drive signal is at the working level, stabilize the output of the signal output terminal OUT of the previous stage shift register and the output of the signal output terminal OUT of the next stage shift register by outputting a second power supply voltage through the second power supply voltage terminal VGL, and stabilize the output of the signal output terminal OUT of the shift register at this stage by outputting a second power supply voltage through the second power supply voltage terminal VGL when the gate drive signal output by the signal output terminal OUT is at the non-working level.

[0038] It should be noted that the working level is an effective signal level, and the non-working level is an invalid signal level. In the embodiments of this disclosure, the working level is when the gate drive signal is high and the non-working level is when the gate drive signal is low, which will not be repeated below.

[0039] It should be noted that in the embodiments of this disclosure, one of the first power supply voltage terminal VGH and the second power supply voltage terminal VGL is a high-voltage terminal, and the other is a low-voltage terminal. For example, the first power supply voltage terminal VGH can be a voltage source to output a constant positive voltage, while the second power supply voltage terminal VGL can be a voltage source to output a constant negative voltage. This embodiment of the disclosure uses the first power supply voltage terminal VGH as a voltage source to output a constant positive voltage and the second power supply voltage terminal VGL as a voltage source to output a constant negative voltage as an example; further details will not be elaborated upon below.

[0040] The gate drive circuit includes cascaded first-stage shift registers GOA_1 to nth-stage shift registers GOA_N. Figure 2 for Figure 1 A schematic diagram of the middle gate drive circuit is shown below. Figure 2 As shown, for ease of description and understanding, the gate drive circuit only shows the first-stage shift register GOA_1, the second-stage shift register GOA_2, and the third-stage shift register GOA_3, and the second-stage shift register GOA_2 is used as an example for specific explanation.

[0041] GOA_2 includes a gate signal generation module 10 and a voltage regulator module 20. The voltage regulator module 20 of GOA_2 is configured to stabilize the output of the signal output terminal OUT of GOA_2 by the first power supply voltage output by the first power supply voltage terminal VGH when the gate drive signal output by the signal output terminal OUT is at the working level, and stabilize the output of the signal output terminal OUT of GOA_1 and the signal output terminal OUT of GOA_3 by the second power supply voltage output by the second power supply voltage terminal VGL when the gate drive signal output by the signal output terminal OUT is at the non-working level.

[0042] Specifically, in this embodiment of the present disclosure, by adding a voltage regulator module 20 to the signal output terminal OUT of the gate signal generation module 10, bistable state of the gate drive signal can be achieved. Here, bistable state refers to the ability to stabilize both its on and off states. For example, when the gate drive signal output from the signal output terminal OUT of GOA_2 is at the working level, the voltage regulator module 20 inputs the first power supply voltage output from the first power supply voltage terminal VGH to the signal output terminal OUT of GOA_2 to stabilize the gate drive signal output from the gate signal generation module 10 of GOA_2 at a high level. At the same time, the voltage regulator module 20 inputs the second power supply voltage output from the second power supply voltage terminal VGL to the signal output terminals OUT of GOA_1 and GOA_3 to stabilize the gate drive signals output from the gate signal generation modules 10 of GOA_1 and GOA_3 at a low level. When the gate drive signal output from the signal output terminal OUT of GOA_2 is at a non-working level, the voltage regulator module 20 inputs the second power supply voltage output from the second power supply voltage terminal VGL to the signal output terminal OUT of GOA_2 to stabilize the gate drive signal output from the gate signal generation module 10 of GOA_2 at a low level.

[0043] Therefore, for GOA_2, when the gate drive signal output from its signal output terminal OUT is at the working level, the voltage regulation module 20 of this stage shift register can further stabilize the gate drive signal to a high level. At the same time, the voltage regulation module 20 of this stage shift register can further stabilize the gate drive signals output from the signal output terminals OUT of GOA_1 and GOA_3, which are adjacent to GOA_2, to a low level to prevent display abnormalities. When the gate drive signal output from the signal output terminal OUT of GOA_2 is at a non-working level, the voltage regulation module 20 of this stage shift register can further stabilize the gate drive signal to a low level. At the same time, the voltage regulation modules 20 of GOA_1 and GOA_3 can also further stabilize the gate drive signal output from the signal output terminal OUT of GOA_2 to a low level.

[0044] It is understandable that for GOA_1 (which has no preceding shift register), when the gate drive signal output from its signal output terminal OUT is at the working level, the voltage regulator module 20 of GOA_1 further stabilizes the gate drive signal to a high level. At the same time, the voltage regulator module 20 of this shift register further stabilizes the gate drive signal output from the adjacent signal output terminal OUT of GOA_2 to a low level to prevent display abnormalities. When the gate drive signal output from the signal output terminal OUT of GOA_1 is at a non-working level, the voltage regulator module 20 of this shift register further stabilizes the gate drive signal to a low level. At the same time, the voltage regulator module 20 of GOA_2 also further stabilizes the gate drive signal output from the signal output terminal OUT of GOA_1 to a low level.

[0045] For GOA_N (the last stage shift register), when the gate drive signal output from its signal output terminal OUT is at the working level, the voltage regulator module 20 of GOA_N further stabilizes the gate drive signal to a high level. At the same time, the voltage regulator module 20 of this stage shift register further stabilizes the gate drive signal output from the signal output terminal OUT of the (n-1)th stage shift register GOA_N-1, which is adjacent to GOA_N, to a low level to prevent display abnormalities. When the gate drive signal output from the signal output terminal OUT of GOA_N is at a non-working level, the voltage regulator module 20 of this stage shift register can further stabilize the gate drive signal to a low level. At the same time, the voltage regulator module 20 of GOA_N-1 will also further stabilize the gate drive signal output from the signal output terminal OUT of GOA_N to a low level.

[0046] Except for the first-stage shift register GOA_1 and the nth-stage shift register GOA_N, the specific principles of the other shift registers in implementing stable gate drive signals can be referred to the second-stage shift register GOA_2, which will not be repeated here.

[0047] The gate drive circuit in this embodiment achieves voltage self-stabilization of the output gate drive signal through the above settings, avoiding the loss of defective products caused by reliability processes (high temperature and high humidity) and fluctuations in the process environment, improving product yield, and avoiding problems such as vertical crosstalk, flickering, and poor startup, thereby obtaining better display effects.

[0048] In some embodiments, continue to refer to Figure 2 The voltage regulator module 20 includes a first subunit 21, a second subunit 22, and a third subunit 23. For each shift register stage, the first subunit 21 is configured to stabilize the output of the signal output terminal OUT of the shift register stage by using a second power supply voltage output from the second power supply voltage terminal VGL when the gate drive signal output from the signal output terminal OUT is at a non-operating level; the second subunit 22 is configured to stabilize the output of the signal output terminal OUT of the shift register stage by using a first power supply voltage output from the first power supply voltage terminal VGH when the gate drive signal output from the signal output terminal OUT is at an operating level; and the third subunit 23 is configured to stabilize the output of the signal output terminal OUT of the previous stage shift register and the output of the signal output terminal OUT of the next stage shift register by using a second power supply voltage output from the second power supply voltage terminal VGL when the gate drive signal output from the signal output terminal OUT is at an operating level.

[0049] Specifically, taking GOA_2 as an example, when the gate drive signal output from the signal output terminal OUT of GOA_2 is at a non-working level, the first sub-unit 21 responds to the non-working level signal by inputting the second power supply voltage output from the second power supply voltage terminal VGL to the signal output terminal OUT of GOA_2 to stabilize the gate drive signal output by the gate signal generation module 10 of GOA_2 at a low level. When the gate drive signal output from the signal output terminal OUT of GOA_2 is at a working level, the second sub-unit 22 responds to the working level signal by inputting the first power supply voltage output from the first power supply voltage terminal VGH to the signal output terminal OUT of GOA_2 to stabilize the gate drive signal output by the gate signal generation module 10 of GOA_2 at a high level. At the same time, the third sub-unit 23 responds to the working level signal by inputting the second power supply voltage output from the second power supply voltage terminal VGL to the signal output terminals OUT of GOA_1 and GOA_3, which are adjacent to GOA_2, to stabilize the gate drive signals output by the gate signal generation modules 10 of GOA_1 and GOA_3 at a low level.

[0050] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between their source and drain. In the embodiments of this disclosure and the following description, to distinguish the source and drain of the transistor, one of the terminals is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. In addition, according to the characteristics of the transistor, transistors can be divided into N-type and P-type. When a P-type transistor is used, the first terminal is the source of the P-type transistor, the second terminal is the drain of the P-type transistor, and the source and drain are turned on when a low-level signal is input to the gate. When an N-type transistor is used, the first terminal is the source of the N-type transistor, the second terminal is the drain of the N-type transistor, and the source and drain are turned on when a high-level signal is input to the gate.

[0051] In some embodiments, continue to refer to Figure 2 The first subunit 21 includes a first transistor M1, which is a P-type transistor. The control electrode of the first transistor M1 is electrically connected to the signal output terminal OUT of the shift register of this stage, the second subunit 22, and the third subunit 23. The first electrode of the first transistor M1 is electrically connected to the second power supply voltage terminal VGL, and the second electrode of the first transistor M1 is electrically connected to the signal output terminal OUT of the shift register of this stage.

[0052] Specifically, let's take GOA_2 as an example. When the gate drive signal output by the signal output terminal OUT of GOA_2 is at a non-working level, the control electrode of the first transistor M1 of the first sub-unit 21 receives the non-working level signal and turns on, inputting the second power supply voltage output by the second power supply voltage terminal VGL to the signal output terminal OUT of GOA_2, so as to stabilize the gate drive signal output by the gate signal generation module 10 of GOA_2 to a low level.

[0053] In some embodiments, continue to refer to Figure 2 The second subunit 22 includes a second transistor M2, which is an N-type transistor. The control electrode of the second transistor M2 is electrically connected to the signal output terminal OUT of the shift register of this stage, the first subunit 21, and the third subunit 23. The first electrode of the second transistor M2 is electrically connected to the signal output terminal OUT of the shift register of this stage, and the second electrode of the second transistor M2 is electrically connected to the first power supply voltage terminal VGH.

[0054] Specifically, let's take GOA_2 as an example. When the gate drive signal output by the signal output terminal OUT of GOA_2 is at the working level, the control electrode of the second transistor M2 of the second sub-unit 22 receives the working level signal and turns on, inputting the first power supply voltage output by the first power supply voltage terminal VGH to the signal output terminal OUT of GOA_2, so as to stabilize the gate drive signal output by the gate signal generation module 10 of GOA_2 to a high level.

[0055] In some embodiments, continue to refer to Figure 2 The third subunit 23 includes a third transistor M3, which is an N-type transistor. The control electrode of the third transistor M3 is electrically connected to the signal output terminal OUT of the shift register of this stage, the first subunit 21, and the second subunit 22. The first electrode of the third transistor M3 is electrically connected to the signal output terminal OUT of the previous stage shift register and the signal output terminal OUT of the next stage shift register. The second electrode of the third transistor M3 is electrically connected to the second power supply voltage terminal VGL.

[0056] Specifically, taking GOA_2 as an example, when the gate drive signal output from the signal output terminal OUT of GOA_2 is at the working level, the control electrode of the third transistor M3 of the third sub-unit 23 receives the working level signal and turns on, inputting the second power supply voltage output from the second power supply voltage terminal VGL to the signal output terminals OUT of GOA_1 and GOA_3, which are adjacent to GOA_2, so as to stabilize the gate drive signal output by the gate signal generation module 10 of GOA_1 and GOA_3 to a low level.

[0057] In some embodiments, Figure 3 This is a schematic diagram of the circuit structure of the gate signal generation module in an embodiment of this disclosure, as shown below. Figure 3 As shown, the gate signal generation module 10 includes a pre-charge sub-circuit 11, a first reset sub-circuit 12, an output sub-circuit 13, and a second reset sub-circuit 14. The pre-charge sub-circuit 11 and the output sub-circuit 13 are connected to the pull-up node PU. The pre-charge sub-circuit 11 is configured to pre-charge the pull-up node PU according to the input signal input at the signal input terminal STV; the first reset sub-circuit 12 is configured to reset the pull-up node PU according to the reset signal input at the reset signal input terminal RESET; the output sub-circuit 13 is configured to send the clock control signal in the corresponding clock control signal line to the signal output terminal OUT of the shift register at this stage under the control of the potential of the pull-up node PU, so that the signal output terminal OUT can output the gate drive signal; the second reset sub-circuit 14 is configured to reset the signal output terminal OUT of the shift register at this stage according to the reset signal input at the reset signal input terminal RESET.

[0058] In some embodiments, such as Figure 3As shown, the precharge sub-circuit 11 includes a fourth transistor M4, which is an N-type transistor. The control terminal and the second terminal of the fourth transistor M4 are electrically connected to the signal input terminal STV, and the first terminal of the fourth transistor M4 is connected to the pull-up node PU of the output sub-circuit 13.

[0059] It should be noted that for GOA_1, the input signal at the STV input terminal is the frame enable signal, and GOA_1 does not output a reset signal. Taking GOA_2 as an example, the input signal at the STV input terminal of GOA_2 is actually the output signal (gate drive signal) at the OUT output terminal of GOA_1.

[0060] In some embodiments, such as Figure 3 As shown, the first reset sub-circuit 12 includes a fifth transistor M5, which is an N-type transistor. The control electrode of the fifth transistor M5 is electrically connected to the reset signal input terminal RESET, the first electrode of the fifth transistor M5 is electrically connected to the third power supply voltage terminal VSS, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU along with the precharge sub-circuit 11 and the output sub-circuit 13.

[0061] In some embodiments, such as Figure 3 As shown, the output sub-circuit 13 includes a sixth transistor M6 and a first capacitor C1. The sixth transistor M6 is an N-type transistor. The control electrode of the sixth transistor M6 is connected to the first plate of the first capacitor C1, the precharge sub-circuit 11, and the first reset sub-circuit 12 at the pull-up node PU. The second electrode of the sixth transistor M6 is electrically connected to the clock control signal line, and the first electrode of the sixth transistor M6 is electrically connected to the second plate of the first capacitor C1 and the second reset sub-circuit 14.

[0062] In some embodiments, such as Figure 3 As shown, the second reset sub-circuit 14 includes a seventh transistor M7, which is an N-type transistor. The control electrode of the seventh transistor M7 is electrically connected to the reset signal input terminal RESET, the second electrode of the seventh transistor M7 is electrically connected to the output sub-circuit 13, and the first electrode of the seventh transistor M7 is electrically connected to the third power supply voltage terminal VSS.

[0063] The following is a detailed description of a complete embodiment of a gate signal generation module 10 in this disclosure.

[0064] Continue to refer to Figure 3The gate signal generation module 10 includes a pre-charge sub-circuit 11, a first reset sub-circuit 12, an output sub-circuit 13, and a second reset sub-circuit 14. The pre-charge sub-circuit 11 includes a fourth transistor M4, the first reset sub-circuit 12 includes a fifth transistor M5, the output sub-circuit 13 includes a sixth transistor M6 and a first capacitor C1, and the second reset sub-circuit 14 includes a seventh transistor M7. The pull-up node PU is the connection node between the control electrode of the sixth transistor M6 and the first plate of the first capacitor C1, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all N-type transistors.

[0065] Specifically, the control electrode and second electrode of the fourth transistor M4 are electrically connected to the signal input terminal STV. The first electrode of the fourth transistor M4, the second electrode of the fifth transistor M5, the control electrode of the sixth transistor M6, and the first plate of the first capacitor C1 are connected to the pull-up node PU. The control electrode of the fifth transistor M5 is electrically connected to the reset signal input terminal RESET. The first electrode of the fifth transistor M5 is electrically connected to the third power supply voltage terminal VSS. The second electrode of the sixth transistor M6 is electrically connected to the clock control signal line. The first electrode of the sixth transistor M6 is electrically connected to the second plate of the first capacitor C1 and the second electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is electrically connected to the reset signal input terminal RESET. The first electrode of the seventh transistor M7 is electrically connected to the third power supply voltage terminal VSS. In this embodiment, the third power supply terminal is the low-voltage terminal relative to the signal input terminal STV.

[0066] Figure 4 for Figure 3 The driving timing diagram of the gate signal generation module 10 is shown below, in conjunction with... Figure 3 and Figure 4 This will illustrate the specific operation of the gate signal generation module 10.

[0067] In the first stage T1, CLK = 1; STV = 0. Here, "0" represents a low level and "1" represents a high level, which will not be elaborated further below. At this time, the clock control signal line outputs a high level, and the input signal at the signal input terminal STV is a low level, meaning the output signal of the previous stage shift register has not yet been input to this stage shift register. The pull-up node PU is at a low potential, and the sixth transistor M6 is in the off state.

[0068] In the second stage T2, CLK = 0; STV = 1. At this time, the clock control signal line outputs a low level, and the input signal at the signal input terminal STV is a high level, meaning the output signal of the previous stage shift register is used as the input signal of this stage shift register. The fourth transistor M4 is turned on, and the potential of the pull-up node PU rises. However, because the clock control signal line outputs a low level, the signal output terminal OUT still does not output a high level.

[0069] In the third stage T3, CLK=1; STV=0. At this time, the clock control signal line outputs a high level, the input signal at the signal input terminal STV is at a low level, the potential of the pull-up node PU increases further, and the conduction capability of the sixth transistor M6 is enhanced, causing the signal output terminal OUT to output a high level.

[0070] In the fourth stage T4, CLK=0; STV=0; RESET=1. At this time, the clock control signal line outputs a low level, the input signal at the signal input terminal STV is low, the output signal of the next stage shift register serves as the reset signal for this stage shift register, causing the fifth transistor M5 and the seventh transistor M7 to conduct, the first capacitor C1 to discharge, and the signal output terminal OUT outputs a low level.

[0071] It should be noted that the gate signal generation module 10 of the shift register in this embodiment adopts a 4T1C (i.e., four transistors and one capacitor) structure. However, this embodiment does not impose special restrictions on the specific structure of the gate signal generation module 10, and improvements or modifications can be made based on this disclosure according to actual product requirements. For example, the gate signal generation module 10 can also adopt an 8T1C, 12T1C, or other circuit structures.

[0072] Secondly, embodiments of this disclosure also provide a display device, including a gate driving circuit as described in any of the above embodiments.

[0073] It should be noted that, in the embodiments of this disclosure, the display device can be an organic light-emitting diode display device or a liquid crystal display device, and this disclosure does not impose any special limitations on it. For example, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0074] Figure 5 This is a schematic diagram of a display device provided in an embodiment of the present disclosure, such as... Figure 5 As shown, a liquid crystal display device is used as an example. The display device includes pixel units located in the display area, and each pixel unit includes a pixel driving circuit. The display device also includes a gate driving circuit and a source driving circuit located in a peripheral area surrounding the display area. The gate driving circuit includes multiple cascaded shift registers connected to the gate line (Gate) to sequentially input scan signals to each row of pixel driving circuits. The source driving circuit provides data signals to each column of pixel driving circuits via the data line (Data).

[0075] Specifically, in this embodiment of the gate driving circuit, when the shift register outputs a high level, the driving transistor 01 corresponding to that row is turned on, and data signals are loaded into different columns to drive the liquid crystal LC for display; when the shift register outputs a low level, the driving transistor 01 corresponding to that row is turned off, and the liquid crystal LC stabilizes the current display state under the action of the storage capacitor C2.

[0076] The display device provided in this embodiment can achieve voltage self-stabilization of the output gate drive signal by using a gate drive circuit, thereby avoiding the loss of defective products caused by reliability processes (high temperature and high humidity) and fluctuations in the process environment, improving product yield, and avoiding problems such as vertical crosstalk, flickering, and poor startup, thus achieving better display effects.

[0077] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A gate driving circuit, comprising a plurality of cascaded shift registers, characterized in that, Each stage of the shift register includes: A gate signal generation module is configured to output a gate drive signal through a signal output terminal; A voltage regulator module is configured to, when the gate drive signal is at a working level, stabilize the output of the signal output terminal of the shift register in the same stage by outputting a first power supply voltage from a first power supply voltage terminal, stabilize the output of the signal output terminals of the shift register in the previous stage and the shift register in the next stage by outputting a second power supply voltage from a second power supply voltage terminal, and stabilize the output of the signal output terminal of the shift register in the same stage by outputting a second power supply voltage from a second power supply voltage terminal when the gate drive signal is at a non-working level.

2. The gate driving circuit according to claim 1, characterized in that, The voltage regulator module includes: The first subunit is configured to stabilize the output of the signal output terminal of the shift register of this stage by the second power supply voltage output from the second power supply voltage terminal when the gate drive signal is at a non-working level. The second subunit is configured to stabilize the output of the signal output terminal of the shift register of this stage by the first power supply voltage output from the first power supply voltage terminal when the gate drive signal is at the working level. The third subunit is configured to stabilize the output of the signal output terminal of the previous stage shift register and the output of the signal output terminal of the next stage shift register by the second power supply voltage output from the second power supply voltage terminal when the gate drive signal is at the working level.

3. The gate driving circuit according to claim 2, characterized in that, The first sub-unit includes a first transistor; the control electrode of the first transistor is electrically connected to the signal output terminal of the shift register of this stage, the second sub-unit, and the third sub-unit; the first electrode of the first transistor is electrically connected to the second power supply voltage terminal; and the second electrode of the first transistor is electrically connected to the signal output terminal of the shift register of this stage.

4. The gate driving circuit according to claim 2, characterized in that, The second subunit includes a second transistor; the control electrode of the second transistor is electrically connected to the signal output terminal of the shift register of this stage, the first subunit, and the third subunit; the first electrode of the second transistor is electrically connected to the signal output terminal of the shift register of this stage; and the second electrode of the second transistor is electrically connected to the first power supply voltage terminal.

5. The gate driving circuit according to claim 2, characterized in that, The third subunit includes a third transistor; the control electrode of the third transistor is electrically connected to the signal output terminal of the shift register of this stage, the first subunit, and the second subunit; the first electrode of the third transistor is electrically connected to the signal output terminal of the shift register of the previous stage and the signal output terminal of the shift register of the next stage; and the second electrode of the third transistor is electrically connected to the second power supply voltage terminal.

6. The gate driving circuit according to any one of claims 1-5, characterized in that, The gate signal generation module includes: A pre-charge sub-circuit, connected to the pull-up node, is configured to pre-charge the pull-up node according to the input signal input to the signal input terminal; A first reset sub-circuit is configured to reset the pull-up node according to a reset signal input to the reset signal input terminal; The output sub-circuit, which is connected to the precharge sub-circuit at the pull-up node, is configured to send the clock control signal in the corresponding clock control signal line to the signal output terminal of the shift register at this stage under the control of the pull-up node potential, so that the signal output terminal can output the gate drive signal. The second reset sub-circuit is configured to reset the signal output terminal of the shift register of this stage according to the reset signal input terminal.

7. The gate driving circuit according to claim 6, characterized in that, The pre-charge sub-circuit includes a fourth transistor; the control electrode and the second electrode of the fourth transistor are electrically connected to the signal input terminal, and the first electrode of the fourth transistor is connected to the output sub-circuit at a pull-up node.

8. The gate driving circuit according to claim 6, characterized in that, The first reset sub-circuit includes a fifth transistor; the control electrode of the fifth transistor is electrically connected to the reset signal input terminal, the first electrode of the fifth transistor is electrically connected to the third power supply voltage terminal, and the second electrode of the fifth transistor is connected to the pre-charge sub-circuit and the output sub-circuit at a pull-up node.

9. The gate driving circuit according to claim 6, characterized in that, The output sub-circuit includes a sixth transistor and a first capacitor; the control electrode of the sixth transistor is connected to the first plate of the first capacitor, the precharge sub-circuit, and the first reset sub-circuit at a pull-up node; the second electrode of the sixth transistor is electrically connected to a clock control signal line; and the first electrode of the sixth transistor is electrically connected to the second plate of the first capacitor and the second reset sub-circuit.

10. The gate driving circuit according to claim 6, characterized in that, The second reset sub-circuit includes a seventh transistor; the control electrode of the seventh transistor is electrically connected to the reset signal input terminal, the second electrode of the seventh transistor is electrically connected to the output sub-circuit, and the first electrode of the seventh transistor is electrically connected to the third power supply voltage terminal.

11. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1-10.

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