Shift register, gate drive circuit, array substrate and display device

Abstract

A shift register comprising a first input circuit, a second input circuit, a first output circuit, and an output control circuit. The first input circuit transmits an input signal from a signal input end to a first node under the control of a first clock signal end. The second input circuit transmits a signal from a second clock signal end to a second node under the control of the voltage at a third node. The first output circuit transmits the signal from the second clock signal end to a signal output end and transmits a signal from a first voltage signal end to the signal output end. The output control circuit transmits a second voltage signal from a second voltage signal end to the second node or to the signal output end under the control of a control signal end.

Description

Shift register, gate drive circuit, array substrate and display device

[0001] This application claims priority to Chinese patent application No. 202310961260.4, filed on August 1, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, an array substrate, and a display device. Background Art

[0003] The gate drive circuit is an important component of a display device. It can include multiple cascaded shift registers, each of which is electrically connected to a line in the display device. The gate drive circuit can input scan signals to multiple lines (e.g., gate lines or enable signal lines) in the display device row by row, enabling the display device to display images.

[0004] Summary of the Invention

[0005] In one aspect, a shift register is provided, comprising a first input circuit, a second input circuit, a control circuit, a first output circuit, and an output control circuit.

[0006] The first input circuit is coupled to a signal input terminal, a first clock signal terminal, and a first node, and is configured to transmit an input signal from the signal input terminal to the first node under control of a first clock signal from the first clock signal terminal.

[0007] The second input circuit is coupled to the second clock signal terminal, the second node, and the third node. The second input circuit is configured to transmit the second clock signal from the second clock signal terminal to the second node under the control of the voltage of the third node.

[0008] The first output circuit is coupled to the first node, the second node, a first voltage signal terminal, the second clock signal terminal, and a signal output terminal. The first output circuit is configured to transmit the second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node, and to transmit the first voltage signal from the first voltage signal terminal to the signal output terminal under the control of the voltage of the second node.

[0009] The output control circuit is coupled to the second voltage signal terminal and the control signal terminal, and is further coupled to the second node or the signal output terminal. The output control circuit is configured to transmit the second voltage signal from the second voltage signal terminal to the second node or the signal output terminal under the control of a control signal from the control signal terminal.

[0010] In some embodiments, the output control circuit is coupled to the second voltage signal terminal, the control signal terminal, and the second node. Of the voltage signals received by the first voltage signal terminal and the second voltage signal terminal, one is an operating voltage when the transistor is turned on, and the other is a non-operating voltage when the transistor is turned off.

[0011] In some embodiments, the output control circuit includes a ninth transistor, a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the second node, and a third electrode of the ninth transistor is electrically connected to the control signal terminal.

[0012] In some embodiments, the output control circuit is coupled to the second voltage signal terminal, the control signal terminal, and the signal output terminal. The voltage signal received by the first voltage signal terminal and the second voltage signal terminal is the same.

[0013] In some embodiments, the output control circuit includes a ninth transistor, a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the signal output terminal, and a third electrode of the ninth transistor is electrically connected to the control signal terminal.

[0014] In some embodiments, the first input circuit includes a first transistor, wherein a first electrode of the first transistor is electrically connected to the signal input terminal, a second electrode of the first transistor is electrically connected to the first node, and a third electrode of the first transistor is electrically connected to the first clock signal terminal. And / or, the second input circuit includes a second transistor and a first capacitor. The first electrode of the second transistor is electrically connected to the second clock signal terminal, the second electrode of the second transistor is electrically connected to the second node, and the third electrode of the second transistor is electrically connected to the third node. The first plate of the first capacitor is electrically connected to the second clock signal terminal, and the second plate of the first capacitor is electrically connected to the third node.

[0015] In some embodiments, the first output circuit includes a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor. The first electrode of the seventh transistor is electrically connected to the second clock signal terminal, the second electrode of the seventh transistor is electrically connected to the signal output terminal, and the third electrode of the seventh transistor is electrically connected to the first node. The first electrode of the eighth transistor is electrically connected to the first voltage signal terminal, the second electrode of the eighth transistor is electrically connected to the signal output terminal, and the third electrode of the eighth transistor is electrically connected to the second node. The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the signal output terminal. The first plate of the third capacitor is electrically connected to the second node, and the second plate of the third capacitor is electrically connected to the first voltage signal terminal.

[0016] In some embodiments, the shift register further includes a control circuit coupled to the first node, the second node, the third node, and the first voltage signal terminal. The control circuit is configured to, under control of the voltage from the first node, transmit the first voltage signal from the first voltage signal terminal to the second node and the third node, and, under control of the voltage from the second node, transmit the first voltage signal from the first voltage signal terminal to the first node.

[0017] In some embodiments, the control circuit includes a first control subcircuit and a second control subcircuit. The first control subcircuit is coupled to the first node, the second node, and the first voltage signal terminal. The first control subcircuit is configured to transmit a first voltage signal from the first voltage signal terminal to the first node under control of the voltage of the second node. The second control subcircuit is coupled to the first node, the second node, the third node, and the first voltage signal terminal. The second control subcircuit is configured to transmit the first voltage signal from the first voltage signal terminal to the second node and the third node under control of the voltage of the first node.

[0018] In some embodiments, the first control subcircuit is further coupled to the second clock signal terminal, and the first control subcircuit includes a third transistor and a fourth transistor. A first electrode of the third transistor is electrically connected to the first voltage signal terminal, a second electrode of the third transistor is electrically connected to the first node, and a third electrode of the third transistor is electrically connected to the second node. A first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor, a second electrode of the fourth transistor is electrically connected to the first node, and a third electrode of the fourth transistor is electrically connected to the second clock signal terminal.

[0019] And / or, the second control subcircuit includes a fifth transistor and a sixth transistor. A first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, a second electrode of the fifth transistor is electrically connected to the third node, and a third electrode of the fifth transistor is electrically connected to the first node. A first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, a second electrode of the sixth transistor is electrically connected to the second node, and a third electrode of the sixth transistor is electrically connected to the first node.

[0020] In another aspect, a gate driving circuit is provided, wherein the gate driving circuit includes a plurality of cascaded first shift registers, wherein the first shift registers are the shift registers described in any one of the above embodiments.

[0021] In some embodiments, except for the last stage of the first shift register, in every two adjacent stages of the first shift register, the control signal terminal of the first shift register of the previous stage is coupled to the signal output terminal of the first shift register of the next stage.

[0022] In some embodiments, the gate drive circuit further includes a second shift register, the second shift register including a first input circuit, a second input circuit, a control circuit, and a first output circuit. The signal input terminal of the second shift register is connected to the signal output terminal of the last-stage first shift register, and the control signal terminal of the last-stage first shift register is connected to the signal output terminal of the second shift register.

[0023] In another aspect, an array substrate is provided. The array substrate comprises a display area and a peripheral area located at least to one side of the display area. The array substrate includes a substrate and a gate drive circuit as described in any of the above embodiments, wherein the gate drive circuit is disposed on the substrate and located in the peripheral area.

[0024] In some embodiments, the array substrate further comprises a first voltage signal line and a second voltage signal line. The first voltage signal line is disposed on a side of the gate drive circuit away from the display area. The second voltage signal line overlaps with the gate drive circuit and divides the first shift register of the gate drive circuit into a first circuit and a second circuit, the first circuit being further away from the display area than the second circuit. The first circuit comprises a first input circuit, a second input circuit, a control circuit, and an output control circuit. The second circuit comprises a first output circuit.

[0025] In some embodiments, the control circuit includes a first control subcircuit and a second control subcircuit. The array substrate further includes a first active pattern. The first active pattern includes a first straight line segment, a second straight line segment, a third straight line segment, and a fourth straight line segment. The first straight line segment and the third straight line segment are both substantially parallel to the first voltage signal line, and the first straight line segment is closer to the first voltage signal line than the third straight line segment. The second straight line segment and the fourth straight line segment are both substantially perpendicular to the first voltage signal line.

[0026] The first straight segment includes a first portion and a second portion, the first portion and the second portion being located on opposite sides of the second straight segment. The ends of the second straight segment, the third straight segment, and the fourth straight segment are sequentially connected, and the third straight segment and the first portion are located on the same side of the second straight segment.

[0027] The active layers of the transistors included in the first control subcircuit are located in the second portion. Among the transistors included in the second control subcircuit, the active layers of some transistors are located in the first portion, and the active layers of other transistors are located in the third straight line segment.

[0028] In some embodiments, the output control circuit is coupled to the second voltage signal terminal, the control signal terminal, and the second node. The array substrate further includes a first gate line, a second gate line, and a second active pattern.

[0029] The first gate line is substantially perpendicular to the first voltage signal line. The first gate line overlaps the second portion and is connected to the second control subcircuit and the first output circuit. The second gate line is substantially perpendicular to the first voltage signal line. The second gate line is connected to the first voltage signal line and the first output circuit.

[0030] The second active pattern is substantially parallel to the first voltage signal line and is located between the first gate line and the second gate line. One end of the second active pattern is connected to the first gate line, and the other end is connected to the second voltage signal line. The active layer of the transistor included in the output control circuit is located in the second active pattern.

[0031] In some embodiments, the array substrate further comprises a second clock signal line, a third gate line, a first connection line and a first cascade line. The second clock signal line is disposed on a side of the gate drive circuit away from the display area and is substantially parallel to the first voltage signal line.

[0032] The third gate line is substantially perpendicular to the first voltage signal line. One end of the third gate line is connected to the second clock signal line, and the other end overlaps with the second portion. The first connecting line is connected to an end of the fourth straight line segment away from the third straight line segment, and is connected to an end of the third gate line away from the first voltage signal line.

[0033] In two adjacent shift registers, one end of the first cascade line overlaps with the second active pattern of the previous shift register, and the other end passes through the first connection line and the second voltage signal line and is connected to the signal output end of the next shift register.

[0034] In some embodiments, the first cascade line includes a fourth gate line and a second connecting line, wherein the fourth gate line is located between the first gate line and the second gate line. Furthermore, one end of the fourth gate line overlaps with the second active pattern, and the other end is connected to the second connecting line. The second connecting line is connected to the fourth gate line and a signal output terminal of a shift register of a next stage.

[0035] In some embodiments, the output control circuit is coupled to the second voltage signal terminal, the control signal terminal and the signal output terminal. The array substrate further includes a first gate line, a second gate line and a second active pattern.

[0036] The first gate line is substantially perpendicular to the first voltage signal line. The first gate line overlaps the second portion and is connected to the second control subcircuit and the first output circuit. The second gate line is substantially perpendicular to the first voltage signal line. The second gate line is connected to the first voltage signal line and the first output circuit.

[0037] The second active pattern is substantially perpendicular to the first voltage signal line and is located between the first gate line and the second gate line. One end of the second active pattern is connected to the signal output end, and the other end is connected to the first voltage signal line. The active layer of the transistor included in the output control circuit is located in the second active pattern.

[0038] In some embodiments, the array substrate further comprises a second clock signal line, a third gate line, a first connection line and a first cascade line. The second clock signal line is disposed on a side of the gate drive circuit away from the display area and is substantially parallel to the first voltage signal line.

[0039] The third gate line is substantially perpendicular to the first voltage signal line. One end of the third gate line is connected to the second clock signal line, and the other end overlaps with the second portion. The first connecting line is connected to an end of the fourth straight line segment away from the third straight line segment, and is connected to an end of the third gate line away from the first voltage signal line.

[0040] In two adjacent shift registers, one end of the first cascade line overlaps with the second active pattern of the shift register of the previous stage, and the other end passes through the first connecting line and the second voltage signal line and is connected to the second active pattern and signal output end of the next stage.

[0041] In some embodiments, the first cascade line includes a fourth gate line and a second connecting line. The fourth gate line is located between the first gate line and the second gate line. Furthermore, one end of the fourth gate line overlaps with the second active pattern, and the other end crosses another first cascade line to connect to the second connecting line. The second connecting line is connected to the fourth gate line and a signal output terminal of a shift register of the next stage.

[0042] In some embodiments, an end portion of the first connecting line connected to the fourth straight line segment is farther away from the first voltage signal line than an end portion connected to the third gate line.

[0043] In another aspect, a display device is provided, comprising the array substrate according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0045] FIG1 is a structural diagram of a display device according to some embodiments;

[0046] FIG2 is a structural diagram of another display device according to some embodiments;

[0047] FIG3 is a cross-sectional view taken along section line AA′ in FIG1 ;

[0048] FIG4 is a structural diagram of a display panel according to some embodiments;

[0049] FIG5 is a cross-sectional view taken along section line BB′ in FIG4 ;

[0050] FIG6 is a structural diagram of a gate driving circuit according to some embodiments;

[0051] FIG7 is a structural block diagram of a shift register according to some embodiments;

[0052] FIG8 is a block diagram of another structure of a shift register according to some embodiments;

[0053] FIG9 is a circuit diagram of the shift register shown in FIG7 ;

[0054] FIG10 is a circuit diagram of the shift register shown in FIG8 ;

[0055] FIG11 is a timing diagram of the shift register shown in FIG9 ;

[0056] FIG12 is a simulation comparison diagram of the output voltage of a signal output terminal in a floating stage according to the related art of some embodiments and the output voltage of a signal output terminal in a corresponding stage according to some embodiments of the present disclosure;

[0057] FIG13 is a circuit diagram of a second shift register according to some embodiments;

[0058] FIG14 is a structural diagram of a shift register of an array substrate according to some embodiments;

[0059] FIG15 is a structural diagram of another shift register of an array substrate according to some embodiments;

[0060] FIG16 is a structural diagram of the semiconductor layer of the array substrate shown in FIG14 and FIG15;

[0061] FIG17 is a structural diagram of a first gate conductive layer and a second gate conductive layer of the array substrate shown in FIG14 ;

[0062] FIG18 is a structural diagram of a first gate conductive layer and a second gate conductive layer of the array substrate shown in FIG15 ;

[0063] FIG19 is a structural diagram of the source-drain conductive layer of the array substrate shown in FIG14 ;

[0064] FIG. 20 is a structural diagram of the source-drain conductive layer of the array substrate shown in FIG. 15 . DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0066] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0067] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0068] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0069] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0070] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0071] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0072] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0073] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0074] As used herein, "about," "approximately," or "substantially" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0075] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0076] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0077] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0078] In this specification, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that, unless expressly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted as an ideal or overly formal meaning.

[0079] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0080] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0081] In the embodiments of the present disclosure, the transistors used may be thin film transistors (TFT), metal oxide semiconductors (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0082] In the embodiments of the present disclosure, the third electrode of each thin film transistor used is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0083] In the embodiments of the present disclosure, the capacitor may be a capacitive device fabricated separately through a process, for example, by fabricating specialized capacitive electrodes, each of which may be implemented through a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor may also be a parasitic capacitor between transistors, or implemented through the transistor itself and other devices or circuits, or through the parasitic capacitance between circuits within the circuit itself.

[0084] In the embodiments of the present disclosure, nodes such as the first node and the second node do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram.

[0085] In the embodiments of the present disclosure, “operating voltage” refers to a voltage that can turn on the operated transistor included therein; correspondingly, “non-operating voltage” refers to a voltage that cannot turn on the operated transistor included therein.

[0086] In the embodiments of the present disclosure, "low voltage" refers to a voltage that can turn on the operated P-type transistor included therein, but cannot turn on the operated N-type transistor included therein (i.e., the N-type transistor is turned off); correspondingly, "high voltage" refers to a voltage that can turn on the operated N-type transistor included therein, but cannot turn on the operated P-type transistor included therein (i.e., the P-type transistor is turned off).

[0087] In the following, in the circuits provided in the embodiments of the present disclosure, transistors are all described by taking P-type transistors as an example.

[0088] As shown in FIG. 1 and FIG. 2 , some embodiments of the present disclosure provide a display device 1000 . The display device 1000 may be any device that displays an image, whether in motion (eg, video) or fixed (eg, still image), and whether textual or graphic.

[0089] For example, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.

[0090] For example, as shown in FIG1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in FIG1 . For another example, referring to FIG2 , the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in FIG2 .

[0091] In the following, some embodiments of the present disclosure are schematically described by taking the display device 1000 as the mobile phone shown in FIG. 1 as an example, but the implementation manner of the present disclosure is not limited thereto.

[0092] In some embodiments, referring to FIG. 3 , a display device 1000 includes a display panel 100 .

[0093] The display panel 100 includes a light-emitting side and a non-light-emitting side that are opposite to each other. The light-emitting side is the side of the display panel 100 used for display, that is, the upper side in FIG3 .

[0094] For example, as shown in FIG3 , the display device 1000 may further include a housing 200 , a cover plate 300 , a circuit board 400 , and other electronic components.

[0095] 3 , the cover plate 300 may be a single-layer glass cover plate, or may include a stack of multiple sub-cover plates, which is not specifically limited in the embodiment of the present disclosure.

[0096] As shown in FIG3 , the longitudinal cross-section of the housing 200 may be, for example, U-shaped. The display panel 100 and the circuit board 400 are disposed within the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 is disposed on a side of the display panel 100 away from the cover plate 300, and is connected to the display panel 100 to provide the display panel 100 with the required display signals.

[0097] The display panel 100 may be of various types and may be selected according to actual needs.

[0098] Exemplarily, the display panel 100 may be any one of: an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a micro light emitting diode display panel, a liquid crystal display panel, a plasma display panel, a field emission display panel, an electrowetting display panel or an electrophoretic display panel, etc., and the embodiments of the present disclosure are not specifically limited here.

[0099] The following uses the above-mentioned display panel 100 as an organic light-emitting diode display panel as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited to this, and any other display panel 100 can also be considered as long as the same technical concept is applied.

[0100] 5 , the display panel 100 includes an array substrate 110 and an encapsulation layer 120 for encapsulating the array substrate 110. The encapsulation layer 120 may be an encapsulation film or an encapsulation substrate, which is not specifically limited in the present disclosure.

[0101] In some embodiments, referring to FIG. 4 and FIG. 5 , the array substrate 110 has a display area A. The display area A is a region for displaying images and is configured to dispose a plurality of sub-pixels P.

[0102] Exemplarily, referring to FIG. 4 and FIG. 5 , the array substrate 110 includes a substrate 11 and a plurality of sub-pixels P. The plurality of sub-pixels P are disposed on the substrate 11 and located in the display area A.

[0103] There are many types of substrates 11, which can be selected according to actual needs.

[0104] For example, the substrate 11 may be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0105] For another example, the substrate 11 may be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0106] The sub-pixel P includes a pixel circuit 130 and a light-emitting device 140. The sub-pixels P may be arranged in multiple rows and columns, with each row including multiple sub-pixels P arranged along a first direction X, and each column including multiple sub-pixels P arranged along a second direction Y. The first direction X intersects the second direction Y. For example, the first direction X is substantially perpendicular to the second direction Y.

[0107] It should be noted that the first direction X is the row direction in which the plurality of sub-pixels P are arranged, and the second direction Y is the column direction in which the plurality of sub-pixels P are arranged.

[0108] 4 , the array substrate 110 further includes a peripheral region B disposed on at least one side of the display region A. The peripheral region B is a region where no image is displayed and is configured to house a display driving circuit.

[0109] Exemplarily, referring to FIG. 4 , the array substrate 110 further includes a gate driving circuit 10 and a source driving circuit 20 disposed on the substrate 11 and located in the peripheral area B.

[0110] 4 and 6 , the gate driving circuit 10 includes multiple stages of cascaded shift registers RS, and one shift register RS ​​can be electrically connected to at least one row of sub-pixels P. For example, one shift register RS ​​is electrically connected to one row of sub-pixels P.

[0111] It should be noted that some shift registers RS (such as the second shift register RS2 in Figure 6) can also only serve to output cascade signals and are not connected to the sub-pixels P. Please refer to the following for details. No specific examples are given in the embodiments of the present disclosure.

[0112] Here, multi-stage cascade means that, in every two adjacent shift registers RS, the signal input terminal IN of the next stage shift register RS ​​is coupled to the signal output terminal OT of the previous stage shift register RS. The signal input terminal IN of the first stage shift register RS ​​is connected to the initialization signal line SL.

[0113] In some embodiments, referring to FIG. 4 , the array substrate 110 further includes a plurality of gate lines GL and a plurality of data lines DL disposed on the substrate 11 .

[0114] The gate lines GL extend substantially along the first direction X, and one gate line GL can be electrically connected to at least one row of sub-pixels P. The data lines DL extend substantially along the second direction Y, and one data line DL can be electrically connected to at least one column of sub-pixels P.

[0115] At this time, one shift register RS ​​in the gate driving circuit 10 may be electrically connected to a row of sub-pixels P through the gate lines GL, and the source driving circuit 20 may be electrically connected to a column of sub-pixels P through the data lines DL.

[0116] Based on the above, the gate driving circuit 10 can drive the sub-pixels P in each row from one side of the display area A, i.e., single-sided driving. The gate driving circuit 10 can also drive the sub-pixels P in each row from opposite sides of the display area A, i.e., cross driving. The gate driving circuit 10 can also drive the sub-pixels P in each row from opposite sides of the display area A, i.e., double-sided driving.

[0117] The following uses the single-sided driving mode of the gate driving circuit 10 as an example to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other driving modes can also be considered as long as the same technical concept is applied.

[0118] In the related art, when a gate driver circuit provides a signal to a gate line, there is a floating phase, in which the gate driver circuit does not provide any signal to the gate. During this floating phase, the voltage of the gate line is easily disturbed by coupling from other signal lines (such as data lines), causing voltage fluctuations (such as voltage drops) on the gate line, thereby affecting the stability of the output waveform of the entire gate driver circuit. This can cause data to be written incorrectly or fail to be written to the sub-pixel, affecting display quality.

[0119] Based on this, referring to FIG. 7 and FIG. 8 , some embodiments of the present disclosure provide a shift register RS, which includes a first input circuit 30 , a second input circuit 40 , a control circuit 50 , a first output circuit 60 , and an output control circuit 70 .

[0120] In some examples, referring to Figures 7 and 8 , the first input circuit 30 is coupled to the signal input terminal IN, the first clock signal terminal CK, and the first node N1. The first input circuit 30 is configured to transmit an input signal from the signal input terminal IN to the first node N1 under the control of a first clock signal from the first clock signal terminal CK.

[0121] Exemplarily, as shown in Figures 9 and 10, the first input circuit 30 includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, a second electrode of the first transistor T1 is electrically connected to the first node N1, and a third electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK.

[0122] 7 and 8 , the second input circuit 40 is coupled to the second clock signal terminal CB, the second node N2, and the third node N3. The second input circuit 40 is configured to transmit the second clock signal from the second clock signal terminal CB to the second node N2 under the control of the voltage of the third node N3.

[0123] For example, as shown in Figures 9 and 10, the second input circuit 40 includes a second transistor T2 and a first capacitor C1. A first electrode of the second transistor T2 is electrically connected to the second clock signal terminal CB, a second electrode of the second transistor T2 is electrically connected to the second node N2, and a third electrode of the second transistor T2 is electrically connected to the third node N3. A first plate of the first capacitor C1 is electrically connected to the second clock signal terminal CB, and a second plate of the first capacitor C1 is electrically connected to the third node N3.

[0124] In some examples, referring to Figures 7 and 8 , the control circuit 50 is coupled to the first node N1, the second node N2, the third node N3, and the first voltage signal terminal VGH. The control circuit 50 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3 under the control of the voltage from the first node N1. Furthermore, the control circuit 50 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the voltage from the second node N2.

[0125] Exemplarily, referring to FIG. 7 and FIG. 8 , the control circuit 50 includes a first control sub-circuit 51 and a second control sub-circuit 52 .

[0126] As shown in Figures 7 and 8, the first control sub-circuit 51 is coupled to the first node N1, the second node N2, and the first voltage signal terminal VGH. The first control sub-circuit 51 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the voltage of the second node N2.

[0127] For example, as shown in Figures 9 and 10, the first control sub-circuit 51 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to the first voltage signal terminal VGH, a second electrode of the third transistor T3 is electrically connected to the first node N1, and a third electrode of the third transistor T3 is electrically connected to the second node N2.

[0128] In addition, as shown in Figures 9 and 10, the first control sub-circuit 51 can also be coupled to the second clock signal terminal CB, and the first control sub-circuit 51 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the first node N1 under the control of the voltage of the second node N2 and the second clock signal of the second clock signal terminal CB.

[0129] At this time, as shown in Figures 9 and 10, the first control sub-circuit 51 further includes a fourth transistor T4. The second electrode of the third transistor T3 is electrically connected to the first electrode of the fourth transistor T4, and the second electrode of the fourth transistor T4 is electrically connected to the first node N1, thereby electrically connecting the second electrode of the third transistor T3 to the first node N1. The third electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB.

[0130] As shown in Figures 7 and 8, the second control sub-circuit 52 is coupled to the first node N1, the second node N2, the third node N3, and the first voltage signal terminal VGH. The second control sub-circuit 52 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3 under the control of the voltage of the first node N1.

[0131] For example, as shown in Figures 9 and 10, the second control subcircuit 52 includes a fifth transistor T5 and a sixth transistor T6. A first electrode of the fifth transistor T5 is electrically connected to the first voltage signal terminal VGH, a second electrode of the fifth transistor T5 is electrically connected to the third node N3, and a third electrode of the fifth transistor T5 is electrically connected to the first node N1. A first electrode of the sixth transistor T6 is electrically connected to the first voltage signal terminal VGH, a second electrode of the sixth transistor T6 is electrically connected to the second node N2, and a third electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0132] In some examples, referring to Figures 7 and 8, the first output circuit 60 is coupled to the first node N1, the second node N2, the first voltage signal terminal VGH, the second clock signal terminal CB, and the signal output terminal OT. The first output circuit 60 is configured to transmit the second clock signal from the second clock signal terminal CB to the signal output terminal OT under the control of the voltage of the first node N1. And, under the control of the voltage of the second node N2, transmit the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT.

[0133] Exemplarily, the first output circuit 60 includes a first output sub-circuit 61 and a second output sub-circuit 62 .

[0134] As shown in Figures 7 and 8, the first output sub-circuit 61 is coupled to the first node N1, the second clock signal terminal CB, and the signal output terminal OT. The first output sub-circuit 61 is configured to transmit the second clock signal from the second clock signal terminal CB to the signal output terminal OT under the control of the voltage of the first node N1.

[0135] For example, as shown in Figures 9 and 10, the first output sub-circuit 61 includes a seventh transistor T7 and a second capacitor C2. A first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OT, and a third electrode of the seventh transistor T7 is electrically connected to the first node N1. A first plate of the second capacitor C2 is electrically connected to the first node N1, and a second plate of the second capacitor C2 is electrically connected to the signal output terminal OT.

[0136] As shown in Figures 7 and 8, the second output sub-circuit 62 is coupled to the second node N2, the first voltage signal terminal VGH, and the signal output terminal OT. The second output sub-circuit 62 is configured to transmit the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT under the control of the voltage of the second node N2.

[0137] For example, as shown in Figures 9 and 10, the second output sub-circuit 62 includes an eighth transistor T8 and a third capacitor C3. A first electrode of the eighth transistor T8 is electrically connected to the first voltage signal terminal VGH, a second electrode of the eighth transistor T8 is electrically connected to the signal output terminal OT, and a third electrode of the eighth transistor T8 is electrically connected to the second node N2. A first plate of the third capacitor C3 is electrically connected to the second node N2, and a second plate of the third capacitor C3 is electrically connected to the first voltage signal terminal VGH.

[0138] In some examples, referring to Figures 7 and 8 , the output control circuit 70 is coupled to the second voltage signal terminal VS and the control signal terminal K, and is further coupled to the second node N2 or the signal output terminal OT. The output control circuit 70 is configured to transmit the second voltage signal from the second voltage signal terminal VS to the second node N2 or the signal output terminal OT under the control of the control signal from the control signal terminal K.

[0139] Exemplarily, as shown in FIG7 , the output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the second node N2 .

[0140] For example, as shown in Figure 9, the output control circuit 70 includes a ninth transistor T9, a first electrode of the ninth transistor T9 is electrically connected to the second voltage signal terminal VS, a second electrode of the ninth transistor T9 is electrically connected to the second node N2, and a third electrode of the ninth transistor T9 is electrically connected to the control signal terminal K.

[0141] On this basis, all transistors are P-type transistors or N-type transistors. Of the voltage signals received by the first voltage signal terminal VGH and the second voltage signal terminal VS, one is an operating voltage when the transistor is turned on, and the other is a non-operating voltage when the transistor is turned off.

[0142] For example, all transistors are P-type transistors, the first voltage signal received at the first voltage signal terminal VGH is a constant high voltage, and the second voltage signal received at the second voltage signal terminal VS is a constant low voltage, that is, the second voltage signal is smaller than the first voltage signal.

[0143] Exemplarily, as shown in FIG8 , the output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the signal output terminal OT.

[0144] For example, as shown in Figure 10, the output control circuit 70 includes a ninth transistor T9, a first electrode of the ninth transistor T9 is electrically connected to the second voltage signal terminal VS, a second electrode of the ninth transistor T9 is electrically connected to the signal output terminal OT, and a third electrode of the ninth transistor T9 is electrically connected to the control signal terminal K.

[0145] On this basis, the voltage signals received by the first voltage signal terminal VGH and the second voltage signal terminal VS are the same. For example, all transistors are P-type transistors, and the voltage signals received by the first voltage signal terminal VGH and the second voltage signal terminal VS are both constant high voltages.

[0146] In some embodiments, referring to Figures 9 and 10 , the shift register RS ​​further includes an isolation sub-circuit 80 coupled to the first node N1, the fourth node N4, and the third voltage signal terminal VGL. The first output sub-circuit 61 is coupled to the fourth node N4, i.e., the first output sub-circuit 61 is coupled to the first node N1 via the isolation sub-circuit 80.

[0147] The isolation sub-circuit 80 is configured to transmit the voltage from the first node N1 to the fourth node N4 under the control of the third voltage signal from the third voltage signal terminal VGL.

[0148] Exemplarily, as shown in Figures 9 and 10, the isolation sub-circuit 80 includes a tenth transistor T10, a first electrode of the tenth transistor T10 is electrically connected to the first node N1, a second electrode of the tenth transistor T10 is electrically connected to the third electrode of the seventh transistor T7, and a third electrode of the tenth transistor T10 is electrically connected to the third voltage signal terminal VGL.

[0149] It should be noted that the third voltage signal received at the third voltage signal terminal VGL is a constant operating voltage. For example, the tenth transistor T10 is a P-type transistor, and the third voltage signal received at the third voltage signal terminal VGL is a constant low voltage.

[0150] Fig. 11 is a timing diagram of the shift register shown in Fig. 9. The timing diagram of the shift register in some embodiments of the present disclosure is exemplarily described below with reference to Fig. 9 and Fig. 11.

[0151] As shown in FIG11 , in the first phase P1 , the input signal received by the input signal terminal IN is a low voltage, the first clock signal received by the first clock signal terminal CK is a low voltage, the second clock signal received by the second clock signal terminal CB is a high voltage, and the control signal received by the control signal terminal K is a high voltage.

[0152] At this time, with reference to Figure 9 , the first transistor T1 is turned on under the control of the first clock signal at the first clock signal terminal CK, transmitting the input signal from the signal input terminal IN to the first node N1, which is at a low voltage. The tenth transistor T10 is turned on, transmitting the low voltage at the first node N1 to the fourth node N4, which is at a low voltage. The seventh transistor T7 is turned on under the control of the voltage at the first node N1, transmitting the second clock signal received from the second clock signal terminal CB to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0153] In addition, the ninth transistor T9 is turned off under the control of the control signal of the control signal terminal K. Furthermore, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the voltage of the first node N1, transmitting the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3, respectively, so that the voltages of the second node N2 and the third node N3 are maintained at a high voltage. The second transistor T2, the third transistor T3, and the eighth transistor T8 are turned off.

[0154] As shown in FIG11 , in the second phase P2 , the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a high voltage, the second clock signal received by the second clock signal terminal CB is a low voltage, and the control signal received by the control signal terminal K is a high voltage.

[0155] At this time, referring to FIG9 , the first transistor T1 is turned off under the control of the first clock signal at the first clock signal terminal CK. The first node N1 maintains the voltage of the previous stage, i.e., the low voltage of the first stage P1. The fourth node N4 is still at a low voltage. The seventh transistor T7 is turned on under the control of the voltage at the first node N1, transmitting the second clock signal received from the second clock signal terminal CB to the signal output terminal OT. The signal output terminal OT outputs a low voltage.

[0156] In addition, the ninth transistor T9 is turned off under the control of the control signal of the control signal terminal K. Furthermore, the fifth transistor T5 and the sixth transistor T6 are turned on under the control of the voltage of the first node N1, transmitting the first voltage signal from the first voltage signal terminal VGH to the second node N2 and the third node N3, respectively, so that the voltages of the second node N2 and the third node N3 are maintained at a high voltage. The second transistor T2, the third transistor T3, and the eighth transistor T8 are turned off.

[0157] As shown in FIG11 , in the third phase P3 , the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a low voltage, the second clock signal received by the second clock signal terminal CB is a high voltage, and the control signal received by the control signal terminal K is a low voltage.

[0158] At this time, referring to FIG9 , the ninth transistor T9 is turned on under the control of the control signal of the control signal terminal K, transmitting the second voltage signal from the second voltage signal terminal VS to the second node N2, which is at a low voltage. The eighth transistor T8 is turned on, transmitting the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0159] Furthermore, the first transistor T1 is turned on under the control of the first clock signal of the first clock signal terminal CK, transmitting the input signal from the signal input terminal IN to the first node N1, which is at a high voltage. The tenth transistor T10 is turned on, transmitting the high voltage of the first node N1 to the fourth node N4, which is at a high voltage. The seventh transistor T7 is turned off.

[0160] As shown in FIG11 , in the fourth phase P4, the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a high voltage, the second clock signal received by the second clock signal terminal CB is a low voltage, and the control signal received by the control signal terminal K is a high voltage.

[0161] At this time, referring to FIG9 , the ninth transistor T9 is turned off under the control of the control signal from the control signal terminal K. Furthermore, the second transistor T2 is turned on under the control of the second clock signal from the second clock signal terminal CB, transmitting the second clock signal from the second clock signal terminal CB to the second node N2. The second node N2 is at a low voltage. The eighth transistor T8 is turned on, transmitting the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0162] Furthermore, the first transistor T1 is turned off under the control of the first clock signal at the first clock signal terminal CK, the third transistor T3 is turned on under the control of the second node N2, and the fourth transistor T4 is turned on under the control of the second clock signal at the second clock signal terminal CB. The first voltage signal at the first voltage signal terminal VGH is transmitted to the first node N1, so that the voltage of the first node N1 is maintained at a high voltage and the fourth node N4 is at a high voltage. The seventh transistor T7 is turned off.

[0163] As shown in FIG11 , in the fifth phase P5 , the input signal received by the input signal terminal IN is a high voltage, the first clock signal received by the first clock signal terminal CK is a low voltage, the second clock signal received by the second clock signal terminal CB is a high voltage, and the control signal received by the control signal terminal K is a high voltage.

[0164] At this time, referring to FIG. 9 , the ninth transistor T9 is turned off under the control of the control signal at the control signal terminal K, and the second transistor T2 is turned on and off under the control of the second clock signal at the second clock signal terminal CB. The second node N2 maintains the voltage of the previous stage, i.e., the low voltage of the fourth stage P4. The eighth transistor T8 is turned on under the control of the voltage at the second node N2, transmitting the first voltage signal from the first voltage signal terminal VGH to the signal output terminal OT. The signal output terminal OT outputs a high voltage.

[0165] Furthermore, the first transistor T1 is turned on under the control of the first clock signal of the first clock signal terminal CK, transmitting the input signal from the signal input terminal IN to the first node N1. The first node N1 is at a high voltage, and the fifth transistor T5 and the sixth transistor T6 are turned off. The fourth node N4 is at a high voltage. The seventh transistor T7 is turned off.

[0166] From the above, it can be seen that in the shift register RS ​​provided by the embodiment of the present disclosure, there is a voltage signal output at the signal output terminal OT in any stage, that is, the gate line GL does not have a floating stage. This can improve the stability of the output waveform of the shift register RS, improve the anti-interference stability of the shift register RS, reduce the risk of erroneous writing or writing failure of the sub-pixel P data, and thus improve the display quality.

[0167] FIG12 is a simulation comparison diagram of the output voltage of the signal output terminal in the floating stage according to the related art of some embodiments and the output voltage of the signal output terminal in the corresponding stage according to some embodiments of the present application.

[0168] As shown in FIG12 , in the related art, the voltage drop across the signal output terminal OT of the shift register RS ​​from other signal lines (e.g., the data line DL) is 1.2 V. In the present application, the voltage drop across the signal output terminal OT of the shift register RS ​​from other signal lines (e.g., the data line DL) is 0.5 V. Compared with the related art, the voltage drop fluctuation is reduced by 0.7 V. Therefore, the present application can significantly improve the stability of the output waveform of the shift register RS, improve the anti-interference stability of the shift register RS, reduce the risk of erroneous data writing or write failure in the sub-pixel P, and thus improve display quality.

[0169] In some embodiments of the present disclosure, the gate drive circuit 10 provided in FIG4 and FIG6 includes a multi-stage cascaded shift register RS ​​including a first shift register RS1, which is the shift register RS1 of any of the above embodiments. Each stage of the first shift register RS1 can be connected to a row of sub-pixels P, for example.

[0170] In some embodiments, referring to FIG6 , except for the last first shift register RS1, in every two adjacent first shift registers RS1, the control signal terminal K of the previous first shift register RS1 is coupled to the signal output terminal OT of the next first shift register RS1. This arrangement eliminates the need for a separate signal line for the control signal terminal K, simplifying circuit design.

[0171] 6 and 13 , the gate driving circuit 10 further includes a second shift register RS2, which includes a first input circuit 30, a second input circuit 40, a control circuit 50, and a first output circuit 60. That is, the second shift register RS2 does not include the output control circuit 70.

[0172] It should be noted that the second shift register RS2 may further include an isolation sub-circuit 80. The structures of the first input circuit 30, the second input circuit 40, the control circuit 50, the first output circuit 60 and the isolation sub-circuit 80 may be referred to above and will not be described in detail in this embodiment.

[0173] The signal input terminal IN of the second shift register RS2 is connected to the signal output terminal OT of the last first shift register RS1, and the control signal terminal K of the last first shift register RS1 is connected to the signal output terminal OT of the second shift register RS2.

[0174] It should be understood that the output signal terminal OT of the second shift register RS2 has a floating phase. Based on this, in some embodiments of the present disclosure, the signal output terminal OT of the second shift register RS2 is not connected to the sub-pixel P. The signal output terminal OT of the second shift register RS2 only provides a control signal to the control signal terminal K of the first shift register RS1 of the previous stage.

[0175] 14 and 15 , the array substrate 110 provided in some embodiments of the present disclosure further includes a first voltage signal line VL1 and a second voltage signal line VL2 , both of which extend substantially along the second direction Y.

[0176] It should be noted that the first voltage signal line VL1 is configured to provide a constant high voltage, and the second voltage signal line VL2 is configured to provide a constant low voltage.

[0177] As shown in Figures 4, 14, and 15, the first voltage signal line VL1 is disposed on a side of the gate driving circuit 10 that is away from the display area A. The second voltage signal line VL2 overlaps the gate driving circuit 10 and divides the first shift register RS1 of the gate driving circuit 10 into a first circuit 500 and a second circuit 600. The first circuit 500 is further away from the display area A than the second circuit 600.

[0178] At this time, as shown in Figures 6, 14 and 15, the first voltage signal terminal VGH is connected to the first voltage signal line VL1, the second voltage signal terminal VS is connected to the first voltage signal line VL1 or the second voltage signal line VL2, and the third voltage signal terminal VGL is connected to the second voltage signal line VL2.

[0179] In some embodiments, referring to Figures 14 and 15 , the array substrate 110 further includes a first clock signal line CL1, a second clock signal line CL2, and an initialization signal line SL. The first clock signal line CL1, the second clock signal line CL2, and the initialization signal line SL all extend substantially along the second direction Y, i.e., substantially parallel to the first voltage signal line VL1.

[0180] It should be noted that there can be multiple first clock signal lines CL1 and second clock signal lines CL2. Figures 14, 15, 19 and 20 only use one first clock signal line CL1 and one second clock signal line CL2 for example, and the embodiments of the present disclosure are not limited to this.

[0181] 4 , 14 and 15 , the first clock signal line CL1 , the second clock signal line CL2 and the initialization signal line SL are located on a side of the gate driving circuit 10 away from the display area A.

[0182] For example, as shown in FIG. 4 , FIG. 14 and FIG. 15 , the first clock signal line CL1 , the second clock signal line CL2 and the initialization signal line SL may be sequentially arranged away from the first voltage signal line VL1 .

[0183] At this time, as shown in Figures 6, 14 and 15, the first clock signal terminal CK is connected to the first clock signal line CL1, the second clock signal terminal CB is connected to the second clock signal line CL2, and the signal input terminal IN of the first-stage first shift register RS ​​is connected to the initialization signal line SL.

[0184] In some embodiments, referring to FIG. 16 , the array substrate 110 further includes a first active pattern 21 , a second active pattern 22 , a third active pattern 23 , a fourth active pattern 24 and a fifth active pattern 25 .

[0185] In some examples, as shown in FIG. 16 , the first active pattern 21 includes a first straight line segment 211 , a second straight line segment 212 , a third straight line segment 213 , and a fourth straight line segment 214 .

[0186] As shown in Figures 14, 15 and 16, the first straight line segment 211 and the third straight line segment 213 are both approximately parallel to the first voltage signal line VL1, and the first straight line segment 211 is closer to the first voltage signal line VL1 than the third straight line segment 213, and the second straight line segment 212 and the fourth straight line segment 214 are both approximately perpendicular to the first voltage signal line VL1.

[0187] In addition, as shown in Figure 16, the first straight line segment 211 includes a first part 2111 and a second part 2112, the first part 2111 and the second part 2112 are located on opposite sides of the second straight line segment 212, the ends of the second straight line segment 212, the third straight line segment 213 and the fourth straight line segment 214 are connected in sequence, and the third straight line segment 213 and the first part 2111 are located on the same side of the second straight line segment 212.

[0188] 9 , 14 , and 16 , the active layers of the transistors included in the first control subcircuit 51 are located in the second portion 2112 of the first straight line segment 211 in the first active pattern 21. For example, the active layers of the third transistor T3 and the fourth transistor T4 are located in the second portion 2112 of the first straight line segment 211 in the first active pattern 21.

[0189] 9 , 14 , and 16 , among the transistors included in the second control sub-circuit 52, the active layers of some of the transistors are located in the first portion 2111 of the first straight line segment 211 in the first active pattern 21, while the active layers of other transistors are located in the third straight line segment 213. For example, the active layer of the fifth transistor T5 is located in the first portion 1211, and the active layer of the sixth transistor T6 is located in the third straight line segment 213.

[0190] 9 , 14 and 16 , the active layers of the transistors included in the second input circuit 40 are located on the fourth straight line segment 214 . For example, the active layer of the second transistor T2 is located on the fourth straight line segment 214 .

[0191] In some examples, as shown in FIG. 14 and FIG. 16 , the second active pattern 22 may be located on a side of the first active pattern 21 away from the first voltage signal line VL1 .

[0192] 9 , 14 and 16 , the active layers of the transistors included in the output control circuit 70 are located in the second active pattern 22 . For example, the active layer of the ninth transistor T9 is located in the second active pattern 22 .

[0193] 9 , 14 , and 16 , the third active pattern 23 is located on a side of the first active pattern 21 close to the first voltage signal line VL1 , and the third active pattern 23 may be substantially parallel to the first voltage signal line VL1 .

[0194] At this time, the active layer of the transistor included in the first input circuit 30 is located in the third active pattern 23 . For example, the active layer of the first transistor T1 is located in the third active pattern 23 .

[0195] 9 , 14 , and 16 , the fourth active pattern 24 is located on a side of the second voltage signal line VL2 away from the first voltage signal line VL1 , and the fourth active pattern 24 may be substantially parallel to the first voltage signal line VL1 .

[0196] At this time, the active layers of the transistors included in the isolation sub-circuit 80 are located in the fourth active pattern 24 . For example, the active layer of the tenth transistor T10 is located in the fourth active pattern 24 .

[0197] 9, 14, and 16, the fifth active pattern 25 is located on a side of the fourth active pattern 24 away from the first voltage signal line VL1. The fifth active pattern 25 may include a plurality of sub-active patterns spaced apart along the first direction X.

[0198] At this time, the active layers of the transistors included in the first output circuit 60 are located in the fifth active pattern 25 . For example, the active layers of the seventh transistor T7 and the eighth transistor T8 are located in the fifth active pattern 25 .

[0199] In some embodiments, referring to Figures 14, 15, 17 and 18, the array substrate 110 further includes a first gate line 31, a second gate line 32, a third gate line 33, a fourth gate line 34, a fifth gate line 35, a sixth gate line 36, a seventh gate line 37, an eighth gate line 38, a ninth gate line 39, a tenth gate line 41 and an eleventh gate line 42.

[0200] In some examples, as shown in Figures 9, 14, and 17, the first gate line 31 is substantially perpendicular to the first voltage signal line VL1, overlaps the second portion 2112 of the first straight line segment 211 in the first active pattern 21, and is connected to the second control sub-circuit 52 and the first output circuit 60.

[0201] For example, as shown in Figures 9, 14, and 17, the first gate line 31 overlaps with the second portion 2112 of the first straight line segment 211 in the first active pattern 21 to form the third transistor T3. The third transistor T3 is connected to the connection node (second node N2) between the second transistor T2 and the sixth transistor T6, and is connected to the third electrode of the eighth transistor T8.

[0202] 9 , 14 and 17 , the array substrate 110 may further include a first plate and a second plate of a third capacitor C3 , wherein the first plate and the second plate at least partially overlap. The first gate line 31 is also connected to the first plate of the third capacitor C3 .

[0203] 9 , 14 , and 17 , the second gate line 32 is substantially perpendicular to the first voltage signal line VL1 . The second gate line 32 is connected to the first voltage signal line VL1 and the first output circuit 60 .

[0204] For example, as shown in FIG. 9 , FIG. 14 and FIG. 17 , the second gate line 32 is connected to the first voltage signal line VL1 and to the first electrode of the eighth transistor T8 .

[0205] 9 , 14 and 17 , the array substrate 110 may further include a first plate and a second plate of a third capacitor C3 , the first plate and the second plate at least partially overlapping. The second gate line 32 is also connected to the second plate of the third capacitor C3 .

[0206] In some examples, as shown in Figures 9, 14, and 17, the third gate line 33 is substantially perpendicular to the first voltage signal line VL1. The third gate line 33 is located between the first gate line 31 and the second gate line 32. One end of the third gate line 33 is connected to the second clock signal line CL2, and the other end overlaps with the second portion 2112 of the first straight line segment 211 in the first active pattern 21, forming a fourth transistor T4.

[0207] 9, 14, and 17, the fourth gate line 34 is located between the first gate line 31 and the second gate line 32. The fourth gate line 34 overlaps the second active pattern 22 to form the ninth transistor T9.

[0208] In some examples, as shown in Figures 9, 14, and 17, the fifth gate line 35 is substantially perpendicular to the first voltage signal line VL1. The fifth gate line 35 is located on a side of the first gate line 31 away from the second gate line 32, and one end of the fifth gate line 35 is connected to the first clock signal line CL1, and the other end overlaps with the third active pattern 23 to form the first transistor T1.

[0209] In some examples, as shown in Figures 9, 14, and 17, the sixth gate line 36 is substantially parallel to the first voltage signal line VL1. The sixth gate line 36 is located on a side of the fifth gate line 35 away from the first voltage signal line VL1 and overlaps the fourth straight line segment 214 to form the second transistor T2.

[0210] 9 , 14 and 17 , the array substrate 110 may further include a first plate and a second plate of the first capacitor C1 , the first plate and the second plate at least partially overlapping. The sixth gate line 36 is also connected to the second plate of the first capacitor C1 .

[0211] In some examples, as shown in FIG9 , FIG14 and FIG17 , the seventh gate line 37 overlaps the first portion 2111 and the third straight line segment 213 of the first active pattern 21 , respectively, to form the fifth transistor T5 and the sixth transistor T6 .

[0212] In some examples, as shown in FIG. 9 , FIG. 14 , and FIG. 17 , one end of the eighth gate line 38 is connected to the second voltage signal line VL2 , and the other end overlaps with the fourth active pattern to form the tenth transistor T10 .

[0213] In some examples, as shown in FIG. 9 , FIG. 14 , and FIG. 17 , the ninth gate line 39 overlaps the fifth active pattern 25 to form the seventh transistor T7 .

[0214] 9, 14 and 17, the array substrate 110 may further include a first plate and a second plate of a second capacitor C2, the first plate and the second plate at least partially overlapping. The ninth gate line 39 is also connected to the first plate of the second capacitor C2.

[0215] In some examples, as shown in FIG. 9 , FIG. 14 , and FIG. 17 , the tenth gate line 41 is connected to the first gate line 31 and overlaps the fifth active pattern 25 to form the eighth transistor T8 .

[0216] 9 , 14 and 17 , the array substrate 110 may further include a first plate and a second plate of a third capacitor C3 , wherein the first plate and the second plate at least partially overlap. The tenth gate line 41 is also connected to the first plate of the third capacitor C3 .

[0217] In some examples, as shown in FIG. 9 , FIG. 14 , and FIG. 17 , the eleventh gate line 42 is connected to the second electrodes of the seventh transistor T7 and the eighth transistor T8 , and extends between the first voltage signal line VL1 and the second voltage signal line VL2 .

[0218] In some embodiments, referring to Figures 14, 15, 19 and 20, the array substrate 110 also includes a first connecting line 71, a second connecting line 72, a third connecting line 73, a fourth connecting line 74, a fifth connecting line 75, a sixth connecting line 76, a seventh connecting line 77, an eighth connecting line 78, a ninth connecting line 79, a tenth connecting line 81 and an eleventh connecting line 82.

[0219] In some examples, as shown in Figures 14, 16, 17, and 19, the first connection line 71 is connected to the first electrode of the second transistor T2 and the third electrode of the fourth transistor T4. That is, the first connection line 71 is connected to the end of the fourth straight line segment 214 away from the third straight line segment 213, and is connected to the end of the third gate line 33 away from the first voltage signal line VL1.

[0220] It should be noted that the first connecting line 71 is connected to the first electrode plate of the first capacitor C1.

[0221] 14, 17, and 19, the array substrate 110 may further include a first capacitor C1 and a twelfth gate line 43. The twelfth gate line 43 is connected to a first connection line 71 and a first electrode of the seventh transistor T7. The first connection line 71 may also be connected to a first plate of the first capacitor C1.

[0222] Here, the end of the first connection line 71 connected to the fourth straight segment 214 is further away from the first voltage signal line VL1 than the end connected to the third gate line 33. In this way, the distance between the first connection line 71 and the second voltage signal line VL2 is greater, which is beneficial to the configuration of the output control circuit 70.

[0223] In some examples, as shown in Figures 14, 17, and 19, the second connection line 72 is connected to the fourth gate line 34 and the signal output terminal OT (see Figure 6) of the shift register RS ​​(see Figure 6) of the next stage. That is, one end of the second connection line 72 can be connected to the fourth gate line 34, and the other end can be connected to the portion between the eleventh gate line 42 of the shift register RS ​​(see Figure 6) of the next stage extending to the first voltage signal line VL1 and the second voltage signal line VL2.

[0224] In some examples, as shown in Figures 14, 16, 17, and 19, the third connection line 73 is connected to the second electrode of the first transistor T1 and the third electrodes of the fifth transistor T5 and the sixth transistor T6. That is, one end of the third connection line 73 can be connected to the third active pattern 23, and the other end can be connected to the seventh gate line 37.

[0225] In some examples, as shown in Figures 14, 17, and 19, the fourth connection line 74 is connected to the third electrodes of the fifth transistor T5 and the sixth transistor T6, and the second electrode of the fourth transistor T4. That is, one end of the fourth connection line 74 can be connected to the seventh gate line 37, and the other end can be connected to the second portion 2112 of the first straight line segment 211 in the first active pattern 21, away from the first portion 2111 of the first straight line segment 211 in the first active pattern 21.

[0226] In some examples, as shown in Figures 14, 16, 17, and 19, the fifth connection line 75 is connected to the second electrode of the fifth transistor T5 and the second plate of the first capacitor C1. That is, one end of the fifth connection line 75 can be connected to the first portion 2111 of the first straight line segment 211 in the first active pattern 21, away from the end of the second portion 2112 of the first straight line segment 211 in the first active pattern 21, and the other end can be connected to the second plate of the first capacitor C1.

[0227] In some examples, as shown in Figures 14, 16, 17, and 19, the sixth connection line 76 is connected to the second electrodes of the second transistor T2 and the sixth transistor T6, and the third electrodes of the third transistor T3 and the eighth transistor T8. That is, one end of the sixth connection line 76 can be connected to the inflection point of the third straight line segment 213 and the fourth straight line segment 214, and the other end can be connected to the first gate line 31.

[0228] In some examples, as shown in Figures 14, 16, 17, and 19, the seventh connection line 77 is connected to the second electrode of the tenth transistor T10 and the third electrode of the seventh transistor T7. That is, one end of the seventh connection line 77 can be connected to the fourth active pattern 24, and the other end can be connected to the ninth gate line 39.

[0229] In some examples, as shown in Figures 14, 16, 17, and 19, the eighth connection line 78 is connected to the first stage of the tenth transistor T10, the third electrode of the fifth transistor T5, and the sixth transistor T6. That is, one end of the eighth connection line 78 can be connected to the fourth active pattern 24, and the other end can be connected to the seventh gate line 37.

[0230] In some examples, as shown in Figures 14, 16, 17, and 19, the ninth connection line 79 is connected to the second plate of the third capacitor C3 and the first electrode of the eighth transistor T8. That is, one end of the ninth connection line 79 is connected to the second plate of the third capacitor C3, and the other end is connected to the fifth active pattern 25.

[0231] In some examples, as shown in Figures 14, 16, 17, and 19, the tenth connection line 81 is connected to the first electrode of the seventh transistor T7 and the second clock signal line CL2. In this case, the array substrate 110 may further include a twelfth gate line 43, which is connected to the first connection line 71 and the tenth connection line 81.

[0232] In some examples, as shown in Figures 14, 16, 17, and 19, the eleventh connection line 82 is connected to the second plate of the second capacitor C2, the second electrodes of the seventh transistor T7, and the eighth transistor T8, forming the signal output terminal OT. At this time, the eleventh gate line 42 is connected to the eleventh connection line 82.

[0233] In some embodiments, as shown in FIG. 9 and FIG. 14 , the output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the second node N2 .

[0234] 14, 16 and 17, the second active pattern 22 is substantially parallel to the first voltage signal line VL1. One end of the second active pattern 22 is connected to the first gate line 31, and the other end is connected to the second voltage signal line VL2.

[0235] Here, as shown in Figures 14, 16, 17 and 19, the above-mentioned array substrate 110 may further include a twelfth connecting line 83, the second active pattern 22 is connected to the twelfth connecting line 83, and the twelfth connecting line 83 is electrically connected to the first gate line 31, so that the second active pattern 22 is electrically connected to the first gate line 31.

[0236] In which, the above-mentioned array substrate 110 can also include a first cascade line 90. In the two adjacent shift registers RS, one end of the first cascade line 90 overlaps with the second active pattern 22 of the shift register RS ​​of the previous level, and the other end passes through the first connecting line 71 and the second voltage signal line VL2, and is connected to the signal output end OT of the shift register RS ​​of the next level.

[0237] At this time, the first cascade line 90 includes the second connection line 72 and the fourth gate line 34 , and the second connection line 72 is connected to the fourth gate line 34 and the signal output terminal OT of the next stage shift register RS.

[0238] In other embodiments, referring to FIG. 10 and FIG. 15 , the output control circuit 70 is coupled to the second voltage signal terminal VS, the control signal terminal K, and the signal output terminal OT.

[0239] 15 and 16 , the second active pattern 22 is substantially perpendicular to the first voltage signal line VL1 , and one end of the second active pattern 22 is connected to the signal output terminal OT (see FIG. 10 ) and the other end is connected to the first voltage signal line VL1 .

[0240] In which, the above-mentioned array substrate 110 can also include a first cascade line 90. In the two adjacent shift registers RS, one end of the first cascade line 90 overlaps with the second active pattern 22 of the shift register RS ​​of the previous level, and the other end is connected to the signal output end OT of the shift register RS ​​of the next level by passing through the first connecting line 71 and the second voltage signal line VL2.

[0241] At this time, as shown in Figures 15, 16, 18, and 20, the first cascade line 90 includes the second connecting line 72 and the fourth gate line 34. One end of the fourth gate line 34 overlaps with the second active pattern 22, and the other end crosses another first cascade line 90 and is connected to the second connecting line 72. The second connecting line 72 is connected to the fourth gate line 34 and the signal output terminal OT of the shift register RS ​​of the next stage.

[0242] Based on the above wiring design, the width of the first shift register RS1 is substantially equal to the width of the second shift register RS2 along the first direction X. In other words, the gate driver circuit 10 can be provided with an output control circuit 70 while maintaining the width in the first direction X. This improves the anti-interference stability of the gate driver circuit 10 and reduces the risk of erroneous data writing or data failure in the sub-pixels P, thereby improving display quality.

[0243] For example, when the maximum radial dimension of the sub-pixel P is 110 μm to 120 μm, the width of the gate driving circuit 10 along the first direction X is 380 μm to 390 μm.

[0244] Figure 5 is a cross-sectional view along section line BB' in Figure 4. The following schematically illustrates the film layers where the traces of the array substrate 110 are located in some embodiments of the present disclosure in conjunction with Figure 5, but the present disclosure is not limited thereto.

[0245] As shown in Figure 5, along the direction perpendicular to the substrate 11 and away from the substrate 11, the array substrate 110 includes a semiconductor layer ACT, a gate insulation layer GI, a first gate conductive layer GT1, a first interlayer insulating layer ILD1, a second gate conductive layer GT2, a second interlayer insulating layer ILD2, a source and drain conductive layer SD and a planar layer PLN, which are sequentially arranged on the substrate 11.

[0246] 5 and 16 , the first active pattern 21 , the second active pattern 22 , the third active pattern 23 , the fourth active pattern 24 and the fifth active pattern 25 are located in the semiconductor layer ACT.

[0247] 5 , 17 , and 18 , the first gate line 31 , the third gate line 33 , the fourth gate line 34 , the fifth gate line 35 , the sixth gate line 36 , the seventh gate line 37 , the eighth gate line 38 , the ninth gate line 39 , the tenth gate line 41 , the eleventh gate line 42 , and the twelfth gate line 43 are located in the first gate conductive layer GT1 . The second gate line 32 is located in the second gate conductive layer GT2 .

[0248] 5 , 19 and 20 , the first connecting line 71 , the second connecting line 72 , the third connecting line 73 , the fourth connecting line 74 , the fifth connecting line 75 , the sixth connecting line 76 , the seventh connecting line 77 , the eighth connecting line 78 , the ninth connecting line 79 , the tenth connecting line 81 , the eleventh connecting line 82 and the twelfth connecting line 83 are located in the source-drain conductive layer SD.

[0249] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A shift register, comprising: A first input circuit is coupled to the signal input terminal, the first clock signal terminal and the first node; The first input circuit is configured to transmit an input signal from the signal input terminal to the first node under the control of a first clock signal from the first clock signal terminal; A second input circuit is coupled to the second clock signal terminal, the second node and the third node; the second input circuit is configured to transmit the second clock signal from the second clock signal terminal to the second node under the control of the voltage of the third node; a first output circuit coupled to the first node, the second node, the first voltage signal terminal, the second clock signal terminal and the signal output terminal; the first output circuit is configured to transmit the second clock signal from the second clock signal terminal to the signal output terminal under the control of the voltage of the first node; and, under the control of the voltage of the second node, transmitting the first voltage signal from the first voltage signal terminal to the signal output terminal; An output control circuit is coupled to the second voltage signal terminal and the control signal terminal, and is also coupled to the second node or the signal output terminal; the output control circuit is configured to transmit the second voltage signal from the second voltage signal terminal to the second node or the signal output terminal under the control of the control signal from the control signal terminal.

2. The shift register according to claim 1, wherein: The output control circuit is coupled to the second voltage signal terminal, the control signal terminal and the second node; Of the voltage signals received by the first voltage signal terminal and the second voltage signal terminal, one is a working voltage when the transistor is turned on, and the other is a non-working voltage when the transistor is turned off.

3. The shift register according to claim 2, wherein: The output control circuit comprises: A ninth transistor, wherein a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the second node, and a third electrode of the ninth transistor is electrically connected to the control signal terminal.

4. The shift register according to claim 1, wherein: The output control circuit is coupled to the second voltage signal terminal, the control signal terminal and the signal output terminal; the voltage signals received by the first voltage signal terminal and the second voltage signal terminal are the same.

5. The shift register according to claim 4, wherein: The output control circuit comprises: A ninth transistor, wherein a first electrode of the ninth transistor is electrically connected to the second voltage signal terminal, a second electrode of the ninth transistor is electrically connected to the signal output terminal, and a third electrode of the ninth transistor is electrically connected to the control signal terminal.

6. The shift register according to any one of claims 1 to 5, wherein: The first input circuit comprises: a first transistor, wherein a first electrode of the first transistor is electrically connected to the signal input terminal, a second electrode of the first transistor is electrically connected to the first node, and a third electrode of the first transistor is electrically connected to the first clock signal terminal; And / or, the second input circuit comprises: a second transistor, wherein a first electrode of the second transistor is electrically connected to the second clock signal terminal, a second electrode of the second transistor is electrically connected to the second node, and a third electrode of the second transistor is electrically connected to the third node; A first capacitor, wherein a first plate of the first capacitor is electrically connected to the second clock signal terminal, and a second plate of the first capacitor is electrically connected to the third node.

7. The shift register according to any one of claims 1 to 6, wherein: The first output circuit comprises: a seventh transistor, wherein a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, a second electrode of the seventh transistor is electrically connected to the signal output terminal, and a third electrode of the seventh transistor is electrically connected to the first node; an eighth transistor, wherein a first electrode of the eighth transistor is electrically connected to the first voltage signal terminal, a second electrode of the eighth transistor is electrically connected to the signal output terminal, and a third electrode of the eighth transistor is electrically connected to the second node; a second capacitor, wherein a first plate of the second capacitor is electrically connected to the first node, and a second plate of the second capacitor is electrically connected to the signal output terminal; A third capacitor, wherein a first plate of the third capacitor is electrically connected to the second node, and a second plate of the third capacitor is electrically connected to the first voltage signal terminal.

8. The shift register according to any one of claims 1 to 7, further comprising: a control circuit coupled to the first node, the second node, the third node and the first voltage signal terminal; The control circuit is configured to transmit the first voltage signal from the first voltage signal terminal to the second node and the third node under the control of the voltage from the first node; And, under the control of the voltage from the second node, the first voltage signal from the first voltage signal terminal is transmitted to the first node.

9. The shift register according to claim 8, wherein: The control circuit comprises: a first control subcircuit coupled to the first node, the second node and the first voltage signal terminal; the first control subcircuit is configured to transmit a first voltage signal from the first voltage signal terminal to the first node under the control of the voltage of the second node; The second control subcircuit is coupled to the first node, the second node, the third node and the first voltage signal terminal; the second control subcircuit is configured to transmit the first voltage signal from the first voltage signal terminal to the second node and the third node under the control of the voltage of the first node.

10. The shift register according to claim 9, wherein: The first control subcircuit is also coupled to the second clock signal terminal, and the first control subcircuit includes: a third transistor, wherein a first electrode of the third transistor is electrically connected to the first voltage signal terminal, a second electrode of the third transistor is electrically connected to the first node, and a third electrode of the third transistor is electrically connected to the second node; a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to a second electrode of the third transistor, a second electrode of the fourth transistor is electrically connected to the first node, and a third electrode of the fourth transistor is electrically connected to the second clock signal terminal; And / or, the second control subcircuit includes: a fifth transistor, wherein a first electrode of the fifth transistor is electrically connected to the first voltage signal terminal, a second electrode of the fifth transistor is electrically connected to the third node, and a third electrode of the fifth transistor is electrically connected to the first node; A sixth transistor, wherein a first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, a second electrode of the sixth transistor is electrically connected to the second node, and a third electrode of the sixth transistor is electrically connected to the first node.

11. A gate driving circuit, comprising a plurality of cascaded first shift registers, wherein the first shift register is the shift register according to any one of claims 1 to 10.

12. The gate driving circuit according to claim 11, wherein: Except for the last stage of the first shift register, in every two adjacent stages of the first shift register, the control signal end of the first shift register of the previous stage is coupled to the signal output end of the first shift register of the next stage.

13. The gate driving circuit according to claim 12, further comprising: The second shift register comprises a first input circuit, a second input circuit, a control circuit and a first output circuit; wherein the signal input end of the second shift register is connected to the signal output end of the last-stage first shift register, and the control signal end of the last-stage first shift register is connected to the signal output end of the second shift register.

14. An array substrate having a display area and a peripheral area at least located on one side of the display area, the array substrate comprising: substrate; The gate driving circuit according to any one of claims 11 to 13, wherein the gate driving circuit is disposed on the substrate and is located in the peripheral area.

15. The array substrate according to claim 14, further comprising: A first voltage signal line is arranged on a side of the gate driving circuit away from the display area; a second voltage signal line, overlapping the gate driving circuit, and dividing the first shift register of the gate driving circuit into a first circuit and a second circuit, wherein the first circuit is farther away from the display area than the second circuit; The first circuit includes a first input circuit, a second input circuit, a control circuit and an output control circuit; the second circuit includes a first output circuit.

16. The array substrate according to claim 15, wherein: The control circuit includes a first control subcircuit and a second control subcircuit; the array substrate also includes: A first active pattern, comprising a first straight line segment, a second straight line segment, a third straight line segment and a fourth straight line segment, wherein the first straight line segment and the third straight line segment are both substantially parallel to the first voltage signal line, and the first straight line segment is closer to the first voltage signal line than the third straight line segment; and the second straight line segment and the fourth straight line segment are both substantially perpendicular to the first voltage signal line; The first straight line segment includes a first portion and a second portion, the first portion and the second portion are located on opposite sides of the second straight line segment, ends of the second straight line segment, the third straight line segment and the fourth straight line segment are connected in sequence, and the third straight line segment and the first portion are located on the same side of the second straight line segment; The active layers of the transistors included in the first control subcircuit are located in the second part; among the transistors included in the second control subcircuit, the active layers of some of the transistors are located in the first part, and the active layers of the other transistors are located in the second part. on the third straight line segment.

17. The array substrate according to claim 16, wherein: The output control circuit is coupled to the second voltage signal terminal, the control signal terminal and the second node; The array substrate further includes: a first gate line, substantially perpendicular to the first voltage signal line; the first gate line overlaps the second portion and is connected to the second control subcircuit and the first output circuit; A second gate line, substantially perpendicular to the first voltage signal line; the second gate line is connected to the first voltage signal line and the first output circuit; The second active pattern is substantially parallel to the first voltage signal line and is located between the first gate line and the second gate line; one end of the second active pattern is connected to the first gate line, and the other end is connected to the second voltage signal line; the active layer of the transistor included in the output control circuit is located in the second active pattern.

18. The array substrate according to claim 17, further comprising: A second clock signal line is arranged at a side of the gate driving circuit away from the display area and is substantially parallel to the first voltage signal line; A third gate line, which is substantially perpendicular to the first voltage signal line; one end of the third gate line is connected to the second clock signal line, and the other end of the third gate line overlaps with the second portion; a first connecting line connected to an end of the fourth straight line segment away from the third straight line segment, and connected to an end of the third gate line away from the first voltage signal line; The first cascade line, in two adjacent shift registers, one end of the first cascade line overlaps with the second active pattern of the previous shift register, and the other end passes through the first connecting line and the second voltage signal line and is connected to the signal output end of the next shift register.

19. The array substrate according to claim 18, wherein: The first cascade line includes a fourth gate line and a second connecting line, the fourth gate line is located between the first gate line and the second gate line; one end of the fourth gate line overlaps with the second active pattern, and the other end is connected to the second connecting line; the second connecting line is connected to the fourth gate line and a signal output end of a shift register of the next stage.

20. The array substrate according to claim 16, wherein: The output control circuit is coupled to the second voltage signal terminal, the control signal terminal and the signal output terminal; The array substrate further includes: a first gate line, substantially perpendicular to the first voltage signal line; the first gate line overlaps the second portion and is connected to the second control subcircuit and the first output circuit; A second gate line, substantially perpendicular to the first voltage signal line; the second gate line is connected to the first voltage signal line and the first output circuit; The second active pattern is substantially perpendicular to the first voltage signal line and is located between the first gate line and the second gate line. one end of the second active pattern is connected to the signal output end, and the other end is connected to the first voltage signal line; the active layer of the transistor included in the output control circuit is located in the second active pattern.

21. The array substrate according to claim 20, further comprising: A second clock signal line is arranged at a side of the gate driving circuit away from the display area and is substantially parallel to the first voltage signal line; A third gate line, which is substantially perpendicular to the first voltage signal line; one end of the third gate line is connected to the second clock signal line, and the other end of the third gate line overlaps with the second portion; a first connecting line connected to an end of the fourth straight line segment away from the third straight line segment, and connected to an end of the third gate line away from the first voltage signal line; A first cascade line, in two adjacent shift registers, one end of the first cascade line overlaps with the second active pattern of the shift register of the previous level, and the other end passes through the first connecting line and the second voltage signal line, and is connected to the second active pattern and the signal output end of the next level.

22. The array substrate according to claim 21, wherein: The first cascade line includes a fourth gate line and a second connecting line, the fourth gate line is located between the first gate line and the second gate line; and one end of the fourth gate line overlaps with the second active pattern, and the other end crosses another first cascade line to be connected to the second connecting line; the second connecting line is connected to the fourth gate line and a signal output end of a shift register of the next stage.

23. The array substrate according to any one of claims 18, 19, 21 or 22, wherein: The end portion of the first connecting line connected to the fourth straight line segment is further away from the first voltage signal line than the end portion connected to the third gate line.

24. A display device comprising the array substrate according to any one of claims 14 to 23.