Display panel

Abstract

A display panel includes a display array and a plurality of shift registers. The display array is disposed in an active area. The shift registers are disposed in the active area to drive the display array. Each shift register is divided into a plurality of driving sub-circuits. Each shift register includes a first sub-circuit and a second sub-circuit. The first sub-circuit is disposed in a first row of the display array, and all the first sub-circuits disposed in the first row are coupled to at least one global signal line. The second sub-circuit is disposed in a second row of the display array, and all the second sub-circuits disposed in the second row are concatenated into at least one string through a plurality of cross signal lines.

Description

Technical Field

[0001] This invention relates to a panel, and more particularly to a display panel. Background Technology

[0002] To accommodate narrow-bezel or borderless monitor designs, most modern monitors place the driving circuitry within the active area of ​​the display panel to reduce bezel size. Since the circuit area in the active area directly impacts display quality, balancing display quality with the need for smaller bezels has become a crucial design challenge for modern monitors. Summary of the Invention

[0003] This invention provides a display panel that can be applied to display sizes with narrow bezels or no bezels, while also ensuring display quality.

[0004] The display panel of the present invention includes a display array and a plurality of shift registers. The display array is disposed in an active area. The shift registers are disposed in the active area to drive the display array. Each shift register is divided into a plurality of driving sub-circuits. Each shift register includes a first sub-circuit and a second sub-circuit. The first sub-circuit is disposed in a first row of the display array, and all first sub-circuits in the first row are coupled to at least one global signal line. The second sub-circuit is disposed in a second row of the display array, and all second sub-circuits in the second row are connected in series to at least one column via a plurality of jumper signal lines.

[0005] Based on the above, sub-circuits on the same row can be connected by the same type of signal lines, so that these shift registers can be connected by simpler lines and fewer pins, which can reduce design complexity and save manufacturing costs. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the display panel according to Embodiment 1 of the present invention.

[0007] Figure 2A This is a circuit block diagram of a drive circuit according to an embodiment of the present invention.

[0008] Figure 2B for Figure 2A The operating waveform diagram of the middle column drive circuit.

[0009] Figure 3 This is a circuit diagram of a shift register according to Embodiment 1 of the present invention.

[0010] Figure 4A This is a schematic diagram of the layout of a drive circuit according to an embodiment of the present invention.

[0011] Figure 4B This is a schematic diagram of the layout of a drive circuit according to an embodiment of the present invention.

[0012] Explanation of reference numerals in the attached figures:

[0013] 1: Display panel

[0014] 10: Display Array

[0015] 11, 21: Column drive circuit

[0016] 210, 211: Serial

[0017] STA1, STA2, STB1, STB2: Start signals

[0018] AA: Active Region

[0019] PX: Pixel circuit

[0020] 41a, 41b: Column drive circuits

[0021] CK1~CK4: Clock signal lines

[0022] C1: Capacitor

[0023] Cm+1~Cm+3、Cm+4: rows

[0024] D2U, RST, VGH, VGL, U2D: Lines

[0025] Gx, Rx: Column drive signals

[0026] Jn~Jn+3: Jumper signal lines

[0027] RDn~RDn+3~RDn+9: Column driving lines

[0028] Rn~Rn+3: Columns

[0029] S1~S3: Sub-circuit

[0030] T1~T12: Transistors

[0031] SRn~SRn+3~SRn+9, SRx: Shift registers

[0032] VRD1~VRDn: Voltage Detailed Implementation

[0033] Figure 1This is a schematic diagram of a display panel 1 according to an embodiment of the present invention. The display panel 1 includes a display array 10 and a column driving circuit 11. The display array 10 includes a plurality of pixel circuits PX, which are arranged in rows and columns to form the display array 10 for display. On the other hand, the pixel circuits PX are disposed in an active area AA, which is actually the display area of ​​the display panel 1, where the display panel 1 can display images for the user to view. Furthermore, the column driving circuit 11 is also disposed in the active area AA and extends along the row direction. The column driving circuit 11 is used to drive each column of the display array 10. Although not explicitly shown... Figure 1 However, the column drive circuit 11 is actually formed by connecting multiple shift registers in series. Each shift register corresponds to each column of the display array 10 and is used to provide drive signals to each column of the display array 10.

[0034] In detail, Figure 1 This describes how the driving circuit 11 is located in the active area AA of the display panel 1 and extends along the row direction of the display array 10, spanning all columns of the display array 10. In one embodiment, the shift register in the driving circuit 11 can be divided into multiple sub-circuits, each arranged on a different row. More specifically, the transistors inside the shift register can be divided into multiple sub-circuits according to the type of coupled signal lines, so that the types of coupled signal lines for each sub-circuit are different and non-repetitive. Furthermore, for all shift registers, the sub-circuits coupled to the same signal lines can be arranged on the same row. For example, the shift register can be divided into a first sub-circuit coupled to a power rail and a second sub-circuit coupled to an output signal line. This allows the power rails supplied to the driving circuit 11 to be arranged only on the row where the first sub-circuit is located, thus effectively reducing the number of signal lines required by the driving circuit 11, thereby reducing manufacturing costs and improving display quality. The details of how the shift register is divided and the configuration of the driving circuit 11 will be described in detail later.

[0035] Figure 2A This is a circuit block diagram of a column driving circuit 21 according to an embodiment of the present invention. The column driving circuit 21 can be applied to... Figure 1 The display panel 1 is replaced with the column drive circuit 11 therein. Specifically, the column drive circuit 21 has two series columns 210 and 211, which drive the even-numbered and odd-numbered columns of the display array 10, respectively. Each series column 210 and 211 contains interconnected multi-stage shift registers. Each shift register can generate a column drive signal to drive the corresponding column of the display array 11. Therefore, the number of shift registers connected in series in the column drive circuit 21 corresponds to the number of columns in the display array 10. Although in Figure 2ATwo columns 210 and 211 are shown, but the number of columns can be increased or decreased according to different product requirements, and all of them fall within the scope of variations of the column drive circuit 21.

[0036] For ease of explanation, Figure 2A Only a portion of the column drive circuit 21 is shown, corresponding to columns n to n+9 of the display array; however, those skilled in the art can, of course, determine the appropriate path based on this information. Figure 2A The contents shown are used to infer the other parts of the column drive circuit 21. In detail, the shift registers SRn, SRn+2, SRn+4, SRn+6, and SRn+8 in the serial array 210 are coupled to the column drive lines RDn, RDn+2, RDn+4, RDn+6, and RDn+8, respectively. Similarly, the shift registers SRn+1, SRn+3, SRn+5, SRn+7, and SRn+9 in the serial array 211 are coupled to the column drive lines RDn+1, RDn+3, RDn+5, RDn+7, and RDn+9, respectively. Each shift register can be used to generate a column drive signal to the corresponding column drive line.

[0037] More specifically, the shift registers connected in series in columns 210 and 211 can receive start signals and, driven by each clock signal, sequentially pass the start signals to the next-level shift registers, thus generating sequentially enabled column drive signals. In this embodiment, column 210 can receive start signals STA2 and STB2. The transmission direction of column 210 can be controlled to transmit forward or backward. Thus, when the driving direction of column 210 is controlled to drive backward, column 210 can pass the received start signal STA2 backward to column n, column n+2, etc. When the driving direction of column 210 is controlled to drive forward, column 210 can pass the received start signal STB1 forward to column n+8, column n+6, etc. Similarly, column 211 can also be controlled to transmit one of the start signals STA1 and STB1 in either of the two transmission directions.

[0038] Figure 2B for Figure 2A The operating waveform diagram of the middle column drive circuit 21. Figure 2B The diagram shows the start signals STA1 and STA2, and the voltages VRD to VRDn on the column drive lines RD to RDn, respectively. In this embodiment, the strings 210 and 211 in the column drive circuit 21 are set in a backward transmission direction to transmit the received start signals STA2 and STA1, respectively. In other embodiments, the strings 210 and 211 in the column drive circuit 21 can be set in other transmission directions, and even the transmission directions of the two strings 210 and 211 can be set to the same or different transmission directions.

[0039] like Figure 2B As shown, the start signals STA1 and STA2 can be, for example, pulse signals or square waves with a positive half-cycle. As the start signal STA1 is provided to the serial line 211, the serial line 211 can sequentially provide the pulse of the start signal STA1 to the next stage (the next odd-numbered column) shift register in the next operating cycle. More specifically, when the (n+1)th stage shift register SRn+1 receives the pulse of the start signal STA1 from the shift register SRn-1, in addition to providing the pulse of the start signal STA1 to the shift register SRn+3, the (n+1)th stage shift register SRn+1 can simultaneously provide the pulse of the start signal STA1 to the corresponding column drive line RDn+1, thereby changing the voltage VRDn+1. Then, in the next operating cycle, the same operation can be repeated by the shift register SRn+3, so that the pulse of the start signal STA1 is continuously passed to the next stage. After the odd-numbered columns in the display array 10 are driven by the serial line 211, the start signal STA2 can be provided to the serial line 210, so that the serial line 210 drives the even-numbered columns of the display array 10.

[0040] Figure 3 This is a circuit diagram of a shift register SRx according to an embodiment of the present invention. The shift register SRx includes transistors T1 to T12 and capacitor C1. In this embodiment, the shift register SRx is divided into three sub-circuits S1 to S3 according to the type of coupled signal lines. Sub-circuit S1 can be coupled to the global signal lines, and includes power rails VGH and VGL, a reset signal line RST, an uplink control signal line D2U, and a downlink control signal line U2D. For example, power rails VGH and VGL can provide power to the display panel 1. The voltage on the reset signal line RST can be used to control whether the shift register SRx is reset. The voltages on the uplink control signal line D2U and the downlink control signal line U2D can be used together to control the direction of the shift register SRx transmitting the start signal, so as to determine whether the shift register SRx transmits the start signal to the previous stage (the previous odd / even column) or the next stage (the next odd / even column).

[0041] The element in sub-circuit S2 can be used to regulate the column drive signals Rx and Gx at the disabled voltage level at appropriate times. Figure 3 For example, this circuit architecture is constructed using P-type transistors. Therefore, the disable voltage level can be, for example, a relatively high voltage level on the power rail VGH, which is sufficient to cut off the P-type transistor. If an N-type transistor is used as an example, the disable voltage level can be, for example, a relatively low voltage level on the power rail VGL, which is sufficient to cut off the N-type transistor. Sub-circuit S3 can be used to receive the clock signal line CK and generate column drive signals Rx and Gx, while simultaneously controlling the operation of sub-circuit S2.

[0042] Figure 4A This is a schematic diagram of the layout of a drive circuit 41a according to an embodiment of the present invention. Figure 4A The column drive circuit 41a includes multiple stages of shift registers connected in series, and each shift register in the column drive circuit 41a can be, for example, a... Figure 3 The shift register SRn shown is similarly divided into sub-circuits S1 to S3. In this embodiment, for ease of explanation, Figure 4A Only a portion of the column drive circuit 41a is shown, corresponding to columns n to n+3 of the display array; however, those skilled in the art can, of course, determine the appropriate path based on this information. Figure 4A The contents shown can be used to infer the other parts of the column drive circuit 41a.

[0043] like Figure 4A As shown, in row m, all shift register sub-circuits S1 are set in row m, all shift register sub-circuits S2 are set in row m+1, and all shift register sub-circuits S3 are set in row m+2. Thus, refer to... Figure 3 As can be seen from the content, since the transistors in sub-circuit S1 operate by receiving power rails VGH and VGL, reset signal line RST, uplink control signal line D2U, and downlink control signal line U2D, these global signal lines can be set in the same row Cm of sub-circuit S1. In other words, the same global signal lines do not need to be set repeatedly, effectively reducing hardware costs.

[0044] In the (m+1)th row, the column drive circuit 41a can also set all the bridging signal lines in the (m+1)th row. In this embodiment, the number of columns bridging each bridging signal line is equal, so that the sub-circuit S2 of each shift register can provide the generated column drive signal to the shift registers of the preceding and following stages through the bridging signal lines. Specifically, since the sub-circuit S3 can generate a column drive signal Rx to drive the shift registers of the preceding and following stages, in this case, the column drive signal Rx can be provided to the shift registers of the preceding and following stages through the bridging signal lines. Taking the shift register SRn+1 in the (n+1)th column as an example, the sub-circuit S2 of the shift register SRn+1 can be coupled to the bridging signal lines Jn and Jn+2, so that the column drive signal Rn+1 can be provided to the shift registers SRn-1 and SRn+3 respectively through the bridging signal lines Jn and Jn+2.

[0045] In row m+2, the column driver circuit 41a sets up the sub-circuit S3 for all shift registers, which includes all the transistors in the shift registers that are controlled by the clock signal. In this way, the column driver circuit 41a can adaptively place all the clock signal lines CK1 to CK4 required by the shift registers in row m+3, thus avoiding the need for redundant clock signal lines and shortening the routing distance between the clock signal lines and each transistor, effectively reducing clock skew. For example, the sub-circuit S3 of shift registers SRn and SRn+1 can be coupled to clock signal line CK2, while the sub-circuit S3 of shift registers SRn+2 and SRn+3 can be coupled to clock signal line CK1.

[0046] On the other hand, the sub-circuit S3 located in the (m+2)th row can be coupled to the respective column drive lines to... Figure 3 The column drive signal Gx generated by the shift register SRx is provided to the corresponding column drive line. For example, the sub-circuit S3 of the shift register SRn can be coupled to the column drive line RDn, while the sub-circuit S3 of the shift register SRn+1 can be coupled to the column drive line RDn+1, and so on.

[0047] Therefore, the column driver circuit 41a can divide the shift registers therein into two driver groups, which are used to drive the odd columns and the even columns respectively. For the driver group driving the odd columns and the driver group driving the even columns, although the sub-circuit S2 is set in the (m+1)th row, the shift registers of different groups are connected in series through the sub-circuit S2 to form separate series columns.

[0048] In addition, although Figure 4A Only column drive circuit 41a is shown, but sub-circuits S1 to S3 in column drive circuit 41a can also be arranged corresponding to the rows and columns of display array 11. For example, rows Cm to Cm+3 can be aligned with or staggered with the rows in display array 11. Similarly, columns Rn to Rn+3 can be aligned with or staggered with the columns in display array 11.

[0049] On the other hand, grouping the transistors inside the column drive circuit 41a into corresponding rows according to the coupled signals can further reduce noise interference. Specifically, since the global signal line is only set in the first row, the interference of the global signal line to the sub-circuits set in other rows can be effectively reduced, thereby maintaining the stability of the column drive signal.

[0050] Figure 4B This is a schematic diagram of the layout of a drive circuit 41b according to an embodiment of the present invention. Figure 4B The column drive circuit 41b includes multiple stages of shift registers connected in series, and each shift register in the column drive circuit 41b can be, for example, a... Figure 3The shift register SRn shown is similarly divided into sub-circuits S1 to S3. In this embodiment, for ease of explanation, Figure 4B Only a portion of the column drive circuit 41b is shown, corresponding to columns n to n+3 of the display array; however, those skilled in the art can, of course, determine the appropriate path based on this information. Figure 4A The contents shown can be used to infer the other parts of the column drive circuit 41b.

[0051] Figure 4B The column drive circuit 41b is similar to Figure 4A The column drive circuit 41a is the same, so please refer to the above information regarding the same components and operation. Figure 4A The narrative paragraph. Figure 4B The column drive circuit 41b and Figure 4A The difference between the column driver circuit 41a and the column driver circuit 41b is that, in the column driver circuit 41b, the sub-circuit S2 used to drive the even-numbered rows is located in the (m+1)th row, and the sub-circuit S2 used to drive the odd-numbered rows is located in the (m+2)th row. Furthermore, all sub-circuits S3 are located in the (m+3)th row, and clock signal lines CK1 to CK4 are located in the (m+4)th row.

[0052] Specifically, the column driving circuit 41b can also be divided into a first driving group and a second driving group, driving even-numbered columns and odd-numbered columns respectively. The sub-circuit S2 of the first driving group can be set in the (m+1)th row. Through the interconnected sub-circuits S2 in the (m+1)th row, the shift registers of the first driving group can form a series and be used to drive the even-numbered columns in the display array 10. The sub-circuit S2 of the second driving group can be set in the (m+2)th row. Through the interconnected sub-circuits S2 in the (m+2)th row, the shift registers of the second driving group can form another series and be used to drive the odd-numbered columns in the display array 10. Thus, when the first driving group is enabled, the first group can sequentially transmit the start signal through the jumper signal lines in S2 to the shift registers of the next stage (the next even-numbered column) via the sub-circuit S3 in the (m+1)th row. Furthermore, when the second driving group is enabled, the second group can sequentially transmit the start signal to the shift register of the next stage (the next odd column) through the jumper signal line in S2 via the sub-circuit S3 in the (m+2)th row. Therefore, by using the sub-circuit S2 that are interleaved in the (m+1)th and (m+2)th rows, the shift registers of different groups can be used to drive the odd and even columns of the display array 1 respectively.

[0053] In summary, by appropriately grouping the internal circuitry of shift registers, transistors with the same coupling relationship are grouped into the same sub-circuit. Furthermore, these identical sub-circuits can be arranged in the same row. In other words, transistors with the same coupling relationship in different shift registers are arranged in the same row. This allows sub-circuits in the same row to be connected using the same type of signal lines, enabling these shift registers to operate with simpler wiring and fewer pins, reducing design complexity and manufacturing costs.

Claims

1. A display panel, comprising: A display array is set in an active area; as well as Multiple shift registers are disposed in the active area to drive the display array. Each shift register is divided into multiple driving sub-circuits, and each shift register includes: A first sub-circuit is disposed in a first row of the display array, and all first sub-circuits disposed in the first row are coupled to at least one global signal line, which is disposed only in the first row, and the same global signal line does not need to be disposed repeatedly; and A second sub-circuit is disposed in a second row of the display array, and all second sub-circuits disposed in the second row are connected in series to form at least one column via multiple jumper signal lines. Each of the second sub-circuits provides the generated drive signal to each of the shift registers in the preceding and following stages through each of the bridging signal lines.

2. The display panel as claimed in claim 1, wherein each of the shift registers further includes a third sub-circuit disposed in a third row of the display array, the third sub-circuit being respectively coupled to a plurality of column drive signal lines of the display array.

3. The display panel as claimed in claim 2, wherein a plurality of clock signal lines are further provided in a fourth row of the display array, extending along a row direction.

4. The display panel of claim 1, wherein each of the jumper signal lines spans at least one column of the display array.

5. The display panel of claim 4, wherein the bridging signal lines span the same number of columns.

6. The display panel of claim 4, wherein the shift register is divided into a plurality of drive groups, and a second sub-circuit of each drive group is connected in series in each of the series.

7. The display panel of claim 4, wherein the shift register comprises a plurality of first shift registers forming a first driving group, and the display panel further comprises a plurality of second shift registers forming a second driving group, each of the second shift registers comprising: A third sub-circuit is disposed in a third row of the display array, and the third sub-circuit of the second drive group is interleaved with the second sub-circuit of the first drive group.

8. The display panel as claimed in claim 7, wherein the first driving group is connected in series through a second sub-circuit to form a first array, and the second driving group is connected in series through a third sub-circuit to form a second array.

9. The display panel of claim 1, wherein when each of the columns is enabled, the shift registers of each column are controlled to sequentially provide a plurality of column drive signals to the display array.

10. The display panel of claim 1, wherein the at least one global signal line includes one of a power rail, a reset signal line, an uplink control signal line, and a downlink control signal line.

Images