Chip top layer structure

Abstract

The utility model discloses a kind of chip top layer structures, comprising: multiple chip modules, each chip module includes multiple pins;And wiring unit, including multiple signal lines for being connected with the pin of multiple chip modules, wherein, wiring unit includes first wiring area and second wiring area, logic signal line, noise signal line and clock signal line in the multiple signal lines are arranged in the first wiring area, sensitive signal line and quiet signal line in the multiple signal lines are arranged in the second wiring area, first wiring area and second wiring area are isolated by continuous isolation band between it.This chip top layer structure of the utility model realizes the inhibition between coupling noise of sensitive signal line and noise signal line and clock signal line and parasitic effect between signal line in layout level, while significantly reduce wiring resource occupancy and design complexity.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor chip layout design technology, and in particular to a chip top-level structure. Background Technology

[0002] With the development of microelectronics technology, chips are becoming increasingly larger, leading to a greater number of metal interconnect layers and more complex wiring on integrated circuit chip layouts. Integrated circuit layout is the intermediate link between integrated circuits and integrated circuit manufacturing processes. Through layout design, the integrated circuit system can be presented as a planar representation, which is then processed and manufactured into a chip with specific functions. Therefore, while ensuring the normal functionality of the integrated circuit design, layout design is becoming increasingly important. Layout design directly affects chip performance, cost, and design cycle. Improving the routing skills and work efficiency of layout design engineers and shortening the layout design cycle are crucial.

[0003] In actual large-scale top-level layout design, the top level often needs to simultaneously deploy signal lines of various functional categories, such as clock lines, high-speed interfaces, analog signals, power management lines, and debug buses, totaling thousands of lines. Because these signal lines extend in parallel physically with extremely small spacing, parasitic effects such as inter-line coupling capacitance, mutual inductance, and electromagnetic interference (EMI) are significantly amplified, which can easily lead to signal integrity (SI) degradation, increased clock jitter, decreased analog signal-to-noise ratio (SNR), and even functional failure.

[0004] To suppress the aforementioned parasitic coupling, one existing solution is to employ a "full-line shielding" strategy, which involves inserting a fixed-potential shielding net between signal lines of different functional categories. However, since shielding nets must be reserved on both sides of each signal line, the number of usable traces is drastically reduced. In scenarios with limited area or a fixed number of metal layers, the proportion of traces occupied by shielding nets can be as high as 10% to 20%, directly increasing chip size or forcing the addition of extra metal layers, significantly increasing manufacturing costs.

[0005] In addition, to reduce manufacturing costs, another existing solution is to simply shield or not shield between signal lines of different functional categories, extract the parasitic parameters between signal lines entirely through the layout, and repeatedly adjust the order of signal lines or add shielding lines based on the results of the extracted parasitic parameters. However, this will significantly increase the complexity of the design and the time cost. Utility Model Content

[0006] In view of the above problems, the purpose of this utility model is to provide a chip top-level structure that can not only suppress coupling noise and parasitic effects between sensitive signal lines, noise signal lines and clock signal lines at the layout level, but also significantly reduce wiring resource consumption and design complexity.

[0007] According to one aspect of the present invention, a chip top-level structure is provided, comprising: a plurality of chip modules, each chip module including a plurality of pins; and a wiring unit including a plurality of signal lines for connecting to the pins of the plurality of chip modules, wherein the wiring unit includes a first wiring area and a second wiring area, logic signal lines, noise signal lines and clock signal lines among the plurality of signal lines are arranged in the first wiring area, sensitive signal lines and quiet signal lines among the plurality of signal lines are arranged in the second wiring area, and the first wiring area and the second wiring area are isolated by a continuous isolation strip.

[0008] Optionally, the isolation band is formed by the logic signal line or the quiet signal line, which is arranged between the noise signal line or the clock signal line and the sensitive signal line.

[0009] Optionally, the isolation strip further includes a metal shielding wire independent of the signal line. The metal shielding wire includes a first shielding wire, a second shielding wire, and a third shielding wire. The first shielding wire extends continuously along the edge of the first wiring area away from the second wiring area. The second shielding wire is located at the boundary between the first wiring area and the second wiring area and extends continuously. The third shielding wire extends continuously along the edge of the second wiring area away from the first wiring area, so that the first wiring area and the second wiring area are each sandwiched between two adjacent shielding wires.

[0010] Optionally, the width of the metal shielding wire is equal to the width of the adjacent signal wire.

[0011] Optionally, the metal shielding wire is made of at least one of aluminum, copper, or an aluminum-copper alloy.

[0012] Optionally, the top-level structure of the chip further includes: a plurality of connecting lines perpendicular to the plurality of signal lines, one end of each connecting line being connected to one of the plurality of signal lines through a via, and the other end being connected to a pin of the same functional category in the plurality of chip modules.

[0013] In summary, the chip top-level structure of this utility model physically divides the wiring unit into a first wiring area and a second wiring area. The active signal lines among the multiple signal lines are arranged in the first wiring area, and the protected signal lines among the multiple signal lines are arranged in the second wiring area. By using isolation strips to electrically isolate the first wiring area and the second wiring area, the coupling noise and parasitic effects between the active signal lines and the protected signal lines are suppressed at the layout level, while significantly reducing the wiring resource occupation and design complexity.

[0014] Furthermore, the chip top-level structure of this invention directly labels the functional categories of the signal lines in the corresponding pin names of the multiple chip modules with additional prefixes or suffixes. This ensures that a unified functional category naming rule is followed throughout the design and layout stages, enabling circuit designers and layout engineers to instantly identify the functional categories of the signal lines, automatically call the corresponding spacing and shielding configurations, avoid human error, shorten the design iteration cycle, and improve work efficiency, thereby achieving a balance between high performance, high reliability, and low cost. Attached Figure Description

[0015] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0016] Figure 1 A schematic structural diagram of the chip top-level structure according to the first embodiment of the present invention is shown.

[0017] Figure 2 A schematic structural diagram of the chip top-level structure according to the second embodiment of the present invention is shown. Detailed Implementation

[0018] Various embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0021] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0022] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0023] Figure 1 A schematic structural diagram of the chip top-level structure according to a first embodiment of the present invention is shown. Figure 1 The chip top-level structure 100 includes multiple chip modules (e.g., chip modules 101 to 103) and a wiring unit 110. Each chip module includes multiple pins, and the wiring unit 110 has multiple signal lines for connecting to the pins of the multiple chip modules 101 to 103. The multiple signal lines are divided into active signal lines and protected signal lines according to their sensitivity to noise. The active signal lines are arranged in groups in parallel on one side of the wiring unit 110, and the protected signal lines are arranged in groups in parallel on the other side of the wiring unit 110. The active signal lines and the protected signal lines are isolated from each other by a continuous isolation band.

[0024] For example, the multiple signal lines are pre-divided according to function into Sensitive Net (SN), Quiet Net (QN), Logic Net (LN), Noise Net (NN), and Clock Net (CLN).

[0025] The active signal lines include logic signal line LN, noise signal line NN, and clock signal line CLN, while the protected signal lines include quiet signal line QN and sensitive signal line SN. Furthermore, this classification is based on the electrical characteristics, noise tolerance, and sensitivity to crosstalk of the signals in the circuit, ensuring that differentiated routing strategies can be intuitively identified and implemented during the layout stage. Sensitive signal lines (SN) typically carry high-precision analog or digital signals, such as reference voltage or reference current signals. These signals are extremely sensitive to noise during operation and are easily altered by external noise, reducing the stability and accuracy of the chip. Quiet signal lines (QN) typically carry analog signals in a stable state, such as test voltage or test current signals. These signals generate almost no switching noise during operation and are not affected by external noise. Logic signal lines (LN) typically carry conventional digital signals, such as trimming or enable signals. These signals are mostly in a stable state during chip operation and only undergo logic transitions when needed. Noisy signal lines (NN) typically carry high-current drive or high-speed switching signals, such as the bootstrap voltage signal in a switching power supply chip, which are prone to radiating interference. Clock signal lines (CLN) typically carry clock signals that jump back and forth. Due to their strong periodicity and steep edges, they are one of the main sources of noise.

[0026] Furthermore, to reduce coupling interference between signal lines of different functional categories, the top-level routing structure of this embodiment introduces a shielding mechanism at the layout level. Specifically, the routing unit 110 is physically divided into a first routing area 111 and a second routing area 112. The first routing area 111 and the second routing area 112 are electrically isolated by an isolation strip, thereby achieving functional partitioning at the layout level. For example, the first routing area 111 is centrally located for active signal lines such as the clock signal line CLN, noise signal line NN, and logic signal line LN. These signal lines are classified as potential interference sources due to frequent switching activities or large currents. The second routing area 112 is specifically used to house protected signal lines such as the quiet signal line QN and the sensitive signal line SN to reduce their risk of crosstalk. This partitioning method allows layout design engineers to quickly complete routing based on area attributes during the routing stage, without having to evaluate the coupling strength between signals line by line, significantly improving design efficiency.

[0027] Furthermore, the isolation band consists of a metal shielding wire independent of the signal line. The metal shielding wire is made of at least one of aluminum, copper, or an aluminum-copper alloy. The metal shielding wire can extend continuously at the boundary between the first wiring area 111 and the second wiring area 112 and connect to the chip's ground ring or stable power network, thereby forming a low-impedance shielding wall between the first wiring area 111 and the second wiring area 112 that has no electrical connection to any functional signal line. For example, the width of the metal shielding wire is set to be equal to the width of the adjacent signal line to balance shielding effectiveness and wiring resource usage, and its extension length at least covers the entire overlapping area of ​​the first wiring area 111 and the second wiring area 112 projected on the top layer of the chip, ensuring that the lateral coupling path between the active signal line and the protected signal line is completely blocked.

[0028] Further, the metal shielding wire includes a first shielding wire 113, a second shielding wire 114, and a third shielding wire 115. The first shielding wire 113 extends continuously along the edge of the first wiring area 111 away from the second wiring area 112; the second shielding wire 114 is located at the boundary between the first wiring area 111 and the second wiring area 112 and extends continuously; the third shielding wire 115 extends continuously along the edge of the second wiring area 112 away from the first wiring area 111, such that the first wiring area 111 and the second wiring area 112 are each sandwiched between two adjacent shielding wires.

[0029] Figure 2 A schematic structural diagram of the chip top-level structure according to a second embodiment of the present invention is shown. In another embodiment, the isolation band is formed by the logic signal line LN or the quiet signal line QN, which is arranged between the noise signal line NN or the clock signal line CLN and the sensitive signal line SN, thereby eliminating the need for the second shielding line 114 between the first wiring area 111 and the second wiring area 112. Specifically, during the layout design stage, the logic signal line LN originally used for functional transmission or the quiet signal line QN in a constant logic state is continuously arranged along the boundary between the first wiring area 111 and the second wiring area 112, so that it acts as a shielding barrier in physical location, thereby effectively suppressing coupling noise and parasitic effects between signal lines. Since the logic signal line or the quiet signal line itself already has a defined network connection, there is no need to introduce an additional dedicated metal line, thus saving one metal resource while maintaining the original function and reducing layout congestion.

[0030] To further enhance the reliability of this "functional and shielded" structure, the routing of the logic signal line LN or quiet signal line QN at the junction is implemented as a continuous, uninterrupted straight line segment, the length of which at least covers the entire projected overlap area between the clock signal line CLN or noise signal line NN and the sensitive signal line SN.

[0031] Continue to refer to Figure 1 and Figure 2 The chip top-level structure 100 in this embodiment also includes multiple connection lines 121 and multiple vias 122. The multiple connection lines 121 and the multiple vias 122 are used to connect the multiple signal lines to pins of the same functional category in the multiple chip modules 101 to 103. The functional category of the signal lines is directly labeled in the corresponding pin names of the multiple chip modules 101 to 103 with an additional prefix or suffix. Specifically, the pin names corresponding to the clock signal line CLN, noise signal line NN, logic signal line LN, quiet signal line QN, and sensitive signal line SN all carry a unified prefix "CLN", "NN", "LN", "QN", or "SN" in the top-level netlist and layout database. This allows the layout routing tool to instantly identify the signal category based on the prefix or suffix during the automatic routing stage and call preset spacing rules, shielding rules, and layer allocation rules. Taking chip module 101 as an example, the pins in chip module 101 corresponding to the sensitive signal line SN are named "A1_SN", "A2_SN", "A3_SN" or "A4_SN", and the pins in chip module 101 corresponding to the clock signal line CLN are named "B1_CLN", "B2_CLN" and "B3_CLN", and so on. This naming mechanism is used throughout the entire chip design and layout process, ensuring that any manual or automated script can directly obtain the signal line type when reading the pin name without having to go back to the functional specification document.

[0032] To further reduce human error rates and improve maintainability, the layout inspection tool renders pins and their connecting lines with different prefixes or suffixes using differentiated colors or line types. This allows designers to intuitively confirm whether the physical isolation between active signal lines such as clock signal lines CLN and noise signal lines NN and protected signal lines such as quiet signal lines QN and sensitive signal lines SN meets preset rules, thereby achieving full-process consistency control from design to layout.

[0033] In summary, the chip top-level structure of this utility model physically divides the wiring unit into a first wiring area and a second wiring area. The active signal lines among the multiple signal lines are arranged in the first wiring area, and the protected signal lines among the multiple signal lines are arranged in the second wiring area. By using isolation strips to electrically isolate the first wiring area and the second wiring area, the coupling noise and parasitic effects between the active signal lines and the protected signal lines are suppressed at the layout level, while significantly reducing the wiring resource occupation and design complexity.

[0034] Furthermore, the chip top-level structure of this invention directly labels the functional categories of the signal lines in the corresponding pin names of the multiple chip modules with additional prefixes or suffixes. This ensures that a unified functional category naming rule is followed throughout the design and layout stages, enabling circuit designers and layout engineers to instantly identify the functional categories of the signal lines, automatically call the corresponding spacing and shielding configurations, avoid human error, shorten the design iteration cycle, and improve work efficiency, thereby achieving a balance between high performance, high reliability, and low cost.

[0035] The embodiments of this utility model described above are examples of specific examples, and do not exhaustively describe all details, nor do they limit the utility model to only specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to make good use of this utility model and its modifications. The scope of protection of this utility model should be determined by the scope defined by the claims of this utility model and their equivalents.

Claims

1. A chip top-level structure, characterized in that, include: Multiple chip modules, each chip module including multiple pins; as well as The wiring unit includes multiple signal lines for connecting to pins of the plurality of chip modules, the plurality of signal lines including logic signal lines, noise signal lines, clock signal lines, sensitive signal lines and quiet signal lines; The wiring unit includes a first wiring area and a second wiring area. Logic signal lines, noise signal lines, and clock signal lines among the plurality of signal lines are arranged in the first wiring area, while sensitive signal lines and quiet signal lines among the plurality of signal lines are arranged in the second wiring area. The first wiring area and the second wiring area are isolated by a continuous isolation strip.

2. The chip top-level structure according to claim 1, characterized in that, The isolation band is formed by the logic signal line or the quiet signal line, which is arranged between the noise signal line or the clock signal line and the sensitive signal line.

3. The chip top-level structure according to claim 2, characterized in that, The isolation strip also includes a metal shielding wire independent of the signal line, the metal shielding wire including a first shielding wire, a second shielding wire, and a third shielding wire. The first shielding line extends continuously along the edge of the first wiring area away from the second wiring area, the second shielding line is located at the boundary between the first wiring area and the second wiring area and extends continuously, and the third shielding line extends continuously along the edge of the second wiring area away from the first wiring area, so that the first wiring area and the second wiring area are each sandwiched between two adjacent shielding lines.

4. The chip top-level structure according to claim 3, characterized in that, The width of the metal shielding wire is equal to the width of the adjacent signal wire.

5. The chip top-level structure according to claim 3, characterized in that, The metal shielding wire is made of at least one of aluminum, copper, or an aluminum-copper alloy.

6. The chip top-level structure according to claim 1, characterized in that, Also includes: Multiple connecting lines perpendicular to the multiple signal lines, each connecting line having one end connected to one of the multiple signal lines through a through-hole, and the other end connected to a pin of the same functional category in the multiple chip modules.

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