A shift register, a gate driving circuit and an active display thereof

Abstract

The application discloses a shift register, which comprises at least one shift register unit, and the shift register unit comprises: a reset unit, two signal input ends of the reset unit are respectively used for inputting a set signal and a reset signal, and the reset unit is used for determining the level of an output enable signal according to the set signal and the reset signal; a current stage signal generating unit, the current stage signal generating unit is used for inputting a first clock signal and the set signal respectively, and the current stage signal generating unit is used for triggering the level of a scanning signal output end to follow the level of the first clock signal during the enable signal being an invalid level based on the effective level of the set signal; and a first maintaining unit, the first maintaining unit is connected between the scanning signal output end and a first level, and the control end of the first maintaining unit inputs the enable signal, and the first maintaining unit is used for resetting the potential of the scanning signal output end to the first level at least when the input enable signal is an effective level. Since the multiple-pulse line scanning signal realizes multiple programming and compensation, the display effect of a display panel driven by the shift register is improved. The application further provides a gate driving circuit and an active display.

Description

Technical Field

[0001] This invention relates to the field of display device technology, specifically to a shift register, a gate driving circuit, and an active display thereof. Background Technology

[0002] In recent years, active-matrix semiconductor display technology has developed rapidly. Typical active-matrix semiconductor displays include active organic light-emitting diode (AMOLED) displays and micro-light-emitting diode (Micro-LED) displays. Benefiting from advantages such as high contrast, fast response speed, low power consumption, high brightness, and suitability for flexible displays, active-matrix displays are widely regarded as the next generation of display technology and will completely replace traditional thin-film transistor liquid crystal displays (TFT-LCD) displays.

[0003] However, unlike TFT-LCDs, the brightness of an active-matrix display is proportional to the on-state current of the driving TFT. This requires the display pixel circuit to extract the threshold voltage (Vth) of the driving TFT, the voltage drop (IR drop) on the power line, and convert the data voltage Vdata into the pixel driving current while maintaining a relatively constant voltage-current conversion relationship. To accurately extract the threshold voltage (Vth) of the driving TFT and the voltage drop (IR drop) on the power line, the gate driving circuit of an active-matrix display needs to have corresponding line-by-line scanning pulses to program the data voltage within the display pixel and compensate for the threshold voltage.

[0004] However, due to the limited area and insufficient driving capability of the gate driving circuit, the current TFT integrated gate driving circuit still has problems such as poor versatility, slow circuit response speed and large output noise when applied to active light-emitting semiconductor displays. This results in non-ideal effects such as low accuracy and inaccurate grayscale of active light-emitting displays. These are key issues that urgently need to be solved. Summary of the Invention

[0005] The main technical problem this invention addresses is how to improve intra-pixel compensation and programming precision to enhance display performance.

[0006] According to a first aspect, one embodiment provides a shift register, including at least one shift register unit, the shift register unit comprising:

[0007] The reset unit has two signal input terminals for inputting a set signal and a reset signal, respectively, and determines the level of the output enable signal based on the set signal and the reset signal.

[0008] This level signal generation unit is used to input the first clock signal and the set signal respectively, and based on the effective level of the set signal, trigger the level output by the scan signal output terminal to follow the level of the first clock signal during the period when the enable signal is ineffective.

[0009] A first sustaining unit is connected between the scan signal output terminal and the first level. Its control terminal receives the enable signal, which is used to reset the potential of the scan signal output terminal to the first level at least when the input enable signal is at an active level.

[0010] According to a second aspect, one embodiment provides a gate drive circuit, including: a shift register, a start signal line, and a common ground line as described in the first aspect;

[0011] The start signal line is connected to at least the scan signal input terminal of the first-stage shift register unit and the scan signal input terminal of the last-stage shift register unit;

[0012] For two adjacent shift register units in the shift register, the first clock signal terminal of the preceding shift register unit and the first clock signal terminal of the following shift register unit are input with different clock signals.

[0013] According to a third aspect, one embodiment provides an active display, comprising:

[0014] The display panel has multiple pixel circuits arranged in a two-dimensional pixel matrix, multiple gate scan lines in a first direction connected to each pixel circuit, and multiple data lines in a second direction connected to each pixel circuit.

[0015] The gate driving circuit as described in the second aspect is used to generate at least a scan signal and provide the required control signal to the corresponding pixel circuit through each row of gate scan lines formed along the first direction to complete the row-by-row scanning of the two-dimensional pixel matrix.

[0016] A data driving circuit is used to generate a data voltage signal and transmit it to the corresponding pixel circuit through the data line to realize the image grayscale.

[0017] According to the shift register, gate drive circuit, and active display of the above embodiments, the reset unit can determine the level of the output enable signal based on the set signal and the reset signal. The signal generation unit at this stage can trigger the level output by the scan signal output terminal to follow the level of the first clock signal during the period when the enable signal is inactive, when the set signal is active. Therefore, it can output a single-pulse row scan signal or a multi-pulse row scan signal. The multi-pulse row scan signal is required for high-precision data voltage programming and multiple threshold voltage compensation processes. By implementing data programming and threshold voltage compensation in a time-division multiplexing manner and extending the actual threshold voltage compensation time, the accuracy of intra-pixel programming and compensation is improved, thereby enhancing the display effect of the driven display panel. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a shift register unit according to one embodiment;

[0019] Figure 2 This is a timing diagram of a shift register unit according to one embodiment;

[0020] Figure 3 This is a schematic diagram of the shift register unit in another embodiment;

[0021] Figure 4 This is a schematic diagram of the structure of a reset unit according to one embodiment;

[0022] Figure 5 This is a schematic diagram of the reset unit according to another embodiment;

[0023] Figure 6 This is a schematic diagram of the reset unit according to another embodiment;

[0024] Figure 7 This is a schematic diagram of the reset unit according to another embodiment;

[0025] Figure 8 This is a schematic diagram of the reset unit according to another embodiment;

[0026] Figure 9 This is a schematic diagram of the reset unit according to another embodiment;

[0027] Figure 10 This is a schematic diagram of the reset unit according to another embodiment;

[0028] Figure 11 This is a schematic diagram of the reset unit according to another embodiment;

[0029] Figure 12 This is a schematic diagram of the shift register unit in another embodiment;

[0030] Figure 13 The timing diagram is for a shift register unit of another embodiment;

[0031] Figure 14 This is a schematic diagram of the structure of an active display according to one embodiment;

[0032] Figure 15 This is a schematic diagram of the structure of an active-matrix display pixel circuit according to one embodiment;

[0033] Figure 16 This is a timing diagram of an active-matrix display pixel circuit according to one embodiment. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0035] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0036] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0037] Current gate drive circuits typically generate single-pulse scan signals to compensate and program within pixels. However, due to the increase in display frame rate and display resolution, the actual scanning time for each row of pixels is getting shorter and shorter. Therefore, single-pulse scan signals can lead to insufficient precision in programming data voltage and compensation of threshold voltage within pixels, resulting in unsatisfactory display effects on the driven display panel.

[0038] In this embodiment of the invention, the shift register can generate a multi-pulse row scanning signal under the control of the set signal and the reset signal. The multi-pulse row scanning signal actually realizes multiple data voltage programming and multiple threshold voltage compensation processes through multiple pulses, thereby improving the accuracy of intra-pixel programming and compensation, and thus improving the display effect of the driven display panel.

[0039] It should be noted that, unless otherwise specified, the transistor in this invention can be any type of transistor, such as a bipolar junction transistor (BJT), a field-effect transistor (FET), or a thin-film transistor (TFT). When the transistor is a bipolar junction transistor, its control electrode refers to the base of the bipolar junction transistor. The first electrode can be the collector or emitter of the bipolar junction transistor, and the corresponding second electrode can be the emitter or collector. In practical applications, the "emitter" and "collector" can be interchanged according to the signal flow direction. When the transistor is a field-effect transistor, its control electrode refers to the gate of the field-effect transistor. The first electrode can be the drain or source of the field-effect transistor, and the corresponding second electrode can be the source or drain. In practical applications, the "source" and "drain" can be interchanged according to the signal flow direction. In the following embodiments, P-type transistors are used for illustration.

[0040] Example 1:

[0041] This embodiment provides a shift register, which includes at least one shift register unit. The shift register unit can generate a desired output signal under the control of an input signal, such as a pulse signal. A shift register formed by cascading multiple shift register units can achieve cascading transmission of the output signal, thereby serving as a row scan signal for a display panel to achieve intra-pixel programming and compensation. Please refer to... Figure 1 The shift register unit includes a reset unit 10, a local signal generation unit 20, and a first sustaining unit 30. In the following embodiments, the shift register unit is specifically described with the effective level being low and the ineffective level being high (i.e., addressing the p-type transistors in the display array).

[0042] The reset unit 10 receives a set signal ST and a reset signal RST through its two signal input terminals, and outputs an enable signal QD. The level of the enable signal QD is determined by the reset unit 10 based on the set signal and the reset signal. In some embodiments, when the set signal ST is inactive and the reset signal RST is active, the reset unit 10 maintains the output level of the enable signal QD at an active level until the set signal ST becomes active, at which point the reset unit 10 maintains the output level of the enable signal QD at an inactive level. Therefore, when the enable signal QD output by the reset unit 10 is low, as soon as the set signal ST becomes low, the reset unit 10 changes from a low-level output state to a high-level output state, and when the set signal ST becomes high and the reset signal RST becomes low, the reset unit 10 changes from a high-level output state to a low-level output state. As can be seen from the above, the reset unit 10 can, under the control of the set signal ST and the reset signal RST, select to maintain the output high level of the enable signal QD or maintain the output low level of the enable signal QD.

[0043] The signal generation unit 20 is used to input the first clock signal CK1 and the set signal ST respectively, and output the scan signal C[n] of this stage. In this embodiment, when the set signal is low, the level of the scan signal output terminal triggered by it follows the level of the first clock signal CK1 while the enable signal QD is high, so as to serve as the scan signal C[n] of this stage. In some embodiments, since the enable signal QD output by the reset unit 10 is always high when the set signal ST is low, the level of the scan signal output terminal follows the level of the first clock signal CK1 after the reset unit 10 changes from a low-level output state to a high-level output state.

[0044] The first sustaining unit 30 is connected between the scan signal output terminal and the first level. Its control terminal receives an enable signal QD. When the enable signal QD is low, the first sustaining unit 30 resets the potential of the scan signal output terminal to at least the first level. In this embodiment, the effective level of the current scan signal is also low, and the ineffective level is also high. Therefore, the corresponding first level is high. That is, when the reset unit 10 changes from an output high level state to an output low level state, the first sustaining unit 30 resets the potential of the scan signal output terminal to a high level.

[0045] As can be seen from the above embodiments, the enable signal QD output by the reset unit 10 has two states: maintaining a high level and maintaining a low level. When the reset unit 10 is in the low-level output state, it will maintain the low-level output state as long as the set signal ST is high. If the set signal ST changes from high to low, the reset unit 10 will change from the low-level output state to the high-level output state. Furthermore, the reset unit 10 will maintain the high-level output state when the set signal ST is low, and when the set signal ST and the reset signal RST are at the same level. Therefore, by controlling the states of the set signal ST and the reset signal RST, the reset unit 10 can be controlled to maintain either a high-level or low-level output state.

[0046] When the reset unit 10 maintains a high output level, the level output by the scan signal output terminal follows the level of the first clock signal CK1, serving as the scan signal C[n] for this stage. When the reset unit 10 maintains a low output level, the first sustaining unit 30 resets the potential of the scan signal output terminal to a high level. With the shift register enabled, the scan signal C[n] for this stage changes with the first clock signal CK1. Therefore, the output of the scan signal for this stage can be controlled by the high or low output of the reset unit 10, allowing the scan signal C[n] to be either a single-pulse scan signal or a multi-pulse scan signal. A multi-pulse scan signal can achieve multiple data voltage programming and multiple threshold voltage compensation processes within a pixel, thereby improving the accuracy of pixel programming and compensation, and ultimately enhancing the display effect of the driven display panel.

[0047] Please refer to this again. Figure 1 In some embodiments, the signal generation unit 20 includes a fifth transistor T5, a sixth transistor T6, and a bootstrap capacitor C1. The control electrode (gate) of the fifth transistor T5 is connected to the first electrode (drain) of the fifth transistor T5 and is used to input a set signal ST. The second electrode (source) of the fifth transistor T5 is connected to the first terminal of the bootstrap capacitor C1 to form an output node Q, and the control electrode of the sixth transistor T6 is connected to the output node Q. The first electrode (source) of the sixth transistor T6 is used to input a first clock signal CK1, and the second electrode (drain) of the sixth transistor T6 is connected to the second terminal of the bootstrap capacitor C1. Under the level control of the output node Q, the first clock signal CK1 is output to the scan signal output terminal as the scan signal C[n] of this stage.

[0048] Please refer to this again. Figure 1In some embodiments, the first sustaining unit 30 includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 is connected between a high level and the output node Q, and the eighth transistor T8 is connected between a high level and the scan signal output terminal. The control electrodes of the seventh transistor T7 and the eighth transistor T8 are used to input the enable signal QD, and when the enable signal QD is low, the potentials of the output node Q and the scan signal output terminal are reset to high level, respectively.

[0049] In some embodiments, the shift register may include multiple cascaded shift register units to achieve cascading transmission of scan signals. In this case, the set signal ST can be the scan signal of the preceding X-stage shift register units, while the reset signal RST can be the scan signal of the following Y-stage shift register units. In some embodiments, since each stage of the shift register unit requires a clock signal to generate its own scan signal, multiple cascaded shift register units require at least two clock signals. The values ​​of X and Y are also related to the number of clock signals. For example, when there are two clock signals, X and Y are both 1; when there are four clock signals, X and Y can be 2, 1 and 3, or 3 and 1, as long as the sum of X and Y is even, ensuring that the clock phases corresponding to the set signal ST and the reset signal RST are the same.

[0050] Please refer to Figure 1 and Figure 2 The following explanation uses two clock signals, the first clock signal CK1 and the second clock signal CK2, and X and Y respectively set to 1 as examples to illustrate the working principle of the single-pulse scanning signal and multi-pulse scanning signal generated by the shift register.

[0051] In this system, adjacent shift register units are respectively fed with a first clock signal CK1 and a second clock signal CK2 to output the scan signal C[n] of the current stage. For the nth stage shift register unit, it has four operating states during the output of the scan signal C[n]: P1a, P2a, P3a, and P4a. If the shift register receives M consecutive pulses within one display frame, the nth stage shift register unit will experience one P1a state, M P2a states, M-1 P3a states, and one P4a state, and the final output scan signal C[n] will also consist of M consecutive pulses. Figure 2 The diagram shows the timing for M=1 and M=4. The following provides a detailed explanation of the four operating states of the shift register unit:

[0052] In state P1a: At this time, the scan signal C[N-1] of the previous stage shift register unit is a low-level VSS pulse, while the scan signal C[N+1] of the next stage shift register unit remains at a high level VGH. The enable signal QD output by the reset unit 10 is high, so the first sustaining unit 30 does not perform a reset function, and both the seventh transistor T7 and the eighth transistor T8 are in the off state. The fifth transistor T5 enters the saturation conduction state because C[N-1] is low, causing the potential of the output node Q to become VS1 = VSS + |VTH| (VTH is the threshold voltage of the fifth transistor T5). It stores charge through the bootstrap capacitor C1 to maintain the potential of the output node Q, and causes the sixth transistor T6 to conduct, thereby outputting the first clock signal CK1 to the scan signal output terminal through the sixth transistor T6. At this time, since the first clock signal CK1 is high, the scan signal C[N] is output at a high level.

[0053] P2a state: At this time, both scan signals C[N-1] and C[N+1] are at high level, and the enable signal QD output by the reset unit 10 remains at high level. When the first clock signal CK1 goes low, due to the bootstrap effect of the bootstrap capacitor C1, the sixth transistor T6 is in the linear region. At this time, the potential VS2 of the output node Q is lower than the low level VSS. Therefore, the low level of the first clock signal CK1 can still be transmitted to the scan signal output terminal without voltage loss. At this time, the scan signal C[N] output is low level.

[0054] P3a State: After P2a state, if both scan signals C[N-1] and C[N+1] are low-level VSS pulses, then P3a state will be entered. At this time, the enable signal QD output by reset unit 10 remains high. The fifth transistor T5 and the sixth transistor T6 are both in the on state, and the potential of output node Q becomes VS1 = VSS + |V TH Therefore, the scan signal C[N] outputs a high level. When the shift register unit first enters the P3a state, the scan signal C[N-1] has already received two pulses. After entering the P3a state, it will enter the P2a state again, causing the scan signal C[N] to output a low level once more.

[0055] P4a State: After P2a state, if the output of scan signal C[N-1] is high and the output of scan signal C[N+1] is a low-level pulse, then P4a state will be entered. At this time, the enable signal QD output by reset unit 10 is low, so the first sustaining unit 30 performs a reset function, and the seventh transistor T7 and the eighth transistor T8 are both in the on state, thereby resetting the potential of output node Q and scan signal output terminal to high level, thus ending the output of pulse scan signal of this stage.

[0056] As can be seen from the working principle of the shift register described above, when the shift register is input with only one pulse, each shift register unit goes through the P1a, P2a and P4a states in sequence to achieve single-pulse scan signal output. When the shift register is input with multiple pulses, each shift register unit will repeatedly go through the P2a and P3a states according to the number of pulses to achieve multi-pulse scan signal output.

[0057] As can be seen from the working principle of the signal generation unit 20, the fifth transistor T5 and the bootstrap capacitor C1 form a pre-discharge unit 22, and output a pre-discharge level VS1 or VS2 through the output node Q. Both the pre-discharge levels VS1 and VS2 are less than the global high level and greater than the global low level. The sixth transistor T6 forms an output unit 24, and is turned on under the control of the pre-discharge level VS1 or VS2, so that the scan signal C[n] output to the scan signal output terminal follows the level of the first clock signal CK1.

[0058] Please refer to Figure 3 In some embodiments, the shift register unit further includes a second sustaining unit 40. The second sustaining unit 40 is connected between the scan signal output terminal and the high level, and is used to reset the potential of the scan signal output terminal to the high level when the scan signal C[n] of this stage is output at a high level, so as to maintain the high level output of the scan signal C[n] of this stage.

[0059] The second sustaining unit 40 includes a ninth transistor T9, a ninth transistor T10, and an eleventh transistor T11. The ninth transistor T9 is connected between the scan signal output terminal and the high level, and the ninth transistor T10 is connected between the high level and the source of the eleventh transistor T11. A node QC is formed between the ninth transistor T10 and the eleventh transistor T11 and is connected to the control electrode of the ninth transistor T9. The drain of the eleventh transistor T11 is connected to the control electrode and used to input the second clock signal CK2, or the drain of the eleventh transistor T11 is grounded. The control electrode of the ninth transistor T10 is connected to the scan signal output terminal. When the scan signal C[n] of this stage is low and the second clock signal CK2 is high, the eleventh transistor T11 is turned off, while the ninth transistor T10 is turned on and pulls the potential of node QC to a high level, causing the ninth transistor T9 to turn off. Therefore, the scan signal C[n] of this stage is not affected. When the scan signal C[n] of this stage changes from low level to high level, and the second clock signal CK2 outputs a low level, the ninth transistor T10 is turned off, while the eleventh transistor T11 is turned on and pulls the potential of node QC to a low level. This causes the ninth transistor T9 to turn on and reset the potential of the scan signal output terminal to a high level, so as to maintain the high level output of the scan signal C[n] of this stage.

[0060] As described above, the second sustaining unit 40 can maintain the high level of the shift register unit's output when the shift register unit outputs the scan signal C[n] of this stage, thus ensuring stable output. Furthermore, the second sustaining unit 40 can work with the first sustaining unit 30 to maintain the high level of the shift register unit when it is not outputting the scan signal C[n] of this stage.

[0061] Example 2:

[0062] This embodiment provides some specific circuits for the reset unit 10. The reset unit 10 will be described in detail below.

[0063] In some embodiments, the reset unit 10 includes a main module 12 and a sub-module 14. The power supply terminal of the main module 12 is connected to a high level, and its signal input terminal is used to input a set signal ST. The power supply terminal of the sub-module 14 is connected to a low level, and its signal input terminal is used to input a reset signal RST. The output terminals of the main module 12 and the sub-module 14 are connected, and the connection node serves as an enable signal output terminal. When the set signal ST is low, the main module 12 applies a high level from its power supply terminal to the enable signal output terminal. When the reset signal RST is low, the sub-module 14 applies a low level from its power supply terminal to the enable signal output terminal. When both the set signal ST and the reset signal RST are low, the main module 12 controls the potential of the enable signal output terminal to be closer to a high level. When both the set signal ST and the reset signal RST are high, the potential of the enable signal output terminal remains at its previous level. Voltage sources VGH and VGL are used to provide high and low voltage levels, respectively. They only need to carry high and low voltage signals, and do not necessarily need to be fixed voltage sources.

[0064] Please refer to Figure 4 In some embodiments, the main module 12 includes a first transistor T1, and the sub-module 14 includes a second transistor T2. The first transistor T1 and the second transistor T2 are connected between a high level and a low level. The connection node between the first transistor T1 and the second transistor T2 serves as an enable signal output terminal. The gates of the first transistor T1 and the second transistor T2 are respectively input to a set signal ST and a reset signal RST. Wherein, the first transistor T1 and the second transistor T2, under the same other performance or structure, satisfy at least one of the following conditions:

[0065] 1) The channel width-to-length (W / L) ratio of the first transistor T1 is greater than the channel width-to-length (W / L) ratio of the second transistor T2.

[0066] 2) The equivalent field-effect mobility of the first transistor T1 is greater than that of the second transistor T2.

[0067] 3) The overdrive voltage of the first transistor T1 is greater than the overdrive voltage of the second transistor T2.

[0068] 4) The first transistor T1 is a dual-gate transistor, and the second transistor T2 is a single-gate transistor.

[0069] Among them, for the channel width-to-length ratio (W / L) and equivalent field-effect mobility of the transistor, the first transistor T1 and the second transistor T2 that meet the requirements can be selected according to the size and material of the transistor. For the overdrive voltage, the absolute value of the gate-source voltage difference of the first transistor T1 can be made greater than the absolute value of the gate-source voltage difference of the second transistor T2.

[0070] When the above conditions are met between the first transistor T1 and the second transistor T2, the equivalent impedance of the first transistor T1 is less than the equivalent impedance of the second transistor T2, so that the pull-up capability of the first transistor T1 is greater than the pull-down capability of the second transistor T2. Thus, when both the set signal ST and the reset signal RST are at low level, the first transistor T1 can control the potential of the enable signal output terminal to be closer to the high level.

[0071] In this embodiment, both the first transistor T1 and the second transistor T2 can be PMOS devices. Since PMOS devices can transmit high-level voltages at full amplitude, but there is a threshold voltage loss problem when transmitting low-level voltages, even if the first transistor T1 and the second transistor T2 have the same device size and device characteristics, the pull-up capability of the first transistor T1 is greater than the pull-down capability of the second transistor T2.

[0072] Please refer to Figure 5 , Figure 6 and Figure 7 In some embodiments, the first transistor T1 of the main module 12 can be a dual-gate transistor, while the second transistor T2 of the sub-module 14 can be a single-gate transistor. The first gate of the first transistor T1 is used to input a set signal ST, and the second gate of the first transistor T1 is used to input a first bias voltage, or the set signal ST, or an enable signal QD. Since the operating state of the dual-gate transistor is jointly controlled by the top and bottom gate metal layers, configuring a suitable bias voltage for the dual-gate transistor can make the equivalent impedance of the dual-gate structure first transistor T1 less than that of the single-gate structure second transistor T2, thereby achieving a pull-up capability of the first transistor T1 greater than the pull-down capability of the second transistor T2. Please refer to... Figure 7In this embodiment, the second transistor T2 of the sub-module 14 can also be a dual-gate transistor. The first gate of the second transistor T2 is used to input the reset signal RST, and the second gate of the second transistor T2 is used to input the second bias voltage, which is lower than the first bias voltage, the set signal ST, or the voltage of the reset signal. Since, under the same device characteristics, by reasonably adjusting the bias voltage of the second gate of the first transistor T1 and the second gate of the second transistor T2—for example, setting the second bias voltage lower than the first bias voltage, or leaving the second gate of the second transistor T2 floating—the equivalent impedance of the first transistor T1 can be made smaller than that of the second transistor T2, thereby achieving a pull-up capability of the first transistor T1 greater than that of the second transistor T2.

[0073] As can be seen from the above embodiments, transistors with different performance and structure can be selected to implement the main module 12 and the sub-module 14, and the equivalent impedance of the output port of the main module 12 can be made smaller than that of the output port of the sub-module 14 by means of the performance of the transistor itself or the connection method.

[0074] Please refer to Figure 8 and Figure 9 In some embodiments, the main module 12 includes a first transistor T1, and the sub-module 14 includes a second transistor T2 and a third transistor T3. The first transistor T1, the second transistor T2, and the third transistor T3 are connected between a high level and a low level. The gates of the first transistor T1 and the third transistor T3 are respectively input to a set signal ST and a reset signal RST. The gate of the second transistor T2 is connected to its drain or to a control signal S1. The connection node between the first transistor T1 and the second transistor T2 serves as an enable signal output terminal. When the gate of the second transistor T2 is connected to its drain, there is a threshold voltage loss between the source and drain of the second transistor T2. When the gate of the second transistor T2 is connected to the control signal S1, the control signal S1 can cause a voltage difference between the source and drain of the second transistor T2, or even cause the second transistor T2 to be in a turned-off state. In both cases, the equivalent impedance of the output port of the main module 12 is less than the equivalent impedance of the output port of the sub-module 14, thereby making the pull-up capability of the main module 12 greater than the pull-down capability of the sub-module 14. In this embodiment, the positions of the second transistor T2 and the third transistor T3 in the sub-module 14 can be interchanged without affecting the overall equivalent impedance of the output port of the sub-module 14. In this embodiment, when the transistors have the same device size and device characteristics, when the number of transistors connected in series in the sub-module 14 is greater than the number of transistors connected in series in the main module 12, the equivalent impedance of the output port of the main module 12 can be made smaller than that of the sub-module 14.

[0075] As can be seen from the above embodiments, in addition to the performance of the transistor itself or the connection method, the number of transistors can also be used to make the equivalent impedance of the output port of the main module 12 less than the equivalent impedance of the output port of the sub-module 14.

[0076] In some embodiments, the reset unit 10 includes a main module 12 and a sub-module 14. The main module 12 and the sub-module 14 are connected between a high level and a low level. The signal input terminal of the main module 12 is used to input a set signal ST, and the signal input terminal of the sub-module 14 is used to input a reset signal RST. The output terminal of either the main module 12 or the sub-module 14 is used to output the potential of the connection node between the main module 12 and the sub-module 14, which serves as the level of the enable signal QD. When both the set signal ST and the reset signal RST are low, the level of the enable signal QD is closer to a high level; when both the set signal ST and the reset signal RST are high, the level of the enable signal QD remains at its previous level.

[0077] Please refer to Figure 10 In some embodiments, the main module 12 includes a first transistor T1, and the sub-module 14 includes a second transistor T2 and a third transistor T3. The first transistor T1 and the second transistor T2 are connected between a high level and a low level, forming a node QI between them. The first terminal (source) of the third transistor T3 is connected to the node QI, and the second terminal (drain) of the third transistor T3 is used to output the potential of the node QI as the level of the enable signal QD. The control terminal of the third transistor T3 is used to input the reset signal RST, and the control terminal of the first transistor T1 is used to input the set signal ST. In this embodiment, the pull-up capability of the first transistor T1 can be made greater than the pull-down capability of the second transistor T2, and the potential of the node QI is output through the third transistor T3 in the sub-module 14 as the level of the enable signal QD.

[0078] Please refer to Figure 11In some embodiments, the main module 12 includes a first transistor T1, a fourth transistor T4, and a first capacitor C2, while the sub-module 14 includes a second transistor T2 and a third transistor T3. The first transistor T1, the second transistor T2, and the third transistor T3 are connected between a high level and a low level. A node Q1 is formed between the first transistor T1 and the second transistor T2. Under the control of a second clock signal input to its control electrode, the fourth transistor T4 outputs the potential of node Q1 as the level of the enable signal QD. The first capacitor C2 is connected between the first level and the second electrode (drain) of the fourth transistor T4. The control electrode of the third transistor T3 is used to input the reset signal RST, and the control electrode of the first transistor T1 is used to input the set signal ST. In this embodiment, the pull-up capability of the first transistor T1 is greater than the pull-down capability of the sub-module 14. Alternatively, the pull-up capability of the first transistor T1 can be greater than the pull-down capability of the sub-module 14 through the method described in the above embodiment. The potential of the output node Q1 is then used as the level of the enable signal QD through the fourth transistor T4 in the main module 12. Furthermore, the potential of the output enable signal QD is made more stable through the fourth transistor T4 and the first capacitor C2.

[0079] Example 3:

[0080] Please refer to Figure 12 This embodiment provides a shift register, which differs from Embodiment 1 in that the shift register unit further includes a light-emitting signal generation unit 50. The light-emitting signal generation unit 50 is connected between the output node Q and the high-level signal. The light-emitting signal generation unit 50 uses its two signal input terminals to input the previous stage light-emitting control signal and the third clock signal ECK1, respectively. Under the control of the pre-discharge level of the output node Q, it outputs a high-level light-emitting control signal EM[n] to the light-emitting signal output terminal. The high-level light-emitting control signal EM[n] can be used to control the light-emitting diodes within the pixel to emit light. The effective level of the light-emitting control signal EM[n] is high, but it can also be set to low depending on the situation. In this embodiment, a high level is used for specific explanation.

[0081] In some embodiments, the light emission signal generating unit 50 includes a twelfth transistor TE1, a thirteenth transistor TE2, a fourteenth transistor TE3, and a fifteenth transistor TE4.

[0082] The twelfth transistor and the fourteenth transistor are connected between a high level and the third clock signal ECK1, a node QB is formed between the twelfth transistor and the fourteenth transistor, the thirteenth transistor and the fourteenth transistor are connected between a high level and the third clock signal ECK1, and the node between the thirteenth transistor and the fourteenth transistor is connected to the light-emitting signal output terminal. The control electrode of the twelfth transistor is used for inputting a previous-stage light-emitting control signal, the control electrode of the thirteenth transistor is connected to the node QB, and the control electrodes of the fourteenth transistor and the fifteenth transistor are respectively connected to the output node Q.

[0083] In this embodiment, if the shift register is input with M consecutive pulses within the time of one display frame, then the shift register unit of the nth stage will experience 1 time of P1a state, M times of P2a state, M - 1 times of P3a state, 1 time of P4a state, and finally the scan signal C[n] output by the local signal generating unit 20 will also have M consecutive pulses. The shift register unit of the nth stage will also sequentially experience P1d state, P2d state, and P3d state, and after experiencing these three states, the local light-emitting control signal EM[n] is output by the light-emitting signal generating unit 50, and the pulse width of the local light-emitting control signal EM[n] is positively correlated with the number of pulses of the scan signal C[n]. The process of outputting the local light-emitting control signal EM[n] will be specifically described below.

[0084] Please refer to Figure 12 and Figure 13 , in this embodiment, the period of the clock signal for generating the local scan signal is T1, the ratio of the effective level time to the clock period is k1 (0 < k1 < 1), the period of the clock signal for generating the local light-emitting control signal is T2, the ratio of the effective level time to the clock period is k2 (0 < k2 < 1). Taking a two-phase non-overlapping clock (CK1, CK2) with a period of T1 and a duty cycle of 50%, and a four-phase overlapping clock (ECK1, ECK2, ECK3, ECK4) with a period of T2 and a duty cycle of 50% as an example, for exemplary illustration:

[0085] P1d State: When the potential of the output node Q of the nth stage is high (VGH), the light-emitting signal generation unit 50 enters the P1d state. In the early stage of the P1d state, when the light-emitting control signal EM[n-2] output by the (n-2)th stage light-emitting signal generation unit 50 is low, although the potential of node QB of the nth stage light-emitting signal generation unit 50 periodically changes to VSS+|Vth| or VGH with the change of the third clock signal ECK1, and because the gate-drain potentials of the thirteenth transistor TE2 are the same, the thirteenth transistor TE2 remains off, causing the output light-emitting control signal EM[n] of this stage to remain low. In the later stage of the P1d state, when the light-emitting control signal EM[n-2] is high, the thirteenth transistor TE2 remains off, so in the P1d state, the light-emitting control signal EM[n] of this stage maintains a low voltage.

[0086] P2d state: When the potential of the nth stage output node Q is at the pre-discharge level VS1 or VS2, the light emission signal generation unit 50 enters the P2d state. At this time, the pre-discharge level VS1 or VS2 effectively turns on the fourteenth transistor TE3 and the fifteenth transistor TE4, while the twelfth transistor TE1 and the thirteenth transistor TE2 are turned off. Therefore, the light emission control signal EM[n] of node QB and this stage is high.

[0087] P3d State: When the potential of the nth stage output node Q returns to a high level, the light emission signal generation unit 50 enters the P3d state. At this time, the fourteenth transistor TE3 and the fifteenth transistor TE4 are turned off, the light emission control signal EM[N-2] is low, the twelfth transistor TE1 is turned on, and the third clock signal ECK1 changes from high to low. Due to the bootstrap effect of the intrinsic capacitance of the thirteenth transistor TE2, the potential of node QB drops to VS2, causing the thirteenth transistor TE2 to turn on. Thus, the low level of the third clock signal ECK1 is transmitted to the light emission signal output terminal without loss, making the light emission control signal EM[n] low.

[0088] In this embodiment, due to the voltage feedthrough effect caused by the transition of the third clock signal ECK1, the potential of node QB may also change, which is not conducive to stably turning off the twelfth transistor TE1. Therefore, the light emission control signal EM[n-2] can be input through the gate of the twelfth transistor TE1, so that the twelfth transistor TE1 can be kept off well in the P2d stage, so that the light emission control signal EM[n] and the potential of node QB are maintained at a high level without being disturbed by the clock feedthrough.

[0089] As can be seen from the above embodiments, since the light-emitting signal generating unit 50 outputs a high-level light-emitting control signal EM[n] under the control of the pre-discharge level VS1 or VS2 of the output node Q, the signal width of the light-emitting control signal EM[n] is consistent with the width of the pre-discharge level VS1 and VS2. For each pulse input to the shift register, the output node Q will generate a pre-discharge level VS1 and VS2 respectively. Therefore, the signal width of the light-emitting control signal EM[n] is M*T1, that is, the product of the number of pulses M and the period T1 of the first clock signal CK1.

[0090] In this embodiment, since each shift register unit can generate the same level of light emission control signal EM[n] when generating the scan signal C[n] of the same level, the level transmission of the scan signal and the level transmission of the light emission control signal can be realized by sharing a set of shift registers. Compared with the implementation by using different sets of shift registers, the shift register structure in this embodiment is simpler, reduces implementation cost, and can also reduce the wiring required when driving pixels, thereby reducing the area occupied by the circuit and facilitating the implementation of narrow bezel display panels.

[0091] Example 4:

[0092] This embodiment provides a gate drive circuit, which includes a shift register, a start signal line, and a common ground line.

[0093] The shift register can be the shift register described in Embodiment 1 or Embodiment 3, which can be used to generate the cascaded scanning signal, or it can also simultaneously generate the cascaded light emission control signal. In the shift register, adjacent shift register units receive different clock signals at their first clock signal terminals.

[0094] The start signal line is connected to the scan signal input terminal of the first-stage shift register unit and the scan signal input terminal of the last-stage shift register unit.

[0095] Example 5:

[0096] Please refer to Figure 14 This embodiment provides an active display, which includes a display panel, a gate driving circuit, and a data driving circuit.

[0097] The display panel has multiple pixel circuits arranged in a two-dimensional pixel matrix, multiple gate scan lines in a first direction connected to each pixel circuit, and multiple data lines in a second direction connected to each pixel circuit.

[0098] The gate driving circuit can be the gate driving circuit in Embodiment 4, which is used to generate scanning signals and provide the required control signals to the corresponding pixel circuits through the rows of gate scanning lines formed along the first direction to complete the row-by-row scanning of the two-dimensional pixel matrix. In some embodiments, the gate driving circuit can also be used to generate light emission control signals and complete the light emission control of the two-dimensional pixel matrix through corresponding lines.

[0099] A data driving circuit is used to generate a data voltage signal and transmit it to the corresponding pixel circuit through the data line to realize the image grayscale.

[0100] In this embodiment, the shift register can output multi-pulse scanning signals. These multi-pulse line scanning signals enable multiple data voltage programming and threshold voltage compensation processes for the pixel circuit, thereby improving the accuracy of intra-pixel programming and compensation, and ultimately enhancing the display panel's performance. This embodiment uses a shared set of shift registers to achieve the cascading transmission of scanning signals and light emission control signals. Compared to using different sets of shift registers, this embodiment has a simpler shift register structure, reduces implementation costs, and also reduces the wiring required to drive pixels, thus reducing the circuit area and facilitating the implementation of narrow-bezel display panels.

[0101] Please refer to Figure 15 In some embodiments, each pixel circuit of the display panel is an active-matrix display pixel circuit, which includes a light-emitting element 60, a storage capacitor Cst, and six transistors. The light-emitting element 60 can be an OLED or an LED, connected in series with a first switching transistor Ta1 and a third switching transistor Ta3 for switching, and a second driving transistor Ta2 for driving. The current of the light-emitting element 60 is mainly determined by the second driving transistor Ta2. A fourth driving transistor Ta4 is connected between the data line Data and the source (node ​​B) of the second driving transistor Ta2, serving to transmit data signals. A fifth driving transistor Ta5 is connected between the gate (node ​​A) and drain of the second driving transistor Ta2, serving to extract the threshold voltage of the second driving transistor Ta2. A sixth driving transistor Ta6 is connected between the gate (node ​​A) of the second driving transistor Ta2 and the reference voltage line Vref, serving to initialize node A. The storage capacitor Cst is connected between the source of the first switching transistor Ta1 and node A.

[0102] For the pixel circuit in the nth row, it requires the neighboring row scan signals P[n-1] and P[n], as well as the light emission control signal EM[n]. The gates of the first switching transistor Ta1 and the third switching transistor Ta3 are used to input the light emission control signal EM[n], the connection node between the gates of the fourth driving transistor Ta4 and the fifth driving transistor Ta5 is used to input the scan signal P[n], and the gate of the sixth driving transistor Ta6 is used to input the scan signal P[n-1].

[0103] For the pixel circuit of the nth row, the scanning signals P[n-1], P[n], P[n+1] and the light emission control signals EM[n-1], EM[n], EM[n+1] are used for explanation. The scanning signals P[n-1], P[n], P[n+1] are non-overlapping low-level pulse signals used to provide row-by-row programming signals for the display array. The light emission control signals EM[n-1], EM[n], EM[n+1] are high-level pulse signals with a 50% overlap in pulse width between adjacent rows, used to turn off the pixel circuit during the programming and threshold voltage extraction stages, and turn it on during the light emission display stage. Figure 16 The diagram also illustrates the timing of the pixel circuit entering PWM dimming mode, where scan signals P[n-1], P[n], and P[n+1] remain at a high level, while signals EM[n-1], EM[n], and EM[n+1] are at 0%, 50%, and 75% brightness in subframes FR1, FR2, and FR3, respectively.

[0104] Please refer to Figure 16 The pixel circuit operates in three stages to emit light: P1, P2, and P3. During each stage, the transistors in the pixel circuit are switched on and off accordingly to perform functions such as reset, data writing, Vth compensation, and light emission control. The following provides a detailed explanation of the P1, P2, and P3 stages of the pixel circuit.

[0105] P1 initialization phase,

[0106] When the gate scan signal P[n-1] goes low, the sixth driving transistor Ta6 is turned on, and the potential of node A is pulled low. The lower plate of the storage capacitor Cst is charged to Vref, and the second driving transistor Ta2 is pre-turned on. Since the gate scan signal P[n] and the light emission control signal EM[n] are high, all other transistors in the pixel circuit are off.

[0107] P2 programming and compensation phase

[0108] When the gate scan signal P[n] goes low, the fourth driving transistor Ta4 and the fifth driving transistor Ta5 are turned on, and the voltage at node B becomes Vdata. The voltage at node A is gradually raised through the second driving transistor Ta2 and the fifth driving transistor Ta5. The second driving transistor Ta2 is turned off only when the voltage at node A reaches Vdata-|Vth|. Thus, the data line voltage Vdata and the threshold voltage information of the second driving transistor Ta2 are stored on the lower plate of capacitor Cst.

[0109] During the P2 stage, since the gate scan signal P[n-1] and the light emission control signal EM[n] are at high levels, the other transistors in the pixel circuit are all in the off state.

[0110] 3) P3 luminescence stage,

[0111] When the gate scan signals P[n-1] and P[n] go high, the related fourth driving transistor Ta4, fifth driving transistor Ta5, and sixth driving transistor Ta6 are all turned off. Under the action of the storage capacitor Cst, node A stores the data voltage signal and threshold voltage extraction signal of the pixel written in stage P2. When the light emission control signal EM[n] is low, the source of the second driving transistor Ta2 (node ​​B) is charged to VDD, and the third switching transistor Ta3 is turned on. Therefore, the current of the light emission element 60 is uniquely determined by the second driving transistor Ta2 (operating in saturation state).

[0112]

[0113] Due to V B The value remains Vdata-|Vth|, therefore the current of the second driving transistor Ta2 is:

[0114]

[0115] Thus, it can be seen that the current of the light-emitting element 60 is independent of the threshold voltage of the second driving transistor Ta2, thereby achieving compensation for the non-uniformity / drift characteristics of the threshold voltage.

[0116] Furthermore, in the actual light-emitting display stage, the brightness of the light-emitting element 60 can be precisely controlled by adjusting the duty cycle of the light-emitting control signal EM[n]. The light-emitting control signals EM[n-1], EM[n], EM[n+1], etc., can be controlled synchronously or sequentially.

[0117] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A shift register, comprising at least one shift register unit, characterized in that, The shift register unit includes: A reset unit has two signal input terminals for inputting a set signal (ST) and a reset signal (RST), respectively, and determines the level of the output enable signal (QD) based on the set signal (ST) and the reset signal (RST). The reset unit includes a main module and a sub-module. The power supply terminal of the main module is connected to a first voltage level, and its signal input terminal is used to input the set signal (ST). The power supply terminal of the sub-module is connected to a second voltage level, and its signal input terminal is used to input the reset signal (RST). The output terminals of the main module and the sub-module are connected, and the connection node is used as... At the enable signal output terminal, when the set signal (ST) is active, the main module applies a first level to the enable signal output terminal, and when the reset signal (RST) is active, the sub-module applies a second level to the enable signal output terminal. When both the set signal (ST) and the reset signal (RST) are active, the main module and the sub-module are configured to keep the level of the enable signal (QD) closer to the first level. When both the set signal (ST) and the reset signal (RST) are inactive, the main module and the sub-module are configured to keep the level of the enable signal (QD) unchanged. This level signal generation unit is used to input the first clock signal (CK1) and the set signal (ST) respectively, and based on the effective level of the set signal (ST), trigger the level output by the scan signal output terminal to follow the level of the first clock signal (CK1) during the period when the enable signal (QD) is inactive; The first sustaining unit is connected between the scan signal output terminal and the first level. Its control terminal is input with the enable signal (QD) to reset the potential of the scan signal output terminal to the first level when the input enable signal (QD) is active.

2. A shift register, comprising at least one shift register unit, characterized in that, The shift register unit includes: A reset unit has two signal input terminals for inputting a set signal (ST) and a reset signal (RST), respectively, and determines the level of the output enable signal (QD) based on the set signal (ST) and the reset signal (RST). The reset unit includes a main module and a sub-module, which are connected between a first level and a second level. The signal input terminal of the main module is used to input the set signal (ST), and the signal input terminal of the sub-module is used to input the reset signal (RST). The output terminal of the main module or the sub-module is used to output the potential of the connection node between the main module and the sub-module as the level of the enable signal (QD). When the set signal (ST) and the reset signal (RST) are both active, the main module and the sub-module are configured to keep the level of the enable signal closer to the first level. When the set signal (ST) and the reset signal (RST) are both inactive, the main module and the sub-module are configured to keep the level of the enable signal unchanged. This level signal generation unit is used to input the first clock signal (CK1) and the set signal (ST) respectively, and based on the effective level of the set signal (ST), trigger the level output by the scan signal output terminal to follow the level of the first clock signal (CK1) during the period when the enable signal (QD) is inactive; The first sustaining unit is connected between the scan signal output terminal and the first level. Its control terminal is input with the enable signal (QD) to reset the potential of the scan signal output terminal to the first level when the input enable signal (QD) is active.

3. The shift register as described in claim 1 or 2, characterized in that, When the set signal (ST) is inactive and the reset signal (RST) is active, the reset unit maintains the output enable signal (QD) at an active level until the set signal (ST) is active, at which point it maintains the output enable signal (QD) at an inactive level.

4. The shift register as described in claim 3, characterized in that, The set signal (ST) is the scan signal for the first X-stage shift register unit, and the reset signal (RST) is the scan signal for the second Y-stage shift register unit.

5. The shift register as described in claim 4, characterized in that, The sum of X and Y is an even number.

6. The shift register as described in claim 5, characterized in that, The set signal (ST) is the scan signal of the previous stage shift register unit, and the reset signal (RST) is the scan signal of the next stage shift register unit.

7. The shift register as described in claim 1, characterized in that, The equivalent impedance of the output port of the main module is less than the equivalent impedance of the output port of the sub-module.

8. The shift register as described in claim 7, characterized in that, The main module includes a first transistor, and the sub-module includes a second transistor. The first transistor and the second transistor are connected between a first level and a second level, and the connection node between the first transistor and the second transistor serves as an enable signal output terminal. The channel width-to-length ratio of the first transistor is greater than that of the second transistor; And / or, the equivalent field-effect mobility of the first transistor is greater than the equivalent field-effect mobility of the second transistor; And / or, the overdrive voltage of the first transistor is greater than the overdrive voltage of the second transistor; And / or, the first transistor is a dual-gate transistor and the second transistor is a single-gate transistor.

9. The shift register as described in claim 7, characterized in that, The main module includes several first transistors connected in series, and the sub-module includes several second transistors connected in series. The first transistors and the second transistors are connected between a first level and a second level, wherein the connection node between one of the first transistors and one of the second transistors serves as an enable signal output terminal; the number of first transistors is less than the number of second transistors.

10. The shift register as described in claim 7, characterized in that, The main module includes a first transistor, and the sub-module includes a second transistor. The first transistor and the second transistor are connected between a first level and a second level, and the connection node between the first transistor and the second transistor serves as an enable signal output terminal. The first transistor is a dual-gate transistor, where the first gate of the first transistor is used to input the set signal (ST), and the second gate of the first transistor is used to input a first bias voltage (VB1), or to input the set signal (ST), or to input an enable signal (QD); the second transistor is a single-gate transistor. Alternatively, the second transistor is a dual-gate transistor, with the first gate of the second transistor used to input the reset signal (RST) and the second gate of the second transistor used to input a second bias voltage (VB2), which is lower than the voltage of the first bias voltage (VB1), the set signal (ST), or the reset signal.

11. The shift register as described in claim 2, characterized in that, The equivalent impedance of the output port of the main module is less than the equivalent impedance of the output port of the sub-module.

12. The shift register as described in claim 11, characterized in that, The main module includes a first transistor, and the sub-module includes a second transistor and a third transistor; The first transistor and the second transistor are connected between a first level and a second level, forming a node (QI) between the first transistor and the second transistor. The first terminal of the third transistor is connected to the node (QI), and the second terminal of the third transistor is used to output the potential of the node (QI) as the level of the enable signal (QD). The control terminal of the third transistor is used to input the reset signal (RST), and the control terminal of the first transistor is used to input the set signal (ST).

13. The shift register as described in claim 11, characterized in that, The main module includes a first transistor, a fourth transistor, and a first capacitor; the sub-module includes a second transistor and a third transistor. The first transistor, the second transistor, and the third transistor are connected between the first level and the second level, forming a node (QI) between the first transistor and the second transistor. Under the control of the second clock signal input to the control electrode, the fourth transistor outputs the potential of the node (QI) as the level of the enable signal (QD). The first capacitor is connected between the first level and the second electrode of the fourth transistor. The control electrode of the third transistor is used to input the reset signal (RST), and the control electrode of the first transistor is used to input the set signal (ST).

14. The shift register as described in claim 1 or 2, characterized in that, The first level is high and the second level is low; or, the first level is low and the second level is high.

15. The shift register as described in claim 1 or 2, characterized in that, The signal generation unit of this stage includes a pre-discharge unit and an output unit. The signal input terminal of the pre-discharge unit is used to input the set signal (ST). When the set signal (ST) is at an active level, its output node Q outputs a pre-discharge level. The pre-discharge level is less than the global high level and greater than the global low level. When the set signal (ST) is at an inactive level, its output node Q remains at the pre-discharge level. The output unit is connected to the output node Q of the pre-discharge unit and the output terminal of the first clock signal (CK1), and under the control of the pre-discharge level, the scan signal (C[n]) of this stage output to the scan signal output terminal follows the level of the first clock signal (CK1).

16. The shift register as described in claim 15, characterized in that, The pre-discharge unit includes a fifth transistor and a bootstrap capacitor, and the output unit includes a sixth transistor; The control electrode of the fifth transistor is connected to the first electrode of the fifth transistor and is used to input the set signal (ST). The second electrode of the fifth transistor is connected to the first terminal of the bootstrap capacitor to form the output node Q. The control electrode of the sixth transistor is connected to the output node Q. The first electrode of the sixth transistor is used to input the first clock signal (CK1). The second electrode is connected to the second terminal of the bootstrap capacitor and, under the control of the pre-discharge level of the output node Q, outputs the first clock signal (CK1) to the scan signal output terminal as the scan signal (C[n]) of this stage.

17. The shift register as described in claim 16, characterized in that, The first sustaining unit includes a seventh transistor and an eighth transistor; The seventh transistor is connected between the first level and the output node Q, and the eighth transistor is connected between the first level and the scan signal output terminal. The control electrodes of the seventh and eighth transistors are respectively used to input the enable signal (QD), and when the enable signal (QD) is at an active level, the potentials of the scan signal output terminal and the output node Q are respectively reset to the first level.

18. The shift register as described in claim 16, characterized in that, It also includes a light emission signal generation unit; The light emission signal generation unit is connected between the output node Q and the first level. The light emission signal generation unit is used to input the previous stage light emission control signal and the third clock signal (ECK1) through its two signal input terminals. The light emission signal generation unit is used to output an effective level light emission control signal of this stage to the light emission signal output terminal under the control of the pre-discharge level of the output node Q, and the signal width is positively correlated with the number of pulses of the scan signal of this stage. Under the control of the previous stage light emission control signal and the third clock signal (ECK1), the light emission signal generation unit outputs an ineffective level light emission control signal of this stage to the light emission signal output terminal.

19. The shift register as described in claim 18, characterized in that, The light-emitting signal generating unit includes a twelfth transistor (TE1), a thirteenth transistor (TE2), a fourteenth transistor (TE3), and a fifteenth transistor (TE4). The twelfth transistor (TE1) and the fourteenth transistor (TE3) are connected between the first level and the third clock signal (ECK1), and a node (QB) is formed between the twelfth transistor (TE1) and the fourteenth transistor (TE3). The thirteenth transistor (TE2) and the fourteenth transistor (TE3) are connected between the first level and the third clock signal (ECK1), and the node between the thirteenth transistor (TE2) and the fourteenth transistor (TE3) is connected to the light-emitting signal output terminal. The control electrode of the twelfth transistor (TE1) is used to input the pre-stage light emission control signal. The control electrode of the thirteenth transistor (TE2) is connected to node (QB) and, under the control of the pre-stage light emission control signal and the third clock signal (ECK1), outputs a portion of the third clock signal (ECK1) to the light emission signal output terminal as a non-active level light emission control signal for this stage. The control electrodes of the fourteenth transistor (TE3) and the fifteenth transistor (TE4) are respectively connected to the output node Q. Under the pre-discharge level control of the output node Q, the fifteenth transistor (TE4) outputs the first level to the light emission signal output terminal as the effective level light emission control signal of this stage. Under the potential control of the output node Q, the fourteenth transistor (TE3) outputs the first level to the node QB, causing the thirteenth transistor (TE2) to be turned off.

20. The shift register as described in claim 1 or 2, characterized in that, It also includes a second sustaining unit, which is connected between the scan signal output terminal and the first level; The second sustaining unit is used to input the second clock signal (CK2) and the scan signal (C[n]) of this stage through its two signal input terminals respectively. When the scan signal (C[n]) of this stage is an inactive level output, the second sustaining unit outputs the first level to the scan signal output terminal under the control of the second clock signal (CK2) to maintain the inactive level output of the scan signal (C[n]) of this stage.

21. The shift register unit as described in claim 20, characterized in that, The second sustaining unit includes a ninth transistor, a tenth transistor, and an eleventh transistor; The ninth transistor is connected between the scan signal output terminal and the first level. When the scan signal (C[n]) of this stage is output at an effective level, the tenth transistor, under the control of the scan signal (C[n]) of this stage input to the control terminal, pulls the potential of the control terminal of the ninth transistor to an ineffective level. When the scan signal (C[n]) of this stage is output at an ineffective level, the eleventh transistor, under the control of the second clock signal (CK2) input to the control terminal, pulls the potential of the control terminal of the ninth transistor to an effective level, so that the ninth transistor outputs the first level to the scan signal output terminal.

22. A gate driving circuit, characterized in that, include: The shift register, start signal line, and common ground line are as described in any one of claims 1-21; The start signal line is connected to at least the scan signal input terminal of the first-stage shift register unit and the scan signal input terminal of the last-stage shift register unit; For two adjacent shift register units in the shift register, the first clock signal terminal of the preceding shift register unit and the first clock signal terminal of the following shift register unit are input with different clock signals.

23. An active display, characterized in that... include: The display panel has multiple pixel circuits arranged in a two-dimensional pixel matrix, multiple gate scan lines in a first direction connected to each pixel circuit, and multiple data lines in a second direction connected to each pixel circuit. The gate driving circuit as described in claim 22 is used to generate at least a scan signal and provide the required control signal to the corresponding pixel circuit through each row of gate scan lines formed along the first direction to complete the row-by-row scanning of the two-dimensional pixel matrix. A data driving circuit is used to generate a data voltage signal and transmit it to the corresponding pixel circuit through the data line to realize the image grayscale.

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