Shift register circuit and control method therefor, and gate drive circuit and display apparatus

Abstract

A shift register circuit and a control method therefor, and a gate drive circuit and a display apparatus. The shift register circuit comprises an input sub-circuit, an output sub-circuit, a noise reduction sub-circuit and an electric leakage prevention sub-circuit, wherein the input sub-circuit is configured to change, in response to an input control signal from an input control signal terminal, the voltage of a first control node to an operating voltage on the basis of a first input signal from a first input signal terminal; the output sub-circuit is configured to enable, under the control of the first control node, a scan signal terminal to output a gate scan signal on the basis of a clock signal from a clock signal terminal; the noise reduction sub-circuit is configured to change the voltage of the first control node to a non-operating voltage on the basis of a noise reduction signal from a noise reduction signal terminal, and comprises two transistors connected in series, of which a common terminal is connected to an electric leakage prevention node; and the electric leakage prevention sub-circuit is coupled to the electric leakage prevention node, and is configured to charge the electric leakage prevention node when the voltage of the first control node is the operating voltage.

Description

Shift register circuit and its control method, gate drive circuit, display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register circuit and its control method, a gate driving circuit, and a display device. Background Technology

[0002] The gate driving circuit is an important component of a display device. It can include multiple cascaded shift registers, each of which can be electrically connected to one or more scan lines in the display device. The gate driving circuit can sequentially input gate scan signals to multiple scan lines in the display device, enabling the display device to display an image.

[0003] In related technologies, during the process of providing gate scanning signals to the scan lines, the voltage of the scan lines fluctuates (e.g., voltage drop), resulting in poor stability of the output waveform of the shift register circuit. This can cause data to be incorrectly written or fail to be written to the pixel units, affecting display quality. Summary of the Invention

[0004] On one hand, a shift register circuit is provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a noise reduction sub-circuit, and a leakage protection electronic circuit. The input sub-circuit is coupled to an input control signal terminal, a first input signal terminal, and a first control node, and is configured to, in response to an input control signal from the input control signal terminal, change the voltage of the first control node to an operating voltage based on a first input signal from the first input signal terminal. The output sub-circuit is coupled to the first control node, a clock signal terminal, and a scan signal terminal, and is configured to, under the control of the first control node, output a gate scan signal from the scan signal terminal based on a clock signal from the clock signal terminal. The noise reduction sub-circuit is coupled to the first control node and a noise reduction signal terminal, and is configured to change the voltage of the first control node to a non-operating voltage based on a noise reduction signal from the noise reduction signal terminal. The noise reduction sub-circuit includes two transistors connected in series, the common terminal of which is connected to a leakage protection node. The leakage protection electronic circuit is coupled to the leakage protection node and is configured to charge the leakage protection node when the voltage of the first control node is the operating voltage. When the voltage of the first control node is a non-operating voltage, the leakage protection node is discharged.

[0005] In one feasible embodiment, the shift register circuit further includes a control sub-circuit. The control sub-circuit is coupled to a control signal terminal, a first voltage signal terminal, a first control node, and a second control node. The control sub-circuit is configured to switch the voltage of the second control node between an operating voltage and a non-operating voltage based on the voltage of the first control node, a first voltage signal from the first voltage signal terminal, and a control signal from the control signal terminal. The noise reduction sub-circuit includes a first noise reduction sub-circuit, with the first voltage signal terminal coupled to it as the noise reduction signal terminal. The first noise reduction sub-circuit is also coupled to the second control node. The first noise reduction sub-circuit is configured to, when the voltage of the second control node is an operating voltage, set the voltage of the first control node to a non-operating voltage based on the first voltage signal from the first voltage signal terminal. The leakage protection node includes a first leakage protection node, with the common terminal of two transistors connected in series in the first noise reduction sub-circuit connected to the first leakage protection node. The leakage protection electronic circuit includes a first leakage protection electronic circuit coupled to the first leakage protection node.

[0006] In one feasible embodiment, the first leakage protection electronic circuit includes a first capacitor, a first end of the first capacitor being coupled to the first leakage protection node, and a second end of the first capacitor being coupled to a third voltage signal terminal or the scanning signal terminal.

[0007] In one feasible embodiment, the input sub-circuit includes two transistors connected in series, and the first leakage protection node is also coupled to the common terminal of the two transistors connected in series in the input sub-circuit.

[0008] In one feasible embodiment, the noise reduction subcircuit further includes a second noise reduction subcircuit, with the second input signal terminal coupled to the second noise reduction subcircuit as the noise reduction signal terminal. The second noise reduction subcircuit is also coupled to a first reset signal terminal. The second noise reduction subcircuit is configured to, in response to a first reset signal from the first reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a second input signal from the second input signal terminal. The common terminal of the two transistors in series in the second noise reduction subcircuit is connected to the first leakage protection node.

[0009] In one feasible embodiment, the noise reduction subcircuit further includes a third noise reduction subcircuit. The first voltage signal terminal is coupled to the third noise reduction subcircuit as the noise reduction signal terminal, and the third noise reduction subcircuit is also coupled to a second reset signal terminal. The third noise reduction subcircuit is configured to, in response to a second reset signal from the second reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a first input signal from the first input signal terminal. The common terminal of the two transistors connected in series in the third noise reduction subcircuit is connected to the first leakage protection node.

[0010] In one feasible embodiment, the first leakage protection electronic circuit further includes a charge / discharge control unit. The charge / discharge control unit is coupled to the input control signal terminal, the first input signal terminal, the first reset signal terminal, the second input signal terminal, and the first leakage protection node. The charge / discharge control unit is configured to charge the first leakage protection node based on a first input signal from the first input signal terminal in response to an input control signal from the input control signal terminal. The charge / discharge control unit is also configured to discharge the first leakage protection node based on a second input signal from the second input signal terminal in response to a first reset signal from the first reset signal terminal.

[0011] In one feasible embodiment, the charge / discharge control unit includes a first transistor and a second transistor. The control electrode of the first transistor is coupled to the input control signal terminal, the first electrode of the first transistor is coupled to the first input signal terminal, and the second electrode of the first transistor is coupled to the first electrode of the second transistor. The control electrode of the second transistor is coupled to the first reset signal terminal, and the second electrode of the second transistor is coupled to the second input signal terminal. Both the second electrode of the first transistor and the first electrode of the second transistor are coupled to the first leakage protection node.

[0012] In one feasible embodiment, the first leakage protection electronic circuit includes a third transistor. The control electrode of the third transistor is coupled to the first control node, the first electrode of the third transistor is coupled to the control electrode of the third transistor, and the second electrode of the third transistor is coupled to the first leakage protection node.

[0013] In one feasible embodiment, the noise reduction subcircuit further includes a second noise reduction subcircuit. A second input signal terminal is coupled to the second noise reduction subcircuit as the noise reduction signal terminal, and the second noise reduction subcircuit is also coupled to a first reset signal terminal. The second noise reduction subcircuit is configured to, in response to a first reset signal from the first reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a second input signal from the second input signal terminal. The leakage protection node further includes a second leakage protection node, the common terminal of two transistors in series in the second noise reduction subcircuit being connected to the second leakage protection node. The leakage protection electronic circuit further includes a second leakage protection electronic circuit coupled to the second leakage protection node.

[0014] In one feasible embodiment, the second leakage protection electronic circuit includes a second capacitor. A first terminal of the second capacitor is coupled to the second leakage protection node, and a second terminal of the second capacitor is coupled to a third voltage signal terminal or the scan signal terminal.

[0015] In one feasible embodiment, the input sub-circuit includes two transistors connected in series, and the second leakage protection node is also coupled to the common terminal of the two transistors connected in series in the input sub-circuit.

[0016] In one feasible embodiment, the second leakage protection electronic circuit further includes a discharge control unit. The discharge control unit is coupled to the second control node, the first voltage signal terminal, and the second leakage protection node; the discharge control unit is configured to discharge the second leakage protection node based on a first voltage signal from the first voltage signal terminal when the voltage of the second control node is the operating voltage.

[0017] In one feasible embodiment, the discharge control unit includes a fourth transistor. The control electrode of the fourth transistor is coupled to the second control node, the first electrode of the fourth transistor is coupled to the second leakage protection node, and the second electrode of the fourth transistor is coupled to the first voltage signal terminal.

[0018] In one feasible embodiment, the noise reduction subcircuit further includes a third noise reduction subcircuit. The first voltage signal terminal is coupled to the third noise reduction subcircuit as the noise reduction signal terminal, and the third noise reduction subcircuit is also coupled to a second reset signal terminal. The third noise reduction subcircuit is configured to, in response to a second reset signal from the second reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a first input signal from the first input signal terminal. The common terminal of the two transistors connected in series in the third noise reduction subcircuit is connected to the second leakage protection node.

[0019] In one feasible embodiment, the shift register circuit includes at least two control sub-circuits. Each of the at least two control sub-circuits is respectively coupled to at least two control signal terminals, which are configured to sequentially input control signals for controlling the corresponding control sub-circuit to turn on. Each of the at least two control sub-circuits is respectively coupled to a second control node of each of the at least two first noise reduction sub-circuits. The common terminal of each of the at least two first noise reduction sub-circuits is coupled to a first leakage protection node.

[0020] In one feasible embodiment, the shift register circuit includes at least two control sub-circuits. Each of the at least two control sub-circuits is coupled to at least two corresponding control signal terminals, which are configured to sequentially input control signals for controlling the corresponding control sub-circuit to turn on. Each of the at least two control sub-circuits is coupled to one of the second control nodes of at least two first sub-noise reduction circuits. The common connection of each of the at least two first noise reduction sub-circuits is coupled to the first leakage protection node. One control sub-circuit is coupled to one corresponding control signal terminal, and at least two control signal terminals are configured to sequentially input control signals for controlling the control sub-circuit to turn on. The second control nodes of at least two control sub-circuits are both coupled to the first leakage protection node. The leakage protection electronic circuit includes at least two discharge control units, and one discharge control unit is coupled to the second control node of one of the control sub-circuits.

[0021] In one feasible embodiment, the first input signal input to the first input signal terminal and the second input signal input to the second input signal terminal are both constant voltage signals and are inverse signals to each other.

[0022] In one feasible embodiment, the third voltage signal input to the third voltage signal terminal is a constant voltage signal.

[0023] On the other hand, a gate driving circuit is provided. The gate driving circuit includes a plurality of cascaded shift register circuits, wherein the shift register circuits are the shift register circuits described above.

[0024] In another aspect, a display device is provided. The display device includes the gate driving circuit described above and a plurality of scan lines. Each shift register circuit in the gate driving circuit is connected to at least one of the scan lines.

[0025] Furthermore, a control method for a shift register circuit is provided, applied to the aforementioned shift register circuit. The control method includes multiple row scan periods, each row scan period comprising a first stage, a second stage, and a third stage. In the first stage, an input sub-circuit is activated in response to an input control signal from an input control signal terminal, transmitting a first input signal from a first input signal terminal to a first control node, causing the voltage of the first control node to change to its operating voltage; a leakage protection electronic circuit charges a leakage protection node, maintaining the voltage of the first control node at its operating voltage. In the second stage, an output sub-circuit is activated under the control of the first control node, transmitting a clock signal from a clock signal terminal to a scan signal terminal, causing the scan signal terminal to output a gate scan signal; the leakage protection electronic circuit continues to maintain the voltage of the first control node at its operating voltage. In the third stage, a noise reduction sub-circuit is activated, transmitting a noise reduction signal from a noise reduction signal terminal to the first control node, causing the voltage of the first control node to change to its non-operating voltage; the leakage protection electronic circuit discharges the leakage protection node. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 is a structural diagram of a display device according to some embodiments;

[0028] Figure 2 is a circuit block diagram of a display device according to some embodiments;

[0029] Figure 3 is a structural diagram of a gate drive circuit according to some embodiments;

[0030] Figure 4 is one of the circuit diagrams of a shift register according to some embodiments;

[0031] Figure 5 is a timing diagram of a shift register according to some embodiments;

[0032] Figure 6 is one of the circuit diagrams of a shift register according to some embodiments;

[0033] Figure 7 is a timing diagram of a shift register according to some embodiments;

[0034] Figure 8 is one of the circuit diagrams of a shift register according to some embodiments;

[0035] Figure 9 is one of the circuit diagrams of a shift register circuit according to some embodiments;

[0036] Figure 10 is one of the circuit diagrams of a shift register circuit according to some embodiments;

[0037] Figure 11 shows the waveforms of the leakage protection nodes under different connection methods of the leakage protection electronic circuit according to some embodiments;

[0038] Figure 12 is a waveform diagram of the gate scan signal at high frequency according to some embodiments of the gate drive circuit;

[0039] Figure 13 is a waveform diagram of the gate scan signal at low frequency according to some embodiments of the gate drive circuit. Detailed Implementation

[0040] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0042] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0043] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0044] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0045] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0046] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0047] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0048] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] Figure 1 is a structural diagram of a display device according to some embodiments. As shown in Figure 1, embodiments of this disclosure provide a display device 1000, which is a product with image display functionality. Exemplarily, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image.

[0051] For example, the display device 1000 can be any product or component with display functionality, such as a television, laptop computer, tablet computer, personal digital assistant (PDA), mobile phone, watch, clock, calculator, GPS receiver / navigator, camera, camera view display (e.g., a rearview camera display in a vehicle), wearable device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle display, or flight display. For example, as shown in Figure 1, the display device 1000 can be a mobile phone.

[0052] Regarding the type of light emission of the display device 1000, it can be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, or a quantum dot light-emitting diode (QLED) display. Regarding the form of the display device 1000, it can be a flat panel display, a curved display, or a foldable display, etc. Regarding the shape of the display device 1000, it can be rectangular or circular, etc.

[0053] The following describes some embodiments of the present disclosure using a rectangular and planar liquid crystal display device 1000 as an example. However, the implementation of the present disclosure is not limited to this, and any other display device can be considered as long as the same technical concept is applied.

[0054] Figure 2 is a circuit block diagram of a display device according to some embodiments. As shown in Figure 2, the display device 1000 includes a display array 100, a gate driving circuit 200, and a data driving circuit 400.

[0055] The display array 100 includes multiple pixel units (not shown in the figure) arranged in an array, m scan lines for transmitting scan signals, and n data lines for transmitting grayscale data, where m and n are both non-zero integers.

[0056] The gate driving circuit 200 is connected to m scan lines and provides multiple scan signals corresponding to the number of scan lines, thereby selecting multiple pixel units in the display array 100 row by row. In some feasible embodiments, the gate driving circuit 200 can be integrated with the display array 100 on the same substrate to form an array substrate gate driver (GOA).

[0057] The shift register circuit 300 is connected to n data lines. The shift register circuit 300 provides multiple grayscale data corresponding to the number of data lines and provides the multiple grayscale data to the selected pixel unit, thereby enabling the display device 1000 to display an image.

[0058] Referring to Figures 2 and 3, Figure 3 is a structural diagram of a gate driving circuit according to some embodiments. The gate driving circuit 200 includes multiple cascaded shift register circuits 300. One shift register circuit 300 can be connected to at least one scan line to drive at least one row of pixel units. The shift register circuit 300 includes at least a clock signal terminal CLK for receiving a clock signal CLK, a second reset signal terminal RST2 for receiving a second reset signal RST2, an input control signal terminal IPT for receiving an input control signal IPT, a second reset signal terminal RST2 for receiving the second reset signal RST2, and a scan signal terminal Gout for outputting a gate scan signal Gout.

[0059] In a cascaded array of shift register circuits 300, except for the first-stage shift register circuit 300, the input control signal terminal IPT of each of the remaining shift register circuits 300 is connected to the scan signal terminal Gout of the previous-stage shift register circuit 300. Except for the last-stage shift register circuit 300, the first reset signal terminal RST1 of each of the remaining shift register circuits 300 is connected to the scan signal terminal Gout of the next-stage shift register circuit 300. For example, the input control signal terminal IPT of the first-stage shift register circuit 300 is configured to receive a trigger signal STV, and the first reset signal terminal RST1 of the last-stage shift register circuit 300 is configured to receive a first reset signal RST1. This describes the forward scanning scenario. During reverse scanning, the trigger signal STV for the first-stage shift register circuit 300 is replaced with the first reset signal RST1, and the first reset signal RST1 for the last-stage shift register circuit 300 is replaced with the trigger signal STV.

[0060] The gate drive circuit 200 includes a second reset signal line RST2. The second reset signal terminals RST2 of each stage of the shift register circuit 300 are all connected to the second reset signal line RST2 to receive the second reset signal RST2. The gate drive circuit 200 also includes a first clock signal line CLK1 and a second clock signal line CLK2. For example, the first clock signal line CLK1 is configured to be connected to the clock signal terminal CLK of the odd-numbered stage shift register circuit 300, and the second clock signal line CLK2 is configured to be connected to the clock signal terminal CLK of the even-numbered stage shift register circuit 300.

[0061] In some feasible embodiments, the first clock signal line CLK1 is configured to be connected to the clock signal terminal CLK of the even-level shift register circuit 300, and the second clock signal line CLK2 is configured to be connected to the clock signal terminal CLK of the odd-level shift register circuit 300.

[0062] For example, the first clock signal CLK1 and the second clock signal CLK2 provided on the first clock signal line CLK1 and the second clock signal line CLK2 can adopt the signal timing shown in FIG. 7, and the two are complementary to each other. Furthermore, in different embodiments, depending on different configurations, more clock signal lines can be used to provide more different timing sequences for the clock signal CLK, such as 4 clock signal lines or 6 clock signal lines, etc.

[0063] Based on the above, the gate driving circuit 200 can drive each row of pixel units sequentially from one side of the display array 100, i.e., single-sided driving. The gate driving circuit 200 can also drive each row of pixel units sequentially from opposite sides of the display array 100, i.e., cross-driving. The gate driving circuit 200 can also simultaneously drive each row of pixel units sequentially from opposite sides of the display array 100, i.e., dual-sided driving. Figure 2 illustrates this using dual-sided driving as an example.

[0064] In some feasible embodiments, the display device 1000 further includes a timing control circuit 500, which is configured, for example, to provide a clock signal CLK to a first clock signal line CLK1 and a second clock signal line CLK2, and to provide a second reset signal RST2 to a second reset signal line RST2. The timing control circuit 500 is also configured to provide a trigger signal STV and a first reset signal RST1.

[0065] Figure 4 is one of the circuit diagrams of a shift register according to some embodiments. The shift register circuit 300 includes an input sub-circuit 310, an output sub-circuit 320, a noise reduction sub-circuit 330, a leakage protection electronic circuit 340, and a control sub-circuit 350.

[0066] The input sub-circuit 310 is coupled to the input control signal terminal IPT, the first input signal terminal CN, and the first control node PU. The input sub-circuit 310 is configured to, in response to the input control signal IPT from the input control signal terminal IPT, cause the voltage of the first control node PU to change to an operating voltage based on the first input signal CN from the first input signal terminal CN. The operating voltage is either a high level or a low level, and the non-operating voltage is the other of a high level or a low level. For example, the operating voltage can be high, and the non-operating voltage can be low. In some feasible embodiments, the operating voltage can be low, and the non-operating voltage can be high.

[0067] The output sub-circuit 320 is coupled to the first control node PU, the clock signal terminal CLK, and the scan signal terminal Gout. The output sub-circuit 320 is configured to, under the control of the first node, cause the scan signal terminal Gout to output the gate scan signal Gout based on the clock signal CLK from the clock signal terminal CLK.

[0068] The noise reduction sub-circuit 330 is coupled to the first control node PU and the noise reduction signal terminal. The noise reduction sub-circuit 330 is configured to change the voltage of the first control node PU to a non-operating voltage based on the noise reduction signal from the noise reduction signal terminal. For example, the noise reduction sub-circuit 330 includes two transistors connected in series, with their common terminal connected to the leakage protection node S.

[0069] The leakage protection electronic circuit 340 is coupled to the leakage protection node S. The leakage protection electronic circuit 340 is configured to charge the leakage protection node S when the voltage of the first control node PU is the operating voltage. The leakage protection electronic circuit 340 is also configured to discharge the leakage protection node S when the voltage of the first control node PU is not the operating voltage.

[0070] The control sub-circuit 350 is coupled to the control signal terminal VDDA, the first voltage signal terminal VGLA, the first control node PU, and the second control node PDA. The control sub-circuit 350 is configured to switch the voltage of the second control node PDA between the operating voltage and the non-operating voltage based on the voltage of the first control node PU, the first voltage signal VGLA from the first voltage signal terminal VGLA, and the control signal VDDA from the control signal terminal VDDA.

[0071] In some feasible embodiments, the noise reduction sub-circuit 330 includes a first noise reduction sub-circuit 331, a second noise reduction sub-circuit 332, and a third noise reduction sub-circuit 333. A first voltage signal terminal VGLA is coupled to the first noise reduction sub-circuit 331 as a noise reduction signal terminal, and the first noise reduction sub-circuit 331 is also coupled to the second control node PDA. The first noise reduction sub-circuit 331 is configured to, when the voltage of the second control node PDA is the operating voltage, make the voltage of the first control node PDA a non-operating voltage based on the first voltage signal VGLA from the first voltage signal terminal VGLA.

[0072] The second input signal terminal CNB is coupled to the second noise reduction sub-circuit 332 as a noise reduction signal terminal. The second noise reduction sub-circuit 332 is also coupled to the first reset signal terminal RST1. The second noise reduction sub-circuit 332 is configured to, in response to the first reset signal RST1 from the first reset signal terminal RST1, set the voltage of the first control node PU to a non-operating voltage based on the second input signal CNB from the second input signal terminal CNB.

[0073] The first voltage signal terminal VGLA is coupled to the third noise reduction sub-circuit 333 as a noise reduction signal terminal. The third noise reduction sub-circuit 333 is also coupled to the second reset signal terminal RST2. The third noise reduction sub-circuit 333 is configured to, in response to the second reset signal RST2 from the second reset signal terminal RST2, set the voltage of the first control node PU to a non-operating voltage based on the first input signal CN from the first input signal terminal CN.

[0074] Both the first input signal CN at the first input signal terminal CN and the second input signal CNB at the second input signal terminal CNB are constant voltages, and their phases are opposite. When the first input signal CN is high and the second input signal CNB is low, forward scanning of the shift register circuit 300 can be achieved. When the first input signal CN is low and the second input signal CNB is high, reverse scanning of the shift register circuit 300 can be achieved. For example, forward scanning involves scanning from the first-stage shift register circuit 300 to the last-stage shift register circuit 300, and reverse scanning involves scanning from the last-stage shift register circuit 300 back to the first-stage shift register circuit 300.

[0075] For example, the input sub-circuit 310 includes an input transistor M20 and an input transistor M21 connected in series. The first terminal of the input transistor M20 is coupled to the first input signal terminal CN to receive the first input signal CN, and the second terminal is coupled to the first terminal of the input transistor M21. That is, the second terminal of the input transistor M20 is the common terminal of the input transistors M20 and M21, and this common terminal is connected to the leakage protection node S. The second terminal of the input transistor M21 is coupled to the first control node PU. The control terminals of both the input transistors M20 and M21 are coupled to the input control signal terminal IPT to receive the input control signal IPT.

[0076] The output sub-circuit 320 includes an output transistor M5 and an output capacitor C0. The first terminal of the output transistor M5 is coupled to the clock signal terminal CLK to receive the clock signal CLK, the second terminal is coupled to the scan signal terminal Gout to provide the gate scan signal Gout, and the control terminal is coupled to the first node. The first terminal of the output capacitor C0 is coupled to the control terminal of the output transistor M5, and the second terminal is coupled to the second terminal of the output transistor M5.

[0077] The first noise reduction sub-circuit 331 includes a first noise reduction transistor M10 and a second noise reduction transistor M11 connected in series. The first terminal of the first noise reduction transistor M10 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the second noise reduction transistor M11. That is, the second terminal of the first noise reduction transistor M10 is the common terminal of the first noise reduction transistor M10 and the second noise reduction transistor M11, and this common terminal is connected to the leakage protection node S. The first voltage signal terminal VGLA is coupled to the second terminal of the second noise reduction transistor M11 as a noise reduction signal terminal.

[0078] The second noise reduction sub-circuit 332 includes a first reset transistor M0 and a second reset transistor M4 connected in series. The first terminal of the first reset transistor M0 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the second reset transistor M4. That is, the second terminal of the first reset transistor M0 is the common terminal of the first reset transistor M0 and the second reset transistor M4, and this common terminal is connected to the leakage protection node S. The first input signal terminal CN is coupled to the second terminal of the second reset transistor M4 as a noise reduction signal terminal. The control terminals of both the first reset transistor M0 and the second reset transistor M4 are coupled to the first reset signal terminal RST1 to receive the first reset signal RST1.

[0079] The third noise reduction sub-circuit 333 includes a third reset transistor M14 and a fourth reset transistor M15 connected in series. The first terminal of the third reset transistor M14 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the fourth reset transistor M15. That is, the second terminal of the third reset transistor M14 is a common terminal for both the third reset transistor M14 and the fourth reset transistor M15, and this common terminal is connected to the leakage protection node S. The first input signal terminal CN is coupled to the second terminal of the fourth reset transistor M15 as a noise reduction signal terminal. The control terminals of both the third reset transistor M14 and the fourth reset transistor M15 are coupled to the second reset signal terminal RST2 to receive the second reset signal RST2.

[0080] The leakage protection electronic circuit 340 includes a first capacitor C1, with a first end coupled to a leakage protection node S and a second end coupled to a third voltage signal terminal VGLC. In some feasible embodiments, the first end of the first capacitor C1 is coupled to the leakage protection node S and the second end is coupled to the scan signal terminal Gout.

[0081] The control sub-circuit 350 includes a first control transistor M6 and a second control transistor M8 connected in series. The first terminal of the first control transistor M6 is coupled to the control signal terminal VDDA, the second terminal is coupled to the second control node PDA, and the control terminal is coupled to the first terminal of the first control transistor M6. The first terminal of the second control transistor M8 is coupled to the second control node PDA, the second terminal is coupled to the first voltage signal terminal VGLA, and the control terminal is coupled to the first control node PU.

[0082] The shift register circuit 300 also includes an output noise reduction transistor M17, with its first terminal coupled to the scan signal terminal Gout, its second terminal coupled to the second voltage signal terminal VGLB, and its control terminal coupled to the second control node PDA.

[0083] Referring to Figures 4 and 5, the control method of the shift register circuit 300 will be described. Figure 5 is a timing diagram of a shift register according to some embodiments. In Figure 5, from top to bottom, are the input control signal IPT, clock signal CLK, first reset signal RST1, control signal VDDA, first input signal CN, second input signal CNB, voltage of the first control node PU, voltage of the leakage protection node S, voltage of the second control node PDA, and gate scan signal Gout. The following description takes the forward scan of the shift register circuit 300 as an example. The control method of the shift register circuit 300 includes multiple scan periods, each scan period including a first stage t0, a second stage t1, and a third stage t2.

[0084] In the first stage t0, the input sub-circuit 310 responds to the input control signal IPT from the input control signal terminal IPT by turning on, transmitting the first input signal CN from the first input signal terminal CN to the first control node PU, causing the voltage of the first control node PU to change to the operating voltage. At the same time, it charges the 240 pairs of leakage protection nodes S, so that the voltage of the first control node PU is maintained at the operating voltage.

[0085] For example, the input control signal IPT is the operating voltage, and input transistors M20 and M21 are turned on. The turn on input transistor M20 transmits the first input signal CN to the leakage protection node S, which, in conjunction with the leakage protection electronic circuit 340, charges the leakage protection node S, causing it to change to the operating level. The turn on input transistors M20 and M21 transmit the first input signal CN to the first control node PU, charging it. The voltage of the first control node PU changes to the operating voltage, and the second control transistor M8 turns on, causing the second control node PDA to change to a non-operating voltage. The non-operating voltage second control node PDA turns off the output noise reduction transistor M17, thereby disconnecting the current path between the scan signal terminal Gout and the second voltage signal terminal VGLB.

[0086] On one hand, during the process of the input sub-circuit 310 charging the first control node PU, when the voltage of the first control node PU has not changed to a level sufficient to turn on the second control transistor M8, thereby causing the voltage of the second control node PDA to change to a non-operating voltage, the voltage of the second control node PDA remains at the operating voltage, and the first noise reduction transistor M10 and the second noise reduction transistor M11 are in the conducting state. At this time, the input sub-circuit 310, in conjunction with the leakage protection electronic circuit 340, charges the leakage protection node S. The leakage protection node S charges the first control node PU through the conducting first noise reduction transistor M10, causing the first control node PU to quickly change to the operating voltage, thereby causing the voltage of the second control node to change to a non-operating voltage. To avoid the risk of a race condition arising when the first noise reduction transistor M10 and the second noise reduction transistor M11 are in the on state, the charging rate of the first input signal CN through the input sub-circuit 310 to the first control node PU is less than or equal to the discharge rate of the first control node PU through the first noise reduction transistor M10 and the second noise reduction transistor M11.

[0087] On the other hand, in the first stage t0, the voltage of the leakage prevention node S is equal to the voltage of the first control node PU. The gate-source voltage Vgs of the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 are <0, and the source-drain voltage Vds = 0. This makes the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 turn off more thoroughly, preventing the first control node PU from leaking current through the noise reduction sub-circuit where the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 are located. This reduces the power consumption of the display device 1000 and increases the battery life of the display device 1000.

[0088] In the second stage t1, the output sub-circuit 320 is turned on under the control of the first control node PU, transmitting the clock signal CLK from the clock signal terminal CLK to the scan signal terminal Gout, causing the scan signal terminal Gout to output the gate scan signal Gout. The leakage protection electronic circuit 340 continues to maintain the voltage of the first control node PU at the operating voltage.

[0089] For example, when the input control signal IPT changes to a non-operating voltage, the input transistors M20 and M21 of the input sub-circuit 310 turn off, stopping the charging of the first control node PU and the leakage protection node S. In the second stage t1, the output transistor M5 turns on, and the output sub-circuit 320 outputs the clock signal CLK as the gate scan signal Gout from the scan signal terminal Gout. The clock signal CLK changes to the operating voltage in stage t1, so the gate scan signal Gout also changes to the operating voltage. Furthermore, the output transistor M5 and the output capacitor C0 are output coupled, the voltage of the first control node PU increases, causing the output transistor M5 to fully turn on the output gate scan signal Gout. The voltage of the leakage protection node S is maintained at the operating voltage due to the presence of the storage capacitor and / or parasitic capacitance (as shown by the solid line in the voltage timing diagram of the leakage protection node S in Figure 5), or increases due to capacitive coupling (as shown by the dashed line in the voltage timing diagram of the leakage protection node S in Figure 5). The voltage of the first control node PU remains the operating voltage, keeping the second control transistor M8 of the control sub-circuit 350 on, thereby keeping the voltage of the second control node PDA at a non-operating voltage.

[0090] In the second stage t1, the voltage of the leakage prevention node S is equal to the voltage of the first control node PU. The gate-source voltage Vgs of the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 are less than 0, and the source-drain voltage Vds is equal to 0. This makes the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 turn off more thoroughly, preventing the first control node PU from leaking current through the noise reduction sub-circuit 330 where the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 are located. This keeps the output transistor M5 of the output sub-circuit 320 fully turned on, thereby ensuring the stability of the gate scan signal Gout waveform output by the output sub-circuit 320.

[0091] In the third stage t2, the noise reduction sub-circuit 330 is turned on, transmitting the noise reduction signal from the noise reduction signal terminal to the first control node PU, causing the voltage of the first control node PU to change to a non-operating voltage. The leakage protection electronic circuit 340 discharges to the leakage protection node S.

[0092] For example, the first reset signal RST1 changes to the operating voltage, turning on the first reset transistor M0 and the third reset transistor M14. The third reset transistor M14 discharges through the leakage protection node S, and the first reset transistors M0 and M14 discharge through the first control node PU, thereby changing the voltages of the leakage protection node S and the first control node PU to non-operating voltages. With the first control node PU at a non-operating voltage, the second control transistor M8 turns off, and the control signal, through the first control transistor M6, causes the voltage of the second control node PDA to change to the operating voltage, turning on the first noise reduction transistor M10 and the second noise reduction transistor M11, thereby maintaining the voltage of the first control node PU at a non-operating voltage. Simultaneously, the second noise reduction transistor M11 also maintains the voltage of the leakage protection node S at a non-operating voltage.

[0093] The voltages of the first control node PU and the leakage protection node S are non-operating voltages, making the source-drain voltage Vds of the first noise reduction transistor M10, the first reset transistor M0, and the third reset transistor M14 zero. The voltage of the leakage protection node S is also non-operating, making the source-drain voltage Vds of the second noise reduction transistor M11, the second reset transistor M4, and the first reset transistor M15 zero. In the third stage t2, the source-drain voltage difference of the transistors related to the noise reduction sub-circuit 330 is zero in the off state, preventing transistor characteristic shift due to prolonged operation and increasing the expected lifespan of the shift register circuit 300. Simultaneously, the transistors included in the shift register circuit 300 do not experience characteristic shifts, allowing them to respond to corresponding signals for on or off operation. This improves the brightness uniformity of the display device 1000, reduces the probability of crosstalk and other risks, and thus improves the display quality of the display device 1000.

[0094] Figure 6 is one of the circuit diagrams of a shift register according to some embodiments. The shift register circuit 300 includes an input sub-circuit 310, an output sub-circuit 320, a noise reduction sub-circuit 330, a leakage protection electronic circuit 340, and a control sub-circuit 350.

[0095] The input sub-circuit 310 is coupled to the input control signal terminal IPT, the first input signal terminal CN, and the first control node PU. The input sub-circuit 310 is configured to, in response to the input control signal IPT from the input control signal terminal IPT, cause the voltage of the first control node PU to change to an operating voltage based on the first input signal CN from the first input signal terminal CN. The operating voltage is either a high level or a low level, and the non-operating voltage is the other of a high level or a low level. For example, the operating voltage can be high, and the non-operating voltage can be low. In some feasible embodiments, the operating voltage can be low, and the non-operating voltage can be high.

[0096] The output sub-circuit 320 is coupled to the first control node PU, the clock signal terminal CLK, and the scan signal terminal Gout. The output sub-circuit 320 is configured to, under the control of the first control node PU, cause the scan signal terminal Gout to output the gate scan signal Gout based on the clock signal CLK from the clock signal terminal CLK.

[0097] The noise reduction sub-circuit 330 is coupled to the first control node PU and the noise reduction signal terminal. The noise reduction sub-circuit 330 is configured to change the voltage of the first control node PU to a non-operating voltage based on the noise reduction signal from the noise reduction signal terminal. For example, the noise reduction sub-circuit 330 includes two transistors connected in series, with their common terminal connected to the leakage protection node S.

[0098] The leakage protection electronic circuit 340 is coupled to the leakage protection node S. The leakage protection electronic circuit 340 is configured to charge the leakage protection node S when the voltage of the first control node PU is the operating voltage. The leakage protection electronic circuit 340 is also configured to discharge the leakage protection node S when the voltage of the first control node PU is not the operating voltage.

[0099] The control sub-circuit 350 is coupled to a control signal terminal, a first voltage signal terminal VGLA, a first control node PU, and a second control node PDA (i.e., a second control node PDB). The control sub-circuit 350 is configured to switch the voltages of the second control node PDA and the second control node PDB between operating voltages and non-operating voltages based on the voltage of the first control node PU, the first voltage signal VGLA from the first voltage signal terminal VGLA, the control signal VDDA from the control signal terminal VDDA, and the control signal VDDB from the control signal terminal VDDB.

[0100] In some feasible embodiments, the noise reduction sub-circuit 330 includes a first noise reduction sub-circuit 331, a second noise reduction sub-circuit 332, a third noise reduction sub-circuit 333, and a first noise reduction sub-circuit 334. A first voltage signal terminal VGLA is coupled to the first noise reduction sub-circuit 331 as a noise reduction signal terminal. The first noise reduction sub-circuit 331 is also coupled to the second control node PDA and the second control node PDB. The first noise reduction sub-circuit 331 is configured to, when the voltage of at least one of the second control node PDA and the second control node PDB is the operating voltage, set the voltage of the first control node PU to a non-operating voltage based on the first voltage signal VGLA from the first voltage signal terminal VGLA.

[0101] The second input signal terminal CNB is coupled to the second noise reduction sub-circuit 332 as a noise reduction signal terminal. The second noise reduction sub-circuit 332 is also coupled to the first reset signal terminal RST1. The second noise reduction sub-circuit 332 is configured to, in response to the first reset signal RST1 from the first reset signal terminal RST1, set the voltage of the first control node PU to a non-operating voltage based on the second input signal CNB from the second input signal terminal CNB.

[0102] The first voltage signal terminal VGLA is coupled to the third noise reduction sub-circuit 333 as a noise reduction signal terminal. The third noise reduction sub-circuit 333 is also coupled to the second reset signal terminal RST2. The third noise reduction sub-circuit 333 is configured to, in response to the second reset signal RST2 from the second reset signal terminal RST2, set the voltage of the first control node PU to a non-operating voltage based on the first input signal from the first input signal terminal CN.

[0103] The first voltage signal terminal VGLA is coupled to the first noise reduction sub-circuit 334 as a noise reduction signal terminal. The first noise reduction sub-circuit 334 is also coupled to the second control node PDA and the second control node PDB. The first noise reduction sub-circuit 334 is configured to make the voltage of the first control node PU a non-operating voltage based on the first voltage signal VGLA from the first voltage signal terminal VGLA when the voltage of at least one of the second control node PDA and the second control node PDB is the operating voltage.

[0104] In some feasible embodiments, the control subcircuit 350 includes a first control subcircuit 351 and a second control subcircuit 352. The first control subcircuit 351 is coupled to a control signal terminal VDDA, a first voltage signal terminal VGLA, a first control node PU, and a second control node PDA. The first control subcircuit 351 is configured to switch the voltage of the second control node PDA between an operating voltage and a non-operating voltage based on the voltage of the first control node PU, a first voltage signal VGLA from the first voltage signal terminal VGLA, and a control signal VDDA from the control signal terminal VDDA.

[0105] The second control sub-circuit 352 is coupled to the control signal terminal VDDB, the first voltage signal terminal VGLA, the first control node PU, and the second control node PDB. The second control sub-circuit 352 is configured to switch the voltage of the second control node PDB between the operating voltage and the non-operating voltage based on the voltage of the first control node PU, the first voltage signal VGLA from the first voltage signal terminal VGLA, and the control signal VDDB from the control signal terminal VDDB.

[0106] In some feasible embodiments, the control signal VDDA received by the control signal terminal VDDA of the first control sub-circuit 351 and the control signal VDDB received by the control signal terminal VDDB of the second control sub-circuit 352 are both pulse signals, and their phases are opposite, as shown in Figure 6. The control signal terminals VDDA and VDDB are configured to sequentially input control signals VDDA and VDDB to control the activation of either the first or second control sub-circuit 351, causing the first and second control sub-circuit 352 to operate alternately. For example, the control signals VDDA and VDDB can use clock signals CLK with opposite phases, such as a first clock signal CLK1 and a second clock signal CLK2. In some feasible embodiments, the switching frequency of the control signals VDDA and VDDB can also be once per frame or once every few frames.

[0107] Both the first input signal CN at the first input signal terminal CN and the second input signal CNB at the second input signal terminal CNB are constant voltages with opposite phases. When the first input signal CN is high and the second input signal CNB is low, forward scanning of the shift register circuit 300 can be achieved. When the first input signal CN is low and the second input signal CNB is high, reverse scanning of the shift register circuit 300 can be achieved.

[0108] For example, the input sub-circuit 310 includes an input transistor M20 and an input transistor M21 connected in series. The first terminal of the input transistor M20 is coupled to the first input signal terminal CN to receive the first input signal CN, and the second terminal is coupled to the first terminal of the input transistor M21. That is, the second terminal of the input transistor M20 is the common terminal of the input transistors M20 and M21, and this common terminal is connected to the leakage protection node S. The second terminal of the input transistor M21 is coupled to the first control node PU. The control terminals of both the input transistors M20 and M21 are coupled to the input control signal terminal IPT to receive the input control signal IPT.

[0109] The output sub-circuit 320 includes an output transistor M5 and an output capacitor C0. The first terminal of the output transistor M5 is coupled to the clock signal terminal CLK to receive the clock signal CLK, the second terminal is coupled to the scan signal terminal to provide the gate scan signal Gout, and the control terminal is coupled to the first node. The first terminal of the output capacitor C0 is coupled to the control terminal of the output transistor M5, and the second terminal is coupled to the second terminal of the output transistor M5.

[0110] The first noise reduction sub-circuit 331 includes a first noise reduction transistor M10 and a second noise reduction transistor M11 connected in series. The first terminal of the first noise reduction transistor M10 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the second noise reduction transistor M11. That is, the second terminal of the first noise reduction transistor M10 is the common terminal of the first noise reduction transistor M10 and the second noise reduction transistor M11, and this common terminal is connected to the leakage protection node S. The first voltage signal terminal VGLA is coupled to the second terminal of the second noise reduction transistor M11 as a noise reduction signal terminal. The control terminals of both the first noise reduction transistor M10 and the second noise reduction transistor M11 are coupled to the second control node PDA.

[0111] The second noise reduction sub-circuit 332 includes a first reset transistor M0 and a second reset transistor M4 connected in series. The first terminal of the first reset transistor M0 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the second reset transistor M4. That is, the second terminal of the first reset transistor M0 is the common terminal of the first reset transistor M0 and the second reset transistor M4, and this common terminal is connected to the leakage protection node S. The first input signal terminal CN is coupled to the second terminal of the second reset transistor M4 as a noise reduction signal terminal. The control terminals of both the first reset transistor M0 and the second reset transistor M4 are coupled to the first reset signal terminal RST1 to receive the first reset signal RST1.

[0112] The third noise reduction sub-circuit 333 includes a third reset transistor M14 and a fourth reset transistor M15 connected in series. The first terminal of the third reset transistor M14 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the fourth reset transistor M15. That is, the second terminal of the third reset transistor M14 is a common terminal for both the third reset transistor M14 and the fourth reset transistor M15, and this common terminal is connected to the leakage protection node S. The first input signal terminal CN is coupled to the second terminal of the fourth reset transistor M15 as a noise reduction signal terminal. The control terminals of both the third reset transistor M14 and the fourth reset transistor M15 are coupled to the second reset signal terminal RST2 to receive the second reset signal RST2.

[0113] The first noise reduction sub-circuit 334 includes a third noise reduction transistor M12 and a fourth noise reduction transistor M13 connected in series. The first terminal of the third noise reduction transistor M12 is coupled to the first control node PU, and the second terminal is coupled to the first terminal of the fourth noise reduction transistor M13. That is, the second terminal of the third noise reduction transistor M12 is the common terminal of the third noise reduction transistor M12 and the fourth noise reduction transistor M13, and this common terminal is connected to the leakage protection node S. The first voltage signal terminal VGLA is coupled to the second terminal of the fourth noise reduction transistor M13 as a noise reduction signal terminal. The control terminals of both the third noise reduction transistor M12 and the fourth noise reduction transistor M13 are coupled to the second control node PDB.

[0114] The leakage protection electronic circuit 340 includes a first capacitor C1, with a first end of the first capacitor C1 coupled to the leakage protection node S and a second end coupled to the third voltage signal terminal VGLC.

[0115] In some feasible embodiments, the first end of the first capacitor C1 is coupled to the leakage protection node S, and the second end is coupled to the scan signal terminal Gout. As shown in Figure 10, which is one of the circuit diagrams of a shift register circuit according to some embodiments, the remaining circuit structure and connection relationship of the shift register circuit 300 provided in Figure 10 are basically the same as those of the shift register circuit 300 provided in Figure 6, and therefore will not be described again. Figure 11 is a waveform diagram of the leakage protection node S under different connection methods of the leakage protection electronic circuit according to some embodiments. In Figure 11, the horizontal axis is time t in milliseconds, and the vertical axis is voltage U in volts. The dashed line is the waveform diagram of the leakage protection node S of the shift register circuit 300 shown in Figure 6. It can be seen that in the first stage t0, the voltage of the leakage protection node S changes to the working voltage, and in the second stage t1, the voltage of the leakage protection node S is close to the non-working voltage. The solid line represents the waveform of the leakage protection node S in the shift register circuit 300 shown in Figure 10. Because the first capacitor C1 is connected to the scan signal terminal Gout, the waveform of the leakage protection node S is similar to that of the first control node PU in Figure 7. In the first stage t0, the voltage of the leakage protection node S changes to the operating voltage. In the second stage t1, the first capacitor C1 couples, and the voltage of the leakage protection node S rises again. During the stage where the voltage of the first control node PU is the operating voltage, the voltage of the leakage protection node S remains at the operating voltage. That is, throughout the entire first stage t0 and the second stage t1, the voltage of the leakage protection node S is the operating voltage, thereby ensuring that the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 are turned off, avoiding leakage at the first control node PU, thus ensuring that the voltage of the first control node PU is stable at the operating voltage, fully turning on the output transistor M5, and improving the stability of the gate scan signal Gout.

[0116] Referring again to Figure 6, the first control sub-circuit 351 includes a first control transistor M6 and a second control transistor M8 connected in series. The first terminal of the first control transistor M6 is coupled to the control signal terminal VDDA, the second terminal is coupled to the second control node PDA, and the control terminal is coupled to the first terminal of the first control transistor M6. The first terminal of the second control transistor M8 is coupled to the second control node PDA, the second terminal is coupled to the first voltage signal terminal VGLA, and the control terminal is coupled to the first control node PU.

[0117] The second control sub-circuit 352 includes a third control transistor M7 and a fourth control transistor M9 connected in series. The first terminal of the third control transistor M7 is coupled to the control signal terminal VDDB, the second terminal is coupled to the second control node PDB, and the control terminal is coupled to the first terminal of the third control transistor M7. The first terminal of the fourth control transistor M9 is coupled to the second control node PDB, the second terminal is coupled to the first voltage signal terminal VGLA, and the control terminal is coupled to the first control node PU.

[0118] The shift register circuit 300 also includes output noise reduction transistors M17 and M16. The first terminal of output noise reduction transistor M17 is coupled to the scan signal terminal Gout, the second terminal is coupled to the second voltage signal terminal VGLB, and the control terminal is coupled to the second control node PDA. The first terminal of output noise reduction transistor M16 is coupled to the scan signal terminal Gout, the second terminal is coupled to the second voltage signal terminal VGLB, and the control terminal is coupled to the second control node PDB.

[0119] Referring to Figures 3, 6, and 7, the control method of the shift register circuit 300 will be described. Figure 7 is a timing diagram of a shift register according to an embodiment. In Figure 7, from top to bottom, are the input control signal IPT, the first clock signal CLK1, the second clock signal CLK2, the first reset signal RST1, the control signal VDDA, the control signal VDDB, the first input signal CN, the second input signal CNB, the voltage of the first control node PU, the voltage of the leakage protection node S, the voltages of the second control node PDA and the second control node PDB, and the gate scan signal Gout. The clock signal terminal CLK of the shift register circuit 300 is connected to either the first clock signal line CLK1 or the second clock signal line CLK2, so that either the first clock signal CLK1 or the second clock signal CLK2 is provided as the clock signal CLK to the clock signal terminal CLK of the shift register circuit 300. The control method of the shift register circuit 300 includes multiple scan periods, each scan period including a first stage t0, a second stage t1, and a third stage t2.

[0120] In the first stage t0, the input sub-circuit 310 turns on in response to the input control signal IPT from the input control signal terminal IPT. The input control signal IPT is, for example, a trigger signal STV or the gate scan signal Gout of the preceding shift register circuit 300. The first input signal CN from the first input signal terminal CN is transmitted to the first control node PU, causing the voltage of the first control node PU to change to the operating voltage. At the same time, the leakage protection nodes S of 240 are charged, so that the voltage of the first control node PU is maintained at the operating voltage.

[0121] For example, the input control signal IPT is the operating voltage, and input transistors M20 and M21 are turned on. The turn on input transistor M20 transmits the first input signal CN to the leakage protection node S, which, in conjunction with the leakage protection electronic circuit 340, charges the leakage protection node S, causing it to change to the operating level. The turn on input transistors M20 and M21 transmits the first input signal CN to the first control node PU, charging it. The voltage of the first control node PU changes to the operating voltage, and the second control transistor M8 and the fourth control transistor M9 are turned on, causing the second control node PDA and the second control node PDB to change to non-operating voltages. The non-operating voltage second control node PDA turns off the output noise reduction transistor M17, and the non-operating voltage second control node PDB turns off the output noise reduction transistor M16, thereby disconnecting the current path between the scan signal terminal Gout and the second voltage signal terminal VGLB.

[0122] On one hand, during the process of the input sub-circuit 310 charging the first control node PU, when the voltage of the first control node PU has not changed to a level sufficient to turn on the second control transistor M8 and the fourth control transistor M9, thereby causing the voltages of the second control nodes PDA and PDB to change to non-operating voltages, the voltages of the second control nodes PDA and PDB remain operating voltages, and the first noise reduction transistor M10, the second noise reduction transistor M11, the third noise reduction transistor M12, and the fourth noise reduction transistor M13 are in the conducting state. At this time, the input sub-circuit 310, in conjunction with the leakage protection electronic circuit 340, charges the leakage protection node S. The leakage protection node S charges the first control node PU through the conducting first noise reduction transistor M10 and the third noise reduction transistor M12, causing the first control node PU to quickly change to the operating voltage, thereby causing the voltages of the second control nodes PDA and PDB to change to non-operating voltages. To avoid the risk of a race condition arising when the first noise reduction transistor M10, the second noise reduction transistor M11, the third noise reduction transistor M12, and the fourth noise reduction transistor M13 are in the on state, the charging rate of the first input signal CN through the input sub-circuit 310 to the first control node PU is less than or equal to the discharging rate of the first control node PU through the first noise reduction transistor M10, the second noise reduction transistor M11, the third noise reduction transistor M12, and the fourth noise reduction transistor M14, causing the voltage of the first control node PU to fail to change to the operating voltage.

[0123] On the other hand, in the first stage t0, the voltage of the leakage prevention node S is equal to the voltage of the first control node PU. The gate-source voltage Vgs of the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 are <0, and the source-drain voltage Vds is =0. This makes the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 turn off more thoroughly, preventing the first control node PU from leaking current through the noise reduction sub-circuit where the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 are located. This makes the gate scan signal Gout output by the shift register circuit 300 more stable, thereby reducing the power consumption of the display device 1000, increasing the battery life of the display device 1000, and improving the driving stability of the shift register circuit 300.

[0124] In the second stage t1, the output sub-circuit 320 is turned on under the control of the first control node PU, transmitting the clock signal CLK from the clock signal terminal CLK to the scan signal terminal Gout, causing the scan signal terminal Gout to output the gate scan signal Gout. The leakage protection electronic circuit 340 continues to maintain the voltage of the first control node PU at the operating voltage.

[0125] For example, when the input control signal IPT changes to a non-operating voltage, the input transistors M20 and M21 of the input sub-circuit 310 turn off, stopping the charging of the first control node PU and the leakage protection node S. In the second stage t1, the output transistor M5 turns on, and the output sub-circuit 320 outputs the clock signal CLK as the gate scan signal Gout from the scan signal terminal Gout. The clock signal CLK changes to the operating voltage in stage t1, so the gate scan signal Gout also changes to the operating voltage. Furthermore, the output transistor M5 and the output capacitor C0 are output coupled, the voltage of the first control node PU increases, causing the output transistor M5 to fully turn on the output gate scan signal Gout. The voltage of the leakage protection node S is maintained at the operating voltage due to the presence of the storage capacitor and / or parasitic capacitance (as shown by the solid line in the voltage timing diagram of the leakage protection node S in Figure 7), or increases due to capacitive coupling (as shown by the dashed line in the voltage timing diagram of the leakage protection node S in Figure 7). The voltage of the first control node PU remains the operating voltage, keeping the second control transistor M8 of the first control sub-circuit 351 and the fourth control transistor M9 of the second control sub-circuit 352 on, thereby keeping the voltages of the second control node PDA and the second control node PDB at non-operating voltages.

[0126] In the second stage t1, the voltage of the leakage prevention node S is equal to the voltage of the first control node PU. The gate-source voltage Vgs of the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 are less than 0, and the source-drain voltage Vds is equal to 0. This makes the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 turn off more thoroughly, preventing the first control node PU from leaking current through the noise reduction sub-circuit where the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 are located. This keeps the output transistor M5 of the output sub-circuit 320 fully turned on, thereby ensuring the stability of the gate scan signal Gout waveform output by the output sub-circuit 320.

[0127] In the third stage t2, the noise reduction sub-circuit 330 is turned on, transmitting the noise reduction signal from the noise reduction signal terminal to the first control node PU, causing the voltage of the first control node PU to change to a non-operating voltage. The leakage protection electronic circuit 340 discharges to the leakage protection node S.

[0128] For example, the first reset signal RST1 changes to the operating voltage, and the first reset transistor M0 and the third reset transistor M14 are turned on. The third reset transistor M14 discharges to the leakage protection node S, and the first reset transistor M0 and the third reset transistor M14 discharge to the first control node PU, thereby causing the voltages of the leakage protection node S and the first control node PU to change to non-operating voltages. When the first control node PU changes to a non-operating voltage, the second control transistor M8 and the fourth control transistor M9 are turned off. The control signal VDDA causes the voltage of the second control node PDA to change to the operating voltage through the first control transistor M6, and / or the control signal VDDB causes the voltage of the second control node PDB to change to the operating voltage through the third control transistor M7. This turns on the first noise reduction transistor M10, the second noise reduction transistor M11, the third noise reduction transistor M12, and the fourth noise reduction transistor M13, thereby maintaining the voltage of the first control node PU at a non-operating voltage. At the same time, the conduction of the second noise reduction transistor M11 and the fourth noise reduction transistor M13 also maintains the voltage of the leakage protection node S at a non-operating voltage.

[0129] The voltages of the first control node PU and the leakage protection node S are non-operating voltages, making the source-drain voltage Vds of the first noise reduction transistor M10, the first reset transistor M0, the third reset transistor M14, and the third noise reduction transistor M12 zero. The voltage of the leakage protection node S is also non-operating, making the source-drain voltage Vds of the second noise reduction transistor M11, the second reset transistor M4, the first reset transistor M15, and the fourth noise reduction transistor M14 zero. In the third stage t2, the source-drain voltage difference of the transistors related to the noise reduction sub-circuit 330 is zero in the off state, preventing transistor characteristic shift due to prolonged operation and increasing the expected lifespan of the shift register circuit 300. Simultaneously, the shift register circuit 300, including the transistors, does not experience characteristic shift, allowing the transistors to respond to various signals for on or off during operation. This improves the brightness uniformity of the display device 1000, reduces the probability of crosstalk and other risks, and thus improves the display quality of the display device 1000.

[0130] Referring to Figures 12 and 13, Figure 12 is a waveform diagram of the gate scan signal Gout at high frequency according to some embodiments of the gate driving circuit, and Figure 13 is a waveform diagram of the gate scan signal Gout at low frequency according to some embodiments of the gate driving circuit. Figure 12 is a waveform diagram of the gate scan signal Gout of adjacent three-stage shift register circuit 300 in a display device including 1080 rows of pixel units, i.e., the gate driving circuit is connected to 1080 scan lines, and the refresh rate is 144Hz. In Figure 12, the horizontal axis is time t in microseconds, and the vertical axis is voltage U in volts. In Figure 12, the duration of the gate scan signal Gout under the operating voltage is, for example, 6 microseconds. Figure 13 is a waveform diagram of the gate scan signal Gout of adjacent three-stage shift register circuit 300 in a display device including 1080 rows of pixel units, i.e., the gate driving circuit is connected to 1080 scan lines, and the refresh rate is 1Hz. In Figure 13, the horizontal axis is time t in milliseconds, and the vertical axis is voltage U in volts. In Figure 13, the duration of the gate scan signal Gout at the operating voltage is, for example, 0.93 milliseconds.

[0131] As can be seen from Figures 12 and 13, the gate drive circuit 200 using the shift register circuit 300 of this application can output a gate scan signal Gout with good and stable waveform at both high and low frequencies.

[0132] Figure 8 is one of the circuit diagrams of a shift register according to some embodiments. In the shift register circuit 300 shown in Figure 8, the leakage protection node S includes a first leakage protection node S1 and a second leakage protection node S2. The leakage protection electronic circuit 340 of the shift register circuit 300 includes a first leakage protection electronic circuit 341 and a second leakage protection electronic circuit 342. The first leakage protection electronic circuit 341 is coupled to the first leakage protection node S1, and the second leakage protection electronic circuit 342 is coupled to the second leakage protection node S2. The common terminal of the first noise reduction sub-circuit 331 and the first noise reduction sub-circuit 334 is connected to the first leakage protection node S1, and the common terminal of the second noise reduction sub-circuit 332 and the third noise reduction sub-circuit 333 is connected to the second leakage protection node S2.

[0133] The first leakage protection electronic circuit 341 includes a charge / discharge control unit 3411 and a first capacitor C1. The charge / discharge control unit 3411 is coupled to an input control signal terminal IPT, a first input signal terminal CN, a first reset signal terminal RST1, a second input signal terminal CNB, and a first leakage protection node S1. The charge / discharge control unit 3411 is configured to charge the first leakage protection node S1 based on a first input signal CN from the first input signal terminal CN, in response to an input control signal IPT from the input control signal terminal IPT. The charge / discharge control unit 3411 is also configured to discharge the first leakage protection node S1 based on a second input signal CNB from the second input terminal RST1, in response to a first reset signal RST1 from the first reset signal terminal RST1. A first terminal of the first capacitor C1 is coupled to the first leakage protection node S1, and a second terminal is coupled to a third voltage signal terminal VGLC.

[0134] The second leakage protection electronic circuit 342 includes a discharge control unit 3421 and a second capacitor C2. The discharge control unit 3421 is coupled to the second control node PDA, the second control node PDB, the first voltage signal terminal VGLA, and the second leakage protection node S2. The discharge control unit 3421 is configured to discharge the second leakage protection node S2 based on a first voltage signal from the first voltage signal terminal VGLA when the voltage of the second control node PDA and / or the second control node PDB is the operating voltage. The first terminal of the second capacitor C2 is connected to the second leakage protection node S2, and the second terminal is connected to the third voltage signal terminal VGLA.

[0135] For example, the charge / discharge control unit 3411 includes a first transistor M1 and a second transistor M2. The control electrode of the first transistor M1 is coupled to the input control signal terminal IPT, the first electrode is coupled to the first input signal terminal CN, and the second electrode is coupled to the first electrode of the second transistor M2. The control electrode of the second transistor M2 is coupled to the first reset signal terminal RST1, the first electrode is coupled to the first leakage protection node S1, and the second electrode is coupled to the second input signal terminal CNB.

[0136] The discharge control unit 3421 includes a fourth transistor M40 and a fourth transistor M41. The first terminal of the fourth transistor M40 is coupled to the second leakage protection node S2, the second terminal is coupled to the first voltage signal terminal VGLA, and the control terminal is coupled to the second control node PDA. The first terminal of the fourth transistor M41 is coupled to the second leakage protection node S2, the second terminal is coupled to the first voltage signal terminal VGLA, and the control terminal is coupled to the second control node PDB.

[0137] The remaining circuitry of the shift register circuit 300 shown in Figure 8 is basically the same as that shown in Figure 6, so it will not be described again.

[0138] In the shift register circuit 300 shown in Figure 8, the first leakage protection node S1 and the second leakage protection node S2 are separated. The noise reduction sub-circuit 330, which is coupled to the input control signal terminal IPT, the first reset signal terminal RST1 and the second reset signal terminal RST2, is coupled to the first leakage protection node S1. The noise reduction sub-circuit 330, which is coupled to the first control node PU, the second control node PDA and the second control node PDB, is coupled to the second leakage protection node S2. This can prevent the two circuits from interfering with each other and improve the stability and reliability of the shift register circuit 300.

[0139] Furthermore, the discharge control unit 3421 can maintain the second leakage protection node S2 at a non-operating voltage when the voltages of the second control node PDA and / or the second control node PDB are at their operating voltages. This ensures that the source-drain voltage difference between the fourth transistor M4 and the fourth reset transistor M15 is zero, reducing the risk of characteristic shift due to the source-drain voltage difference and improving the stability and lifespan of the shift register circuit 300. The charge / discharge control unit 3411 is compatible with the bidirectional scanning state of the shift register circuit 300, enabling charging and discharging of the first leakage protection node S1 in both forward and reverse scanning states.

[0140] In some feasible embodiments, as shown in Figure 9, which is one of the circuit diagrams of a shift register circuit according to some embodiments, the leakage protection circuit 340 includes a third transistor M3. The control electrode of the third transistor M3 is coupled to the first control node PU, the first stage is coupled to the control electrode dipole of the third transistor M3, and the second stage is coupled to the first leakage protection node S1. The third transistor M3 is connected in a diode configuration, connecting the first control node PU to the first leakage protection node S1, and charging the first leakage protection node S1 through the first control node PU. This reduces the number of transistors in the shift register circuit 300, which is beneficial for reducing the area of ​​the shift register circuit 300, thereby achieving a narrow bezel. The remaining circuit structure and connection relationships of the shift register circuit 300 shown in Figure 9 are basically the same as those of the shift register circuit 300 shown in Figure 6, and therefore will not be described again.

[0141] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register circuit, comprising: The shift register circuit includes: An input sub-circuit, coupled to an input control signal terminal, a first input signal terminal, and a first control node, is configured to, in response to an input control signal from the input control signal terminal, change the voltage of the first control node to an operating voltage based on a first input signal from the first input signal terminal. The output sub-circuit, coupled to the first control node, the clock signal terminal and the scan signal terminal, is configured to, under the control of the first control node, cause the scan signal terminal to output a gate scan signal based on the clock signal from the clock signal terminal; A noise reduction sub-circuit, coupled to the first control node and the noise reduction signal terminal, is configured to change the voltage of the first control node to a non-operating voltage based on the noise reduction signal from the noise reduction signal terminal; the noise reduction sub-circuit includes two transistors connected in series, and the common terminal of the two transistors connected in series is connected to the leakage protection node. A leakage protection electronic circuit, coupled to the leakage protection node, is configured to charge the leakage protection node when the voltage of the first control node is the operating voltage, and to discharge the leakage protection node when the voltage of the first control node is the non-operating voltage.

2. The shift register circuit of claim 1, wherein, The shift register circuit further includes a control sub-circuit coupled to a control signal terminal, a first voltage signal terminal, a first control node, and a second control node; the control sub-circuit is configured to switch the voltage of the second control node between a working voltage and a non-working voltage based on the voltage of the first control node, a first voltage signal from the first voltage signal terminal, and a control signal from the control signal terminal. The noise reduction sub-circuit includes a first noise reduction sub-circuit, wherein the first voltage signal terminal is coupled to the first noise reduction sub-circuit as the noise reduction signal terminal, and the first noise reduction sub-circuit is also coupled to the second control node; the first noise reduction sub-circuit is configured to, when the voltage of the second control node is the operating voltage, make the voltage of the first control node a non-operating voltage based on the first voltage signal from the first voltage signal terminal. The leakage protection node includes a first leakage protection node, and the common terminal of the two transistors in the first noise reduction sub-circuit is connected to the first leakage protection node; the leakage protection electronic circuit includes a first leakage protection electronic circuit, and the first leakage protection electronic circuit is coupled to the first leakage protection node.

3. The shift register circuit of claim 2, wherein, The first leakage protection electronic circuit includes: A first capacitor, wherein a first end of the first capacitor is coupled to the first leakage protection node, and a second end of the first capacitor is coupled to a third voltage signal terminal or the scanning signal terminal.

4. The shift register circuit of claim 3, wherein, The input sub-circuit includes two transistors connected in series, and the first leakage protection node is also coupled to the common terminal of the two transistors connected in series in the input sub-circuit.

5. The shift register circuit according to claim 3 or 4, wherein The noise reduction sub-circuit further includes a second noise reduction sub-circuit, with the second input signal terminal coupled to the second noise reduction sub-circuit as the noise reduction signal terminal, and the second noise reduction sub-circuit also coupled to the first reset signal terminal; the second noise reduction sub-circuit is configured to, in response to a first reset signal from the first reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a second input signal from the second input signal terminal; The common terminal of the two transistors in the second noise reduction sub-circuit is connected to the first leakage protection node.

6. The shift register circuit of claim 5, wherein, The noise reduction sub-circuit further includes a third noise reduction sub-circuit, wherein the first voltage signal terminal is coupled to the third noise reduction sub-circuit as the noise reduction signal terminal, and the third noise reduction sub-circuit is also coupled to the second reset signal terminal; the third noise reduction sub-circuit is configured to, in response to a second reset signal from the second reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a first input signal from the first input signal terminal. The common terminal of the two transistors in the third noise reduction sub-circuit is connected to the first leakage protection node.

7. The shift register circuit of claim 3, wherein, The first leakage protection electronic circuit also includes: The charging and discharging control unit is coupled to the input control signal terminal, the first input signal terminal, the first reset signal terminal, the second input signal terminal, and the first leakage protection node; The charge / discharge control unit is configured to, in response to an input control signal from the input control signal terminal, charge the first leakage protection node based on a first input signal from the first input signal terminal; and, in response to a first reset signal from the first reset signal terminal, discharge the first leakage protection node based on a second input signal from the second input signal terminal.

8. The shift register circuit of claim 7, wherein, The charging and discharging control unit includes: A first transistor, wherein the control electrode of the first transistor is coupled to the input control signal terminal, the first electrode of the first transistor is coupled to the first input signal terminal, and the second electrode of the first transistor is coupled to the first electrode of the second transistor; The second transistor has its control electrode coupled to the first reset signal terminal and its second electrode coupled to the second input signal terminal. The second terminal of the first transistor and the first terminal of the second transistor are both coupled to the first leakage protection node.

9. The shift register circuit of claim 2, wherein, The first leakage protection electronic circuit includes: The third transistor has its control electrode coupled to the first control node, its first electrode coupled to the control electrode, and its second electrode coupled to the first leakage protection node.

10. The shift register circuit according to any one of claims 7 to 9, wherein The noise reduction sub-circuit further includes a second noise reduction sub-circuit, with the second input signal terminal coupled to the second noise reduction sub-circuit as the noise reduction signal terminal, and the second noise reduction sub-circuit also coupled to the first reset signal terminal; the second noise reduction sub-circuit is configured to, in response to a first reset signal from the first reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a second input signal from the second input signal terminal; The leakage protection node also includes a second leakage protection node, wherein the common terminal of the two transistors in the second noise reduction sub-circuit is connected to the second leakage protection node; The leakage prevention electronic circuit also includes a second leakage prevention electronic circuit, which is coupled to the second leakage prevention node.

11. The shift register circuit of claim 10, wherein, The second leakage protection electronic circuit includes: The second capacitor has a first end coupled to the second leakage protection node, and a second end coupled to the third voltage signal terminal or the scanning signal terminal.

12. The shift register circuit of claim 11, wherein, The input sub-circuit includes two transistors connected in series, and the second leakage protection node is also coupled to the common terminal of the two transistors connected in series in the input sub-circuit.

13. The shift register circuit according to claim 11 or 12, wherein, The second leakage protection electronic circuit also includes: The discharge control unit is coupled to the second control node, the first voltage signal terminal and the second leakage protection node; The discharge control unit is configured to discharge the second leakage protection node based on a first voltage signal from the first voltage signal terminal when the voltage of the second control node is the operating voltage.

14. The shift register circuit of claim 13, wherein, The discharge control unit includes: The fourth transistor has its control electrode coupled to the second control node, its first electrode coupled to the second leakage protection node, and its second electrode coupled to the first voltage signal terminal.

15. The shift register circuit according to any one of claims 10 to 14, wherein The noise reduction sub-circuit further includes a third noise reduction sub-circuit, wherein the first voltage signal terminal is coupled to the third noise reduction sub-circuit as the noise reduction signal terminal, and the third noise reduction sub-circuit is also coupled to the second reset signal terminal; the third noise reduction sub-circuit is configured to, in response to a second reset signal from the second reset signal terminal, set the voltage of the first control node to a non-operating voltage based on a first input signal from the first input signal terminal. The common terminal of the two transistors in the third noise reduction sub-circuit is connected to the second leakage protection node.

16. The shift register circuit according to any one of claims 2 to 15, wherein The shift register circuit includes at least two control sub-circuits; The at least two control sub-circuits are respectively coupled to at least two control signal terminals, and the at least two control signal terminals are configured to sequentially input control signals for controlling the corresponding control sub-circuit to turn on; the at least two control sub-circuits are respectively coupled to the second control nodes of at least two first noise reduction sub-circuits; the common terminal of the at least two first noise reduction sub-circuits is coupled to the first leakage protection node.

17. The shift register circuit of claim 13 or 14, wherein, The shift register circuit includes at least two of the control sub-circuits; The at least two control sub-circuits are respectively coupled to at least two control signal terminals, and the at least two control signal terminals are configured to sequentially input control signals for controlling the corresponding control sub-circuit to turn on; the at least two control sub-circuits are respectively coupled to one of the second control nodes of at least two first sub-noise reduction circuits; The common terminals of the at least two first noise reduction sub-circuits are all coupled to the first leakage protection node; One of the control sub-circuits is coupled to one of the control signal terminals, and at least two of the control signal terminals are configured to sequentially input the control signals used to control the control sub-circuit to turn on; At least two of the second control nodes of the control sub-circuits are coupled to the first leakage protection node; The leakage prevention electronic circuit includes at least two discharge control units, one of which is coupled to the second control node of one of the control sub-circuits.

18. The shift register circuit according to any one of claims 5 to 8, 10 to 16, wherein, The first input signal input to the first input signal terminal and the second input signal input to the second input signal terminal are both constant voltage signals and are inverse signals of each other.

19. The shift register circuit according to any one of claims 3 to 8, 11 to 14, wherein, The third voltage signal input at the third voltage signal terminal is a constant voltage signal.

20. A gate drive circuit, wherein, The gate drive circuit includes a plurality of cascaded shift register circuits, wherein the shift register circuit is the shift register circuit as described in any one of claims 1 to 19.

21. A display device, wherein, The display device includes: The gate driving circuit as described in claim 20; Multiple scan lines, wherein each shift register circuit in the gate drive circuit is connected to at least one of the scan lines.

22. A control method of a shift register circuit, applied to the shift register circuit according to any one of claims 1 to 19; wherein, The control method includes multiple row scanning periods, each row scanning period including a first stage, a second stage and a third stage; In the first stage, the input sub-circuit is turned on in response to the input control signal from the input control signal terminal, and transmits the first input signal from the first input signal terminal to the first control node, so that the voltage of the first control node changes to the working voltage; the leakage protection electronic circuit charges the leakage protection node, so that the voltage of the first control node maintains the working voltage. In the second stage, the output sub-circuit is turned on under the control of the first control node, transmitting the clock signal from the clock signal terminal to the scan signal terminal, so that the scan signal terminal outputs the gate scan signal; the leakage protection electronic circuit continues to maintain the voltage of the first control node at the operating voltage; In the third stage, the noise reduction sub-circuit is turned on, transmitting the noise reduction signal from the noise reduction signal terminal to the first control node, causing the voltage of the first control node to change to a non-operating voltage; the leakage protection electronic circuit discharges the leakage protection node.

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