Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a driving circuit (100), the driving circuit (100) comprising N stages of cascaded shift registers (110), where N≥2. Each shift register (110) comprises a first control portion (10) and a second control portion (20). Each first control portion (10) is configured to control a first output signal, wherein a first output signal of an i-th stage shift register (110) is a first input signal of a j-th stage shift register (110); and each first control portion (10) comprises a first node (N1), wherein the potential of the first node (N1) is synchronized with a first output signal. Each second control portion (20) is configured to at least receive a potential signal of a first node (N1) and a frequency control signal, and to control a second output signal, wherein the transition of each first output signal from an invalid level to a valid level is defined as a first voltage edge, and when the first voltage edge of the first output signal overlaps with a valid pulse of the frequency control signal, the second output signal is a valid pulse.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202411748836.X, filed with the Chinese Patent Office on November 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, such as a display panel and a display device. Background Technology

[0003] With the continuous development of display technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work.

[0004] The main component of electronic devices that enables display functions is the display panel. Current display panels already possess the ability to segment and adjust refresh rates, meaning different areas of the display can have different refresh rates. This reduces panel power consumption by lowering the refresh rate of certain areas. However, the shift register circuit in display panels with this segmented refresh rate adjustment function uses both N-type and P-type transistors. On the one hand, the separate fabrication of N-type and P-type transistors increases the fabrication difficulty and number of processes, and also occupies a larger bezel area, which is detrimental to the narrow bezel design of the display panel. Summary of the Invention

[0005] This application provides a display panel and display device to achieve partitioned refresh at any position of the display panel, save display power consumption, ensure normal display of the screen, and further compress the bezel space.

[0006] In a first aspect, embodiments of this application provide a display panel, including:

[0007] The driving circuit includes N cascaded shift registers, where N ≥ 2;

[0008] The shift register includes:

[0009] A first control unit and a second control unit, wherein the first control unit and the second control unit are electrically connected;

[0010] The first control unit is configured to control the first output signal, where the first output signal of the i-th stage shift register is the first input signal of the j-th stage shift register, 1≤i≤N, 2≤j≤N; the first control unit includes a first node, and the potential of the first node is synchronized with the first output signal.

[0011] The second control unit is configured to receive at least a frequency control signal and a potential signal from the first node, and to control the second output signal;

[0012] The process of the first output signal transitioning from an invalid level to an effective level is the first voltage edge;

[0013] When the first voltage edge of the first output signal overlaps with the effective pulse of the frequency control signal, the second output signal is an effective pulse.

[0014] Secondly, embodiments of this application also provide a display device, including a display panel as described in any of the first aspects. Attached Figure Description

[0015] Figure 1 is a schematic diagram of the structure of a shift register provided in an embodiment of this application;

[0016] Figure 2 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0017] Figure 3 is a schematic diagram of the driving circuit in the display panel shown in Figure 2;

[0018] Figure 4 is a schematic diagram of the shift register in the driving circuit shown in Figure 3;

[0019] Figure 5 is a timing diagram of a multi-stage shift register in the driving circuit shown in Figure 3.

[0020] Figure 6 is another driving timing diagram of the multi-stage shift register in the driving circuit shown in Figure 3;

[0021] Figure 7 is a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0022] Figure 8 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0023] Figure 9 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0024] Figure 10 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0025] Figure 11 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0026] Figure 12 is a schematic diagram of another pixel circuit provided in an embodiment of this application;

[0027] Figure 13 is a driving timing diagram of a display panel provided in an embodiment of this application;

[0028] Figure 14 is a driving timing diagram of another display panel provided in an embodiment of this application;

[0029] Figure 15 is a driving timing diagram of a pixel circuit provided in an embodiment of this application;

[0030] Figure 16 is a partial structural schematic diagram of a display panel provided in an embodiment of this application;

[0031] Figure 17 is a driving timing diagram of the two shift registers shown in Figure 16;

[0032] Figure 18 is another driving timing diagram for the two shift registers shown in Figure 16;

[0033] Figure 19 is a schematic diagram of the circuit structure of a shift register provided in an embodiment of this application;

[0034] Figure 20 is a timing diagram of one type of drive for the second control unit in the shift register shown in Figure 19;

[0035] Figure 21 is another driving timing diagram of the second control unit in the shift register shown in Figure 19;

[0036] Figure 22 is a schematic diagram of the circuit structure of another shift register provided in an embodiment of this application;

[0037] Figure 23 is a timing diagram of one type of drive for the second control unit in the shift register shown in Figure 22;

[0038] Figure 24 is another driving timing diagram of the second control unit in the shift register shown in Figure 22;

[0039] Figure 25 is a schematic diagram of the circuit structure of another shift register provided in an embodiment of this application;

[0040] Figure 26 is a timing diagram of one type of drive for the second control unit in the shift register shown in Figure 25;

[0041] Figure 27 is a timing diagram of the drive of the first control unit in a shift register provided in an embodiment of this application;

[0042] Figure 28 is a schematic diagram of the circuit structure of another shift register provided in an embodiment of this application;

[0043] Figure 29 is another driving timing diagram of the multi-stage shift register in the driving circuit shown in Figure 3;

[0044] Figure 30 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0045] The present application will now be described in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit its scope. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0046] In related technologies, a display panel includes a display area and a non-display area. The non-display area is equipped with a driving circuit, and the display area includes multiple pixel circuits arranged in an array and light-emitting elements electrically connected to each pixel circuit. The driving circuit sequentially provides driving signals to the multiple rows of pixel circuits through scan signal lines. The pixel circuits control the corresponding electrically connected light-emitting elements to light up according to the driving signals. In a display frame, the light-emitting elements in the display area are sequentially controlled to light up, and specific pixels can be achieved through the color matching of adjacent light-emitting elements of different colors, thereby achieving the display of the entire image on a macroscopic level.

[0047] Figure 1 is a schematic diagram of a shift register provided in an embodiment of this application. As shown in Figure 1, the driving circuit in the non-display area is configured with cascaded multi-stage shift register circuits 10'. Each stage of the shift register circuit 10' is also equipped with a gating circuit 20'. The output of each gating circuit 20' is connected to at least one row of pixel circuits via at least one scan signal line. Figure 1 can be understood as a schematic diagram of the circuit structure of any stage of the shift register circuit 10' and its corresponding gating circuit 20'. The shift register circuit 10' is responsible for outputting different levels of scan pulse signals SN_NEXT. The gating circuit 20' is connected to the output of the shift register circuit 10', configured to receive the scan pulse signal SN_NEXT, and selectively output the scan pulse signal SN_NEXT under the control of the frequency control signal SN_CTRL. Therefore, the output frequency of the scanning pulse signal SN_NEXT can be controlled by the frequency control signal SN_CTRL to change the refresh frequency of the corresponding connected pixel row. This allows different zones of the display panel to have different refresh frequencies, realizing the zone frequency function of the display panel and adapting to the display power consumption requirements of different display scenarios.

[0048] Referring again to Figure 1, which is only a schematic diagram of one structure of the shift register circuit 10' and the corresponding gating circuit 20', it can be seen that the circuit structure of the gating circuit 20' contains both N-type and P-type transistors. On the one hand, when fabricating the gating circuit 20' in the display panel, it is necessary to separately fabricate the indium gallium zinc oxide (IGZO) semiconductor layer corresponding to the N-type transistor and the low-temperature polycrystalline silicon (LTPS) semiconductor layer corresponding to the P-type transistor, which greatly increases the difficulty and number of steps in the film fabrication process. On the other hand, the circuit structure of the gating circuit 20' is located in the non-display area. The IGZO semiconductor layer has a low mobility, and the size of the N-type transistor needs to be relatively larger. For example, the size of the N-type transistor (for example, the third transistor M3) near the output terminal SN_OUT of the gating circuit 20' needs to be relatively large, which places high demands on the bezel space and is not conducive to the narrow bezel design of the display panel. On the other hand, the instability of the IGZO semiconductor layer and the degradation of the N-type transistor can lead to a weakening of the output capability and even cause the entire circuit to fail.

[0049] This application provides a display panel. The display panel includes:

[0050] The driving circuit includes N cascaded shift registers, where N ≥ 2;

[0051] Shift registers include:

[0052] A first control unit and a second control unit, the first control unit and the second control unit being electrically connected;

[0053] The first control unit is configured to control the first output signal, and the first output signal of the i-th stage shift register is the first input signal of the j-th stage shift register, 1≤i≤N, 2≤j≤N; the first control unit includes a first node, and the potential of the first node is synchronized with the first output signal;

[0054] The second control unit receives at least the frequency control signal and the potential signal of the first node, and controls the second output signal;

[0055] The process of the first output signal transitioning from an invalid level to an effective level is the first voltage edge;

[0056] When the first voltage edge of the first output signal overlaps with the effective pulse of the frequency control signal, the second output signal is an effective pulse.

[0057] In the technical solution of this application embodiment, the display panel sets a first control unit and a second control unit in the shift register. The first control unit controls the first output signal and makes the first output signal of the i-th stage shift register the first input signal of the j-th stage shift register, which can realize the cascading of at least two stages of the first control unit. At the same time, the second control unit receives at least the frequency control signal and the potential signal of the first node, and controls the second output signal to output an effective pulse when the first voltage edge of the first output signal overlaps with the effective pulse of the frequency control signal. In this way, the effective pulse and invalid pulse of the second output signal can be changed through the frequency control signal, thereby controlling the pixel circuit and realizing the adjustment of the refresh rate of different areas of the display panel. This allows the display panel to apply different refresh rates in different areas. The high refresh rate signal cannot be output normally in the low refresh rate area, thereby realizing local frequency reduction, saving power consumption. In addition, the position of the display panel that needs to be refreshed in zones can be freely defined, and multiple different frequencies can be displayed at the same time.

[0058] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0059] Figure 2 is a schematic diagram of a display panel provided in an embodiment of this application. Figure 3 is a schematic diagram of the driving circuit in the display panel shown in Figure 2. Figure 4 is a schematic diagram of the shift register in the driving circuit shown in Figure 3. Figure 5 is a driving timing diagram of a multi-stage shift register in the driving circuit shown in Figure 3. As shown in Figures 2-5, the display panel includes a driving circuit 100, which includes N-stage shift registers 110 cascaded together, where N ≥ 2. The shift registers 110 include a first control unit 10 and a second control unit 20, which are electrically connected. The first control unit 10 is configured to control the first output signal SN_NEXT1, and the i-th stage shift register 110... The first output signal SN_NEXT1 is the first input signal SN_IN1 of the j-th stage shift register 110, where 1≤i≤N and 2≤j≤N; the first control unit 10 includes a first node N1, the potential of the first node N1 being synchronized with the first output signal SN_NEXT1; the second control unit 20 receives at least the frequency control signal SN_CTRL and the potential signal of the first node N1, and controls the second output signal SN_OUT; the process of the first output signal SN_NEXT1 transitioning from an invalid level to an effective level is the first voltage edge; when the first voltage edge of the first output signal SN_NEXT1 overlaps with the effective pulse of the frequency control signal SN_CTRL, the second output signal SN_OUT is an effective pulse.

[0060] As exemplarily shown in Figures 2 and 3, the driving circuit 100 of the display panel is provided with at least two stages of shift registers 110. These at least two stages of shift registers 110 are cascaded, meaning that the output signal of one stage of shift register 110 is the input signal of the next stage of shift register 110. For example, in Figure 3, the output signal of an adjacent upper-level shift register 110 is the input signal of the next-level shift register 110. In this embodiment, the shift register 110 is provided with a first control unit 10 and a second control unit 20 electrically connected. The first control units 10 in the multi-stage shift registers 110 actually form the aforementioned cascaded relationship; that is, the first output signal SN_NEXT1 output by the first control unit 10 in one stage of shift register 110 is the input signal of the first control unit 10 in the next stage of shift register 110.

[0061] The first control unit 10 includes a first node N1. The potential of the first node N1 is synchronized with the first output signal SN_NEXT1. Thus, the potential change of the first output signal SN_NEXT1 can be replaced by the potential change of the first node N1. The output terminal of the first output signal SN_NEXT1 output by the first control unit 10 can be electrically connected to the second control unit 20, or the first node N1 in the first control unit 10 can also be electrically connected to the second control unit 20. In this embodiment, the node in the first control unit 10 is essentially brought out as the first node N1. The specific location and connection relationship of the first node N1 in the first control unit 10 will be described in detail later and will not be explained here. For the second control unit 20 in each stage shift register 110, that is, based on the first output signal SN_NEXT1 provided by the first control unit 10 as the control signal of the second control unit 20, the selection is simultaneously controlled by the additional input frequency control signal SN_CTRL, thereby controlling whether the first output signal SN_NEXT1 provided by the first control unit 10 is output, forming the second output signal SN_OUT.

[0062] A valid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned on, connected, or working. An invalid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned off, cut off, or not working. As shown in Figure 5, the valid pulses of the first output signal SN_NEXT1, the second output signal SN_OUT, and the frequency control signal SN_CTRL are all high-level, and the invalid pulses are all low-level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. Taking the first output signal SN_NEXT1_j of the j-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting a valid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the valid pulse (high level) of the frequency control signal SN_CTRL, thus forming the second output signal SN_OUT (high level). In this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are used to control the output of a second output signal SN_OUT (high level) by ensuring that the time period corresponding to the first voltage edge (rising edge) of the first output signal SN_NEXT1 is completely within the effective pulse (high level) time period of the frequency control signal SN_CTRL. When the first voltage edge (rising edge) of the first output signal SN_NEXT1 is completely covered by the effective pulse (high level) of the frequency control signal SN_CTRL, the second control unit 20 will output the effective pulse (high level) of the first output signal SN_NEXT1. Therefore, this embodiment, through the second control unit 20 and the frequency control signal SN_CTRL, can at least ensure that when the time period corresponding to the first voltage edge of the first output signal SN_NEXT1 is within the effective pulse time period of the frequency control signal SN_CTRL, the second output signal SN_OUT outputs a complete effective pulse, so that the pixel circuit 200 can always receive a normal driving signal, ensuring the normal operation of the pixel circuit 200 and displaying a normal image.

[0063] Furthermore, taking the first output signal SN_NEXT1_h of the h-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting a valid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the valid pulse (high level) of the frequency control signal SN_CTRL, forming the second output signal SN_OUT (high level). After the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, when the first output signal SN_NEXT1 is a valid pulse (high level), it will overlap with the voltage transition edge of the frequency control signal SN_CTRL from a valid pulse (high level) to an invalid pulse (low level). At this time, the second output signal SN_OUT still maintains a valid pulse (high level) output, and the voltage transition edge of the frequency control signal SN_CTRL will not cut off the second output signal SN_OUT.

[0064] Optionally, continuing to refer to Figure 5, when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the second output signal SN_OUT is an invalid pulse.

[0065] Taking the first output signal SN_NEXT1_i of the i-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the invalid pulse (low level) of the frequency control signal SN_CTRL, forming the second output signal SN_OUT (low level). After the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, when the first output signal SN_NEXT1 is a valid pulse (high level), it will overlap with the voltage transition edge of the frequency control signal SN_CTRL from invalid pulse (low level) to valid pulse (high level). At this time, the second output signal SN_OUT still maintains the output of invalid pulse (low level), and the voltage transition edge of the frequency control signal SN_CTRL will not cut off the second output signal SN_OUT. In this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are used to control the output of invalid pulses, forming the second output signal SN_OUT (low level), when the time period corresponding to the first voltage edge (rising edge) of the first output signal SN_NEXT1 is completely within the invalid pulse (low level) time period of the frequency control signal SN_CTRL. When the first voltage edge (rising edge) of the first output signal SN_NEXT1 is not completely covered by the valid pulse (high level) of the frequency control signal SN_CTRL, the second control unit 20 will not output the valid pulse (high level) of the first output signal SN_NEXT1. Therefore, in this embodiment, the second control unit 20 and the frequency control signal SN_CTRL can at least ensure that when the time period corresponding to the first voltage edge of the first output signal SN_NEXT1 is within the invalid pulse time period of the frequency control signal SN_CTRL, the second output signal SN_OUT outputs invalid pulses, so that the corresponding pixel circuit 200 cannot receive the normal driving signal, and different refresh frequencies can be achieved for different areas, that is, the display panel can perform segmented frequency display.

[0066] Optionally, referring to Figure 5, when the first output signal SN_NEXT1 is an invalid pulse, the second output signal SN_OUT is also an invalid pulse.

[0067] Taking the first output signal SN_NEXT1_k of the k-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse when the first output signal SN_NEXT1 is an invalid pulse (low level), that is, when the first output signal SN_NEXT1 has no first voltage edge, to form the second output signal SN_OUT (low level). When the first output signal SN_NEXT1 is an invalid pulse, there is no need to determine whether it overlaps with the valid or invalid pulse of the frequency control signal SN_CTRL, and the second output signal SN_OUT is quickly determined to be an invalid pulse.

[0068] In this embodiment, no special requirements or specific limitations are made on the effective and invalid pulses of the first output signal SN_NEXT1, the second output signal SN_OUT, and the frequency control signal SN_CTRL. In addition, for example, Figure 6 is another driving timing diagram of the multi-stage shift register in the driving circuit shown in Figure 3. The effective pulse can be understood as the implementation of controlling the corresponding connected units, circuits, etc. to be turned on, connected, and working. The invalid pulse can be understood as the implementation of controlling the corresponding connected units, circuits, etc. to be turned off, cut off, and not working. As shown in Figure 6, the effective pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both high level, and the invalid pulses are both low level. The effective pulse of the frequency control signal SN_CTRL is low level, and the invalid pulse is high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. Taking the first output signal SN_NEXT1_o of the 0th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting a valid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the valid pulse (low level) of the frequency control signal SN_CTRL, forming the second output signal SN_OUT (high level). After the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, when the first output signal SN_NEXT1 is a valid pulse (high level), it will overlap with the voltage transition edge of the frequency control signal SN_CTRL from a valid pulse (low level) to an invalid pulse (high level). At this time, the second output signal SN_OUT still maintains a valid pulse (high level) output, and the voltage transition edge of the frequency control signal SN_CTRL will not cut off the second output signal SN_OUT.

[0069] Taking the first output signal SN_NEXT1_p of the p-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the invalid pulse (high level) of the frequency control signal SN_CTRL, thus forming the second output signal SN_OUT (low level). Taking the first output signal SN_NEXT1_q of the q-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse when the first voltage edge (rising edge) of the first output signal SN_NEXT1 overlaps with the invalid pulse (high level) of the frequency control signal SN_CTRL, thus forming the second output signal SN_OUT (low level). After the first voltage edge (rising edge) of the first output signal SN_NEXT1, that is, when the first output signal SN_NEXT1 is a valid pulse (high level), it will overlap with the voltage transition edge of the frequency control signal SN_CTRL from an invalid pulse (high level) to a valid pulse (low level). At this time, the second output signal SN_OUT will still maintain an invalid pulse (low level) output, and the voltage transition edge of the frequency control signal SN_CTRL will not cut off the second output signal SN_OUT.

[0070] Taking the first output signal SN_NEXT1_r of the r-th stage shift register 110 as an example, in this embodiment of the application, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse when the first output signal SN_NEXT1 is an invalid pulse (low level), that is, when the first output signal SN_NEXT1 has no first voltage edge, so as to form the second output signal SN_OUT (low level). In summary, the first output signal SN_NEXT1 of the shift register 110 can always maintain a high refresh rate. When the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL, the second output signal SN_OUT is the same as the first output signal SN_NEXT1, and the second output signal SN_OUT is output to the corresponding pixel circuit 200. When the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, or when the first output signal SN_NEXT1 is an invalid pulse, the second output signal SN_OUT is an invalid pulse, thereby realizing a local low refresh rate and realizing the partitioned refresh design of the display panel.

[0071] Optionally, referring to Figures 5 and 6, the pulse change frequency of the first output signal SN_NEXT1 is F1, and the pulse change frequency of the second output signal SN_OUT is F2; ​​where F1 ≥ F2.

[0072] The second control unit 20 and the frequency control signal SN_CTRL are responsible for limiting the output of some valid pulses based on the first output signal SN_NEXT1 output by the first control unit 10. Therefore, it can be seen that within the same time period, the number of valid pulses of the second output signal SN_OUT output by the second control unit 20 will not exceed the number of valid pulses in the first output signal SN_NEXT1. That is, within the same time period, the pulse change frequency F2 of the second output signal SN_OUT will not exceed the pulse change frequency F1 of the first output signal SN_NEXT1, i.e., F2≤F1.

[0073] Referring to Figure 5, when the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL, or when the first output signal SN_NEXT1 is an invalid pulse, F1 = F2; when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, F1 > F2.

[0074] For the first output signal SN_NEXT1_j or the first output signal SN_NEXT1_h of the j-th stage shift register 110, when its first voltage falls within the effective pulse time period of the frequency control signal SN_CTRL along the corresponding time period, the second control unit 20 outputs effective pulses. The number of effective pulses is the same as the number of effective pulses of the first output signal SN_NEXT1. Therefore, the pulse change frequencies of the second output signal SN_OUT and the first output signal SN_NEXT1 are consistent, and F2 = F1. Alternatively, for the first output signal SN_NEXT1_k of the k-th stage shift register 110, when the first output signal SN_NEXT1 is an invalid pulse, regardless of whether it falls within the effective pulse time period of the frequency control signal SN_CTRL, the second control unit 20 outputs invalid pulses. The number of effective pulses is the same as the number of effective pulses of the first output signal SN_NEXT1. Therefore, the pulse change frequencies of the second output signal SN_OUT and the first output signal SN_NEXT1 are consistent, and F2 = F1. For the first output signal SN_NEXT1_i of the i-th stage shift register 110, when its first voltage edge is within the invalid pulse time period of the frequency control signal SN_CTRL, the second control unit 20 outputs invalid pulses. The number of valid pulses is less than the number of valid pulses of the first output signal SN_NEXT1. Therefore, the pulse change frequency of the second output signal SN_OUT decreases, and F2 < F1.

[0075] Referring again to Figures 5 and 6, in one embodiment, during at least a portion of the time the display panel operates, when the first output signal SN_NEXT1 is a valid pulse, the second output signal SN_OUT is also a valid pulse. Furthermore, in another embodiment, during at least a portion of the time the display panel operates, when the first output signal SN_NEXT1 is a valid pulse, the second output signal SN_OUT is an invalid pulse.

[0076] During at least a portion of the display panel's operation, both the first output signal SN_NEXT1 and the second output signal SN_OUT are valid pulses. This indicates that during this period, the first voltage of the first output signal SN_NEXT1 falls within the valid pulse period of the frequency control signal SN_CTRL. Therefore, the second output signal SN_OUT can provide valid pulses to the display panel, thereby driving the corresponding pixel circuit 200 in the display panel to operate normally. Conversely, during at least a portion of the display panel's operation, the first output signal SN_NEXT1 is a valid pulse while the second output signal SN_OUT is an invalid pulse. This indicates that during this period, the first voltage of the first output signal SN_NEXT1 falls within the invalid pulse period of the frequency control signal SN_CTRL. In this case, the second output signal SN_OUT provides invalid pulses to the display panel, thereby driving the corresponding pixel circuit 200 in the display panel to stop operating. Furthermore, during at least a portion of the display panel's operating time, the first output signal SN_NEXT1 is an invalid pulse, and the corresponding second output signal SN_OUT is always an invalid pulse. This means that during this period, regardless of the relationship between the effective pulse time periods of the first output signal SN_NEXT1 and the frequency control signal SN_CTRL, the second output signal SN_OUT provides invalid pulses to the display panel, thereby driving the corresponding pixel circuit 200 in the display panel to stop working. In this way, the driving frequency of the display panel can be controlled, achieving a zoned refresh effect and improving display quality or driving power consumption.

[0077] Optionally, Figures 7-12 are schematic diagrams of the structures of six pixel circuits provided in the embodiments of this application. Referring to Figures 2 and 7-12, the display panel further includes a pixel circuit 200. The second output signal SN_OUT of the driving circuit 100 is a control signal of the preset module of the pixel circuit 200. When the second output signal SN_OUT is a valid pulse, the preset module is turned on; when the second output signal SN_OUT is an invalid pulse, the preset module is turned off.

[0078] The following describes the process of driving the preset module in the driving circuit 100 with reference to the pixel circuit 200 shown in Figures 7-12. As shown in Figures 7-12, the pixel circuit 200 may include a data writing module 210, a driving module 220, and a compensation module 230; the driving module 220 includes a driving transistor T2, which is configured to provide driving current to the light-emitting element 300 of the display panel 100; the data writing module 210 is connected to the first terminal (i.e., node N02) of the driving transistor T2 and is configured to provide data signals to the driving transistor T2; the compensation module 230 is connected between the gate (i.e., node N01) and the second terminal (i.e., node N03) of the driving transistor T2 and is configured to compensate for the threshold voltage of the driving transistor T2.

[0079] In addition, the pixel circuit 200 may also include a reset module 250, configured to provide a reset signal Vref to the gate of the driving transistor T2; an initialization module 260, configured to provide an initialization signal Vini to the light-emitting element 300; and a light-emitting control module 270, configured to selectively allow the light-emitting element 300 to enter the light-emitting stage. Optionally, the light-emitting control module 270 includes a first light-emitting control module 271 and a second light-emitting control module 272. The first light-emitting control module 271 is connected between the first power supply signal terminal and one pole of the driving transistor T2, and the second light-emitting control module 272 is connected between the other pole of the driving transistor T2 and the light-emitting element 300.

[0080] The control terminal of the data writing module 210 receives a first scan signal S1, which controls the opening and closing of the data writing module 210; the control terminal of the compensation module 230 receives a second scan signal S2, which controls the opening and closing of the compensation module 230; the control terminal of the reset module 250 receives a third scan signal S3, which controls the opening and closing of the reset module 250; the control terminal of the initialization module 260 receives a fourth scan signal S4, which controls the opening and closing of the initialization module 260; and the control terminal of the light emission control module 270 receives a light emission control signal EM, which controls the opening and closing of the light emission control module 270.

[0081] The data writing module 210 includes a data writing transistor T1, and a first scan signal S1 controls the turning on and off of the data writing transistor T1; the compensation module 230 includes a compensation transistor T3, and a second scan signal S2 controls the turning on and off of the compensation transistor T3; the reset module 250 includes a reset transistor T5, and a third scan signal S3 controls the turning on and off of the reset transistor T5; the initialization module 260 includes an initialization transistor T6, and a fourth scan signal S4 controls the turning on and off of the initialization transistor T6; the first light-emitting control module 271 includes a first light-emitting control transistor T7, and the second light-emitting control module 272 includes a second light-emitting control transistor T8, and a light-emitting control signal EM controls the turning on and off of the first light-emitting control transistor T7 and the second light-emitting control transistor T8.

[0082] As shown in Figures 9-12, the pixel circuit 200 may further include a bias adjustment module 240, configured to provide a bias adjustment signal to the driving transistor T2. Optionally, as shown in Figures 9 and 11, the bias adjustment module 240 is connected to the first terminal (i.e., node N02) of the driving transistor T2; as shown in Figures 10 and 12, the bias adjustment module 240 is connected to the second terminal (i.e., node N03) of the driving transistor T2. Optionally, the control terminal of the bias adjustment module 240 receives a bias adjustment control signal SV, which controls the switching on and off of the bias adjustment module 240; the bias adjustment module 240 includes a bias adjustment transistor T4, which is switched on and off by the bias adjustment control signal SV.

[0083] Additionally, in the pixel circuit 200 shown in Figures 7, 9, and 11, the driving transistor T2 is a P-type transistor. The pixel circuit 200 also includes a storage capacitor C1, with its first terminal connected to a first power supply signal terminal and its second terminal connected to the gate of the driving transistor T2, configured to store the signal transmitted to the gate of the driving transistor T2. In the pixel circuit 200 shown in Figures 8, 10, and 12, the driving transistor T2 is an N-type transistor. The pixel circuit 200 also includes a storage capacitor C1, with its first terminal connected to the light-emitting element 300 and its second terminal connected to the gate of the driving transistor T2, configured to store the signal transmitted to the gate of the driving transistor T2.

[0084] In this embodiment, the pixel unit receives power signals PVDD and PVEE. The potential difference between PVDD and PVEE, along with the data signal Vdata written to the gate of the driving transistor T2, controls the driving current, thereby driving the light-emitting element 300 to emit light. The PVDD signal can be, for example, a positive power signal, and the PVEE signal can be, for example, a negative power signal.

[0085] Furthermore, Figures 7-12 only provide illustrative examples of several pixel circuit 200 structures, but do not include all of them. Other pixel circuits 200 whose power signals PVDD and PVEE satisfy the limitations defined in this application are all within the scope of protection of the embodiments of this application, and will not be described in detail in this embodiment.

[0086] Based on the different types of pixel circuits 200 described above, the driving circuit 100 in this embodiment can provide control signals to the data writing module 210, driving module 220, compensation module 230, reset module 250, initialization module 260, bias adjustment module 240, or light emission control module 270 in each type of pixel circuit 200. That is, the preset modules of the pixel circuit 200 mentioned above can be any one of the data writing module 210, driving module 220, compensation module 230, reset module 250, initialization module 260, bias adjustment module 240, or light emission control module 270, and the second output signal SN_OUT of the driving circuit 100 can be the control signal of at least one of the above modules. Taking the second output signal SN_OUT of the driving circuit 100 as the control signal of the data writing module 210 as an example, the driving principle of the pixel circuit 200 will be described below.

[0087] Referring again to Figure 5, generally, shift registers 110 at different levels provide drive signals to pixel circuits 200 in different rows, that is, they provide data writing control signals to data writing modules 210 in pixel circuits 200 in different rows. Taking the i-th level shift register 110 as an example, when the first voltage of the first output signal SN_NEXT1_i falls within the effective pulse time period of the frequency control signal SN_CTRL along the corresponding time period, the second output signal SN_OUT outputs a valid pulse. At this time, the data writing module 210 is turned on, the pixel circuit 200 begins to write data signals, and the storage capacitor C1 begins to charge. Furthermore, since the valid pulse output by the second output signal SN_OUT is a complete valid pulse, the storage capacitor C1 can be fully charged, allowing the light-emitting element 300 to emit light normally as required during the light-emitting stage. For the j-th stage shift register 110, when the time period corresponding to the first voltage edge of its first output signal SN_NEXT1_j falls within the invalid pulse time period of the frequency control signal SN_CTRL, and when the k-th stage shift register 110's first output signal SN_NEXT1_k has no corresponding first voltage edge, the second output signal SN_OUT outputs an invalid pulse. Therefore, the data writing module 210 cannot be activated, the charging process cannot be realized, and the corresponding light-emitting element 300 cannot emit light. Thus, the shift register 110 can control whether the light-emitting elements 300 in different rows emit light.

[0088] Those skilled in the art will understand that the activation process of other modules in the pixel circuit 200 during each data refresh cycle directly affects whether the pixel circuit 200 can drive the corresponding light-emitting element 300 to emit light. That is, except for the data writing module 210, when the second output signal SN_OUT is used as the control signal, the shift register 110 can control whether the corresponding light-emitting element 300 can emit light normally. Those skilled in the art can deduce this based on the specific functional implementation of different modules, which will not be elaborated here. The preset modules in the pixel circuit 200 here refer more to modules whose control signals are directly input from the outside, such as the data writing module 210, compensation module 230, reset module 250, initialization module 260, bias adjustment module 240, or light emission control module 270. For the driving module 220, which is controlled to be turned on or off by the input data signal, it is not directly controlled by the external signal. Therefore, the second output signal SN_OUT of the driving circuit 100 in this application cannot be used as the control signal of the preset modules of the pixel circuit 200.

[0089] Generally, the second output signal SN_OUT refers to a scanning signal where a high-level signal is a valid pulse, controlling the N-type transistor to turn on. In this embodiment, the second output signal SN_OUT can also be inverted to become a scanning signal where a low-level signal is a valid pulse, controlling the P-type transistor to turn on. Therefore, referring to Figures 7-12, taking the data writing module 210 as an example, the preset module in the pixel circuit 200 can include a P-type transistor, and the second output signal SN_OUT is the control signal for the P-type transistor. When the second output signal SN_OUT is a low-level signal, it is a valid pulse, controlling the P-type transistor to turn on. It can be understood that the data writing module 210 shown in Figures 7-12 can also be configured to include an N-type transistor. In this case, if the second output signal SN_OUT is the control signal for the N-type transistor, then when the second output signal SN_OUT is a high-level signal, it is a valid pulse, controlling the N-type transistor to turn on.

[0090] The preset module can also be other modules in the pixel circuit 200, such as the compensation module 230, reset module 250, initialization module 260, bias adjustment module 240, or light emission control module 270. Referring to Figures 7-12, for the reset module 250, it includes a P-type transistor. Therefore, the second output signal SN_OUT is the control signal for the P-type transistor. When the second output signal SN_OUT is a low-level signal, it is an effective pulse that controls the P-type transistor to turn on. Those skilled in the art will know that the effective pulses of the N-type transistor and the P-type transistor are at different potential levels. Therefore, the timing of the second output signal SN_OUT of the P-type transistor is not shown in the accompanying drawings.

[0091] As mentioned above, since each shift register 110 can control the light emission frequency of the corresponding light-emitting element 300 through the second control unit 20 and the frequency control signal SN_CTRL, the operating mode of the display panel as a whole can be changed. Optionally, Figures 13 and 14 are driving timing diagrams of two display panels provided in the embodiments of this application. As shown in Figures 13 and 14, the operation process of the display panel includes a first mode MODEL1 and a second mode MODEL2. One pulse of the frequency control signal SN_CTRL can be understood as a refresh frame or display frame. The operation process of the display panel corresponding to Figures 13 and 14 can be understood as the refresh status of the display panel under multiple refresh frames or display frames. The refresh status of the display panel under the first mode MODEL1 and the second mode MODEL2 is different.

[0092] In one specific embodiment, as shown in FIG13, in the first mode MODEL1, the pulse variation frequency of the frequency control signal SN_CTRL is Fc1, and in the second mode MODEL2, the pulse variation frequency of the frequency control signal SN_CTRL is Fc2, wherein Fc1 ≠ Fc2. And / or, in another specific embodiment, as shown in FIG14, in the first mode MODEL1, the effective pulse duration of the frequency control signal SN_CTRL is Wc1, and in the second mode MODEL2, the effective pulse duration of the frequency control signal SN_CTRL is Wc2, wherein Wc1 ≠ Wc2.

[0093] A valid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned on, connected, and working. An invalid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned off, cut off, and not working. In Figures 13 and 14, the valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both high level, and the invalid pulses are both low level. The valid pulse of the frequency control signal SN_CTRL is low level, and the invalid pulse is high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge.

[0094] Referring to Figures 5 and 6, the second output signal SN_OUT of the shift register 110 is mainly generated by the second control unit 20 based on the first output signal SN_NEXT1 output by the first control unit 10, controlled by the frequency control signal SN_CTRL. Whether the second output signal SN_OUT outputs a valid pulse depends on the valid pulse of the frequency control signal SN_CTRL. Therefore, the frequency Fc and duration Wc of the valid pulse of the frequency control signal SN_CTRL can change the number and frequency of the valid pulses of the second output signal SN_OUT. Taking one valid pulse of the second output signal SN_OUT as corresponding to one emission of the light-emitting element 300, the pulse change frequency Fc or the duration Wc of the valid pulse of the frequency control signal SN_CTRL directly determines the number of times or the frequency of emission of the light-emitting element 300. Therefore, by controlling all the light-emitting elements 300, the screen refresh rate or frequency of the display panel can be controlled macroscopically, thereby realizing the adjustment and switching of the working mode. Therefore, this embodiment essentially controls the driving process of the pixel circuit 200 in the display panel by changing the pulse frequency or the duration of the effective pulse of the frequency control signal SN_CTRL, thereby adjusting the light emission state of the light-emitting element 300 and thus realizing different working modes of the display panel on a macroscopic level.

[0095] Based on the above embodiments, in the first mode MODEL1, the pulse change frequency of the second output signal SN_OUT is Fs1, and in the second mode MODEL2, the pulse change frequency of the second output signal SN_OUT is Fs2; wherein, Fs1≠Fs2.

[0096] Referring again to Figures 13 and 14, the frequency control signal SN_CTRL directly determines the output of the effective pulse of the second output signal SN_OUT. Therefore, in different operating modes of the display panel, when the frequency Fc of the frequency control signal SN_CTRL or the duration Wc of the effective pulse is different, the corresponding frequency of the second output signal SN_OUT will also be different. That is, in the two different operating modes, MODEL1 and MODEL2, the pulse frequency Fs1 and Fs2 of the second output signal SN_OUT will necessarily be different. For example, the display panel in MODEL1 shown in Figure 13 has two refresh frames or display frames, while the display panel in MODEL2 shows one refresh frame or display frame. Similarly, the display panel in MODEL1 shown in Figure 14 has one refresh frame or display frame, while the display panel in MODEL2 shows one refresh frame or display frame.

[0097] For example, (Fc1-Fc2)×(Fs1-Fs2)>0; and / or, (Wc1-Wc2)×(Fs1-Fs2)>0.

[0098] It is understandable that, since the effective pulses of the frequency control signal SN_CTRL directly determine the output of the effective pulses of the second output signal SN_OUT, the number and duration of the effective pulses of the frequency control signal SN_CTRL determine the number of effective pulses of the second output signal SN_OUT. When the number of effective pulses of the frequency control signal SN_CTRL increases or the duration increases, the number of effective pulses of the second output signal SN_OUT will also increase. That is, within the same time period, the number and duration of the effective pulses of the second output signal SN_OUT are positively correlated with the number of effective pulses of the frequency control signal SN_CTRL. Therefore, the pulse change frequency Fs and duration Wc of the second output signal SN_OUT are positively correlated with the pulse change frequency Fc of the frequency control signal SN_CTRL. The larger the pulse change frequency Fc and the larger the duration Wc of the frequency control signal SN_CTRL, the larger the pulse change frequency Fs of the second output signal SN_OUT. Based on this, in the first mode MODEL1 and the second mode MODEL2, when Fc1-Fc2>0, then Fs1-Fs2>0; when Fc1-Fc2<0, then Fs1-Fs2<0; therefore, in the first mode MODEL1 and the second mode MODEL2, the pulse change frequency Fc of the frequency control signal SN_CTRL and the pulse change frequency Fs of the second output signal SN_OUT satisfy (Fc1-Fc2)×(Fs1-Fs2)>0. Similarly, in the first mode MODEL1 and the second mode MODEL2, when Wc1-Wc2>0, then Fs1-Fs2>0; when Wc1-Wc2<0, then Fs1-Fs2<0. Therefore, in the first mode MODEL1 and the second mode MODEL2, the duration Wc of the frequency control signal SN_CTRL and the pulse change frequency Fs of the second output signal SN_OUT satisfy (Wc1-Wc2)×(Fs1-Fs2)>0.

[0099] Figure 15 is a driving timing diagram of a pixel circuit provided in an embodiment of this application. Referring to Figures 7-12 and Figure 15, optionally, in an embodiment of this application, the operation process of the pixel circuit 200 includes a data write frame Tdata and a hold frame Thold; wherein, in the data write frame Tdata, the preset module is turned on; in the hold frame Thold, the preset module is turned off.

[0100] In Figure 15, the effective pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both at a high level, and the invalid pulses are both at a low level. The effective pulses of the frequency control signal SN_CTRL are at a low level, and the invalid pulses are at a high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge.

[0101] Here, the data write frame Tdata and hold frame Thold of the pixel circuit 200 can be understood as the display cycle of the display panel in two working modes. During the data write frame Tdata, the pixel circuit 200 writes data and drives the light emission using the written data during the light emission stage. The second output signal SN_OUT of the driving circuit 100 serves as the control signal for the preset module of the pixel circuit 200. By reasonably setting the frequency control signal SN_CTRL (containing a valid pulse and the first voltage edge corresponding to the first output signal SN_NEXT1 completely overlapping with the valid pulse), the second output signal SN_OUT can output a valid pulse in the data write frame Tdata, thereby turning on the preset module and realizing the data writing process of the pixel circuit 200, that is, realizing the data write frame Tdata. Similarly, during the hold frame Thold of the pixel circuit 200, the pixel circuit 200 does not write data, but uses the data stored in the storage capacitor C1 during the previous data write frame Tdata for light emission driving. The second output signal SN_OUT of the driving circuit 100 serves as the control signal for the preset module of the pixel circuit 200. By appropriately setting the frequency control signal SN_CTRL (which does not contain a valid pulse, or whose valid pulse does not overlap with the first voltage edge corresponding to the first output signal SN_NEXT1), the second output signal SN_OUT can output an invalid pulse in the data write frame Tdata, thereby turning off the preset module. This allows the pixel circuit 200 to retain the stored data without rewriting it, thus achieving the hold frame Thold. Essentially, this embodiment utilizes the frequency control signal SN_CTRL to control the preset module in the pixel circuit 200, thereby controlling whether data is written and implementing different data refresh methods.

[0102] In the first mode MODEL1, the data refresh frequency of the pixel circuit 200 is Fp1, and in the second mode MODEL2, the data refresh frequency of the pixel circuit 200 is Fp2; where Fp1≠Fp2.

[0103] As mentioned above, the display panel in this embodiment utilizes the frequency control signal SN_CTRL to control a preset module, enabling the pixel circuit 200 to switch between data write frames Tdata and hold frames Thold. This means the number of data write frames Tdata can be controlled, thereby changing the data refresh rate of the pixel circuit 200. Based on this, the display panel can achieve two operating modes using the frequency control signal SN_CTRL, each with a different data refresh rate. Specifically, the data refresh rate Fp1 in the first mode MODEL1 is not equal to the data refresh rate Fp2 in the second mode MODEL2. Therefore, the display panel can be used with different data refresh rates in different application scenarios. For example, when the display panel is playing movies or games, the data refresh rate can be increased to make the screen display smoother and meet the user's requirements for screen smoothness; when the display panel is displaying static images, the data refresh rate can be decreased to reduce drive power consumption and save energy.

[0104] Similarly, regarding the data refresh frequency of the pixel circuit 200, since the second output signal SN_OUT controls the on / off state of the preset module in the pixel circuit 200, it can adjust the data refresh frequency. Therefore, the pulse change frequency Fs of the second output signal SN_OUT directly determines the data refresh frequency Fp of the pixel circuit 200, showing a positive correlation. Thus, the larger the pulse change frequency Fs of the second output signal SN_OUT, the larger the data refresh frequency Fp of the pixel circuit 200. In the first mode MODEL1 and the second mode MODEL2, when Fs1-Fs2>0, then Fp1-Fp2>0; when Fs1-Fs2<0, then Fp1-Fp2<0. Therefore, in the first mode MODEL1 and the second mode MODEL2, the pulse change frequency Fs of the second output signal SN_OUT and the data refresh frequency Fp of the pixel circuit 200 satisfy (Fp1-Fp2)×(Fs1-Fs2)>0.

[0105] Figure 16 is a partial structural schematic diagram of a display panel provided in an embodiment of this application. Figures 17 and 18 are driving timing diagrams of the two shift registers shown in Figure 16. Referring first to Figure 16, optionally, the display panel includes a first pixel circuit 201 and a second pixel circuit 202, and the driving circuit 100 includes a first shift register 111 and a second shift register 112. The second output signal SN_OUT of the first shift register 111 is the control signal of the first preset module of the first pixel circuit 201, and the second output signal SN_OUT of the second shift register 112 is the control signal of the second preset module of the second pixel circuit 202.

[0106] Referring to Figures 17 and 18, in one specific embodiment, as shown in Figure 17, the pulse change frequency of the frequency control signal SN_CTRL received by the first shift register 111 is Fc11, and the pulse change frequency of the frequency control signal SN_CTRL received by the second shift register 112 is Fc22, where Fc11 ≠ Fc22; and / or, in another specific embodiment, as shown in Figure 18, the effective pulse duration of the frequency control signal SN_CTRL received by the first shift register 111 is Wc11, and the effective pulse duration of the frequency control signal SN_CTRL received by the second shift register 112 is Wc22, where Wc11 ≠ Wc22.

[0107] The first preset module in the first pixel circuit 201 and the second preset module in the second pixel circuit 202 are the same preset module. For example, as mentioned above, it can be a data writing module, a reset module, an initialization module, a threshold compensation module, etc. There are no restrictions here. The only difference is that they belong to different pixel circuits 200 and receive control from different shift registers 110. Referring to Figures 16-18, for shift registers 110 of different levels, such as the first shift register 111 and the second shift register 112, their second output signal SN_OUT is the control signal of the first preset module in the first pixel circuit 201 and the second pixel circuit 202, respectively. This means that the two shift registers 110 drive the first pixel circuit 201 and the second pixel circuit 202 respectively. Thus, the frequency control signal SN_CTRL received by the two shift registers 110 can actually drive the two pixel circuits 200 respectively. Different frequency control signals SN_CTRL can be provided to the two shift registers 110, that is, the pulse change frequency Fc of the frequency control signal SN_CTRL of the two shift registers 110 is different and / or the effective pulse duration Wc is different, so as to adjust the driving state of the two pixel circuits 200 respectively and realize different data refresh frequencies, etc.

[0108] Since the pulse change frequency Fc and / or effective pulse duration Wc of the frequency control signal SN_CTRL received by the two shift registers 110 are different, the pulse change frequency of the second output signal SN_OUT output by the two shift registers 110 will also be different. That is, the pulse change frequency of the second output signal SN_OUT received by the preset modules of the two pixel circuits 200 will also be different. Let the pulse change frequency of the second output signal SN_OUT received by the first preset module be Fs11, and the pulse change frequency of the second output signal SN_OUT received by the second preset module be Fs22; where Fs11≠Fs22.

[0109] For the two shift registers 110, namely the first shift register 111 and the second shift register 112, the pulse variation frequency Fs of the second output signal SN_OUT is related to the pulse variation frequency Fc of the received frequency control signal SN_CTRL and the duration Wc of the effective pulse, and they are positively correlated. Therefore, when the pulse variation frequency Fc of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Fc11-Fc22>0, the pulse variation frequency Fs of the second output signal SN_OUT satisfies Fs11-Fs22>0; conversely, when the pulse variation frequency Fc of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Fc11-Fc22<0, the pulse variation frequency Fs of the second output signal SN_OUT satisfies Fs11-Fs22<0. Therefore, it can be concluded that (Fc11-Fc22)×(Fs11-Fs22)>0. Similarly, when the effective pulse duration Wc of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Wc11-Wc22>0, the pulse change frequency Fs of the output second output signal SN_OUT satisfies Fs11-Fs22>0; conversely, when the effective pulse duration Wc of the frequency control signal SN_CTRL of the two shift registers 110 satisfies Wc11-Wc22<0, the pulse change frequency Fs of the output second output signal SN_OUT satisfies Fs11-Fs22<0. Therefore, (Wc11-Wc22)×(Fs11-Fs22)>0.

[0110] For the two pixel circuits 200, namely the first pixel circuit 201 and the second pixel circuit 202, different frequency control signals SN_CTRL can be provided to the two shift registers 110, causing the two shift registers 110 to output second output signals SN_OUT with different pulse change frequencies, so as to adjust the driving state of the two pixel circuits 200 respectively and achieve different data refresh frequencies. Therefore, in the embodiments of this application, the data refresh frequencies of the first pixel circuit 201 and the second pixel circuit 202 can be set to be different, and the data refresh frequency Fp11 of the first pixel circuit 201 is not equal to the data refresh frequency Fp22 of the second pixel circuit 202; that is, Fp11≠Fp22.

[0111] For the two pixel circuits 200, namely the first pixel circuit 201 and the second pixel circuit 202, their data refresh frequency Fp is related to the pulse change frequency Fs of the second output signal SN_OUT received by the preset module therein, and they are positively correlated.

[0112] When the pulse variation frequency Fs of the second output signal SN_OUT of the two shift registers 110 satisfies Fs11-Fs22>0, the data refresh frequency Fp of the corresponding two pixel circuits 200 satisfies Fp11-Fp22>0; conversely, when the pulse variation frequency Fs of the second output signal SN_OUT of the two shift registers 110 satisfies Fs11-Fs22<0, the data refresh frequency Fp of the corresponding two pixel circuits 200 satisfies Fp11-Fp22<0. Therefore, it can be concluded that (Fp11-Fp22)×(Fs11-Fs22)>0.

[0113] Referring again to Figure 16, the display panel may include a first display area 1000 and a second display area 2000, with a first pixel circuit 201 located in the first display area 1000 and a second pixel circuit 202 located in the second display area 2000.

[0114] Therefore, the first pixel circuit 201 and the second pixel circuit 202, as described above, are essentially set up as two display areas on the display panel. Thus, the refresh rates of the two display areas can be driven differently by using two shift registers 100 and their corresponding frequency control signals SN_CTRL, so that the two display areas of the display panel have different screen refresh rates.

[0115] In this embodiment, the first display area 1000 and the second display area 2000 of the display panel can be an active area (AA) and an under-display camera (CUP) area, respectively. Alternatively, they can be two display areas arranged periodically in a column direction within one cycle. This embodiment does not limit the specific method of partitioning; those skilled in the art can set it according to actual needs. As can be seen from the above, through the control of the shift register and the frequency control signal SN_CTRL in this embodiment, different display areas can have different screen refresh rates to adapt to the requirements of their respective areas for screen smoothness or display power consumption.

[0116] As described in the above embodiments, the cascaded shift register 110 in this application controls the output of the second output signal SN_OUT through the frequency control signal SN_CTRL, thereby controlling the preset modules in the pixel circuit 200, and switching and adjusting the data refresh frequency of the pixel circuit 200 and the screen refresh frequency of the display panel. Based on the above objectives, the embodiments of this application provide various specific structures of shift register 110. The structure and working process of each type of shift register 110 are described below with reference to the accompanying drawings.

[0117] In one specific embodiment, the second control unit of the shift register 110 includes a first control unit, a second control unit, a third control unit, and a second node; the first control unit further includes a third node, the potential of which is out of phase with the first output signal; the first control unit receives the potential signal and the first voltage signal of the first node, and is configured to control the second output signal to output an invalid pulse; the second control unit receives the potential signal and the frequency control signal of the first node, and is configured to control the potential of the second node; the third control unit receives the potential signal of the second node, the potential signal of the third node, and the second voltage signal, and is configured to control the second output signal to output a valid pulse; one of the first voltage signal and the second voltage signal is a high-level signal, and the other is a low-level signal. In another specific embodiment, the second control unit of the shift register 110 includes a first control unit, a second control unit, a third control unit, and a second node; the first control unit further includes a third node, the potential of which is inverted with the first output signal; the first control unit receives the potential signal and the first voltage signal of the first node, and is configured to control the second output signal to output an invalid pulse; the second control unit receives the potential signal and the frequency control signal of the first node, and is configured to control the potential of the second node; the third control unit receives the potential signal and the potential signal of the second node, and is configured to control the second output signal to output a valid pulse; the first voltage signal is a high-level signal or a low-level signal. The structure and operation of each type of shift register 110 will be described below with reference to the accompanying drawings.

[0118] Optionally, Figure 19 is a schematic diagram of the circuit structure of a shift register provided in an embodiment of this application. As shown in Figure 19, the second control unit 20 of the shift register 110 includes a first control unit 21, a second control unit 22, a third control unit 23, and a second node N2; the first control unit 10 also includes a third node N3, the potential of the third node N3 being out of phase with the first output signal SN_NEXT1; the first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, and is configured to control the second output signal SN_OUT to output an invalid pulse; the second control unit 22 receives the potential signal of the first node N1 and the frequency control signal SN_CTRL, and is configured to control the potential of the second node N2; the third control unit 23 receives the potential signal of the second node N2 and the potential signal of the third node N3, and is configured to control the second output signal SN_OUT to output a valid pulse; the first voltage signal V1 is a high-level signal VGH or a low-level signal VGL.

[0119] The first control unit 21 receives the potential signal and the first voltage signal V1 from the first node N1. That is, under the control of the potential signal and the first voltage signal V1 of the first node N1, the second output signal SN_OUT can be output as an invalid pulse. The second node N2 can be understood as the node controlled by the second control unit 22, and also the node controlling the output of the third control unit 23. Under the control of the potential signal and the frequency control signal SN_CTRL of the first node N1, the potential of the second node N2 can change, thereby changing the output potential of the third control unit 23 controlled by the potential signal of the second node N2, generating the second output signal SN_OUT, so that the second output signal SN_OUT can be output as a valid pulse. It can be understood that the first voltage signal V1 participates in the control process of the second output signal SN_OUT outputting an invalid pulse. Thus, depending on whether the invalid pulse of the second output signal SN_OUT is high or low, the first voltage signal V1 can be selected as a high-level signal VGH or a low-level signal VGL.

[0120] For example, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The first control unit 21 can be set to turn on when the first output signal SN_NEXT1 is a valid pulse and turn off when the first output signal SN_NEXT1 is an invalid pulse. The first control unit 21 shown in Figure 19 includes a first transistor M1, for example, a P-type transistor. At this time, a valid pulse of the first output signal SN_NEXT1 is a low-level signal, and an invalid pulse is a high-level signal; that is, when the first output signal SN_NEXT1 is a low-level signal, the first transistor M1 in the first control unit 21 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the first transistor M1 in the first control unit 21 is turned off.

[0121] At this time, the first output signal SN_NEXT1 is essentially a control signal for the first control unit 21, connected to the control terminal of the first control unit 21. The first output signal SN_NEXT1 controls the first control unit 21 to be turned on or off. Optionally, when the first control unit 21 is turned on, the level signal corresponding to the first voltage signal V1 can be used to generate the second output signal SN_OUT. At this time, the second output signal SN_OUT outputs an invalid pulse. For example, the invalid pulses of the first voltage signal V1 and the second output signal SN_OUT can both be low-level signals VGL.

[0122] Similarly, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The second control unit 22 can be set to turn on when the first output signal SN_NEXT1 is a valid pulse and turn off when the first output signal SN_NEXT1 is an invalid pulse. The second control unit 22 shown in Figure 19 includes a second transistor M2 and a second capacitor C2, for example, a P-type transistor. At this time, a valid pulse of the first output signal SN_NEXT1 is a low-level signal, and an invalid pulse is a high-level signal. That is, when the first output signal SN_NEXT1 is a low-level signal, the second transistor M2 in the second control unit 22 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the second transistor M2 in the second control unit 22 is turned off.

[0123] At this time, the first output signal SN_NEXT1 is also essentially a control signal for the second control unit 22, connected to the control terminal of the second control unit 22, and controls the second control unit 22 to be turned on or off through the first output signal SN_NEXT1. Optionally, when the second control unit 22 is turned on, the level signal corresponding to the frequency control signal SN_CTRL can be used to generate the potential signal of the second node N2, and the potential signal of the second node N2 can also be stored in the second capacitor C2.

[0124] In this embodiment, the node in the first control unit 10 is essentially brought out as the third node N3. The specific location and connection relationship of the third node N3 in the first control unit 10 will be described in detail later and will not be explained here. Furthermore, the potential of the third node N3 is out of phase with the first output signal SN_NEXT1. Therefore, when the first output signal SN_NEXT1 is a valid pulse, the potential signal of the third node N3 is an invalid pulse, and when the first output signal SN_NEXT1 is an invalid pulse, the potential signal of the third node N3 is a valid pulse. For example, the potential signal of the third node N3 can be a control signal of the third control unit 23, connected to the control terminal of the third control unit 23, controlling the conduction or deactivation of the third control unit 23 through the potential signal of the third node N3. For example, the third control unit 23 can be set to be turned on when the potential signal of the third node N3 is a valid pulse, and turned off when the potential signal of the third node N3 is an invalid pulse. The third control unit 23 shown in Figure 19 includes a third transistor M3, for example, a P-type transistor. At this time, the effective pulse of the potential signal of the third node N3 is a low-level signal, and the invalid pulse is a high-level signal. That is, when the potential signal of the third node N3 is a low-level signal, the third transistor M3 in the third control unit 23 is turned on; when the potential signal of the third node N3 is a high-level signal, the third transistor M3 in the third control unit 23 is turned off.

[0125] At this time, the potential signal of the second node N2 is essentially the conduction signal of the third control unit 23. Connecting one end of the third control unit 23, the potential signal of the other end of the third control unit 23 is controlled by the potential signal of the second node N2. Optionally, when the third control unit 23 is turned on, the level signal corresponding to the second node N2 can be used to generate the second output signal SN_OUT, and at this time the second output signal SN_OUT outputs a valid pulse. For example, all valid pulses of the second output signal SN_OUT can be high-level signals.

[0126] Optionally, continuing to refer to FIG19, the first control unit 21 includes a first transistor M1, the control terminal of the first transistor M1 is electrically connected to the first node N1, the first terminal of the first transistor M1 receives a first voltage signal V1, and the second terminal of the first transistor M1 outputs an invalid pulse of the second output signal SN_OUT.

[0127] For example, the first transistor M1 can be configured as a P-type transistor. In this case, the valid pulse of the potential signal of the first node N1 is a low-level signal, and the invalid pulse is a high-level signal. For example, the first voltage signal V1 can be VGL, and the invalid pulse of the second output signal SN_OUT corresponds to a low-level signal. That is, when the first transistor M1 is turned on and the first voltage signal V1 is VGL, the second output signal SN_OUT outputs an invalid pulse.

[0128] Referring again to Figure 19, the first control unit 21 also includes a first capacitor C1. The first plate of the first capacitor C1 is connected to the control terminal of the first transistor M1, and the second plate of the first capacitor C1 is connected to the second terminal of the first transistor M1.

[0129] For example, the control terminal of the first transistor M1 is the gate, and the second terminal of the first transistor M1 is the source. Thus, the two ends of the first capacitor C1 are connected between the gate and the source of the first transistor M1, so that a voltage difference is formed between the gate and the source of the first transistor M1, and the voltage difference is lower than the threshold voltage of the first transistor M1, thereby ensuring that the first transistor M1 is in the conducting state.

[0130] Optionally, referring to Figure 19, the second control unit 22 includes a second transistor M2 and a second capacitor C2; the control terminal of the second transistor M2 is electrically connected to the first node N1, the first terminal of the second transistor M2 receives the frequency control signal SN_CTRL, the second terminal of the second transistor M2 is electrically connected to the first plate of the second capacitor C2 and the second node N2 respectively, and the second plate of the second capacitor C2 receives the fixed potential signal V'.

[0131] For example, the second transistor M2 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal at the first node N1 is a low-level signal, and the invalid pulse is a high-level signal. For example, the first terminal of the second transistor M2 receives the frequency control signal SN_CTRL, and the second terminal of the second transistor M2 is electrically connected to the second node N2. That is, when the second transistor M2 is turned on, the potential signal of the frequency control signal SN_CTRL can be generated at the second node N2. Simultaneously, the second terminal of the second transistor M2 is electrically connected to the second capacitor C2, which can also store the potential signal of the frequency control signal SN_CTRL. When the second transistor M2 is turned off, the potential signal of the frequency control signal SN_CTRL stored in the second capacitor C2 can be released to the second node N2, so that the second node N2 remains floating with the potential signal of the frequency control signal SN_CTRL. When the second transistor M2 is turned off, regardless of whether the frequency control signal SN_CTRL at the first terminal of the second transistor M2 is an effective pulse or an invalid pulse, the potential signal at the second terminal of the second transistor M2 remains the potential signal of the frequency control signal SN_CTRL. The function of the second transistor M2 is to write the frequency control signal SN_CTRL to the second node N2 after a complete pulse signal is output from the first node N1. This prevents a situation where a valid pulse is output from the first node N1 when the frequency control signal SN_CTRL changes, resulting in an incomplete second output signal SN_OUT. In other words, the configuration of the second transistor M2 and the second capacitor C2 is fundamental to solving the problem of incomplete pulse signal output caused by the truncation of the potential signal at the second node N2 by the frequency control signal SN_CTRL, thus resolving the issue of incomplete pulse signal output caused by the truncation of the valid pulse of the second output signal SN_OUT by the frequency control signal SN_CTRL.

[0132] Referring again to Figure 19, the third control unit 23 includes a third transistor M3. The control terminal of the third transistor M3 is electrically connected to the third node N3, the first terminal of the third transistor M3 is electrically connected to the second node N2, and the second terminal of the third transistor M3 outputs a valid pulse of the second output signal SN_OUT.

[0133] For example, the third transistor M3 can be configured as a P-type transistor. In this case, the valid pulse of the potential signal of the third node N3 is a low-level signal, and the invalid pulse is a high-level signal. For example, when the valid pulse of the potential signal of the third node N3 is a low-level signal, the valid pulse of the second output signal SN_OUT corresponds to a high-level signal. That is, when the third transistor M3 is turned on, the second output signal SN_OUT outputs a valid pulse.

[0134] Figure 20 is a timing diagram of a drive for the second control unit in the shift register shown in Figure 19. Referring to Figures 19 and 20, the working principle and process of the second control unit 20 in the shift register according to an embodiment of this application will be described below:

[0135] A valid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned on, connected, and working. An invalid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned off, cut off, and not working. In Figure 20, the valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both high level, and the invalid pulses are both low level. The valid pulse of the frequency control signal SN_CTRL is high level, and the invalid pulse is low level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. The first voltage signal V1 is a low level signal VGL, and the fixed voltage signal V' is a high level signal VGH or a low level signal VGL.

[0136] During the Ta phase, the first output signal SN_NEXT1 is low, has no rising edge, and the frequency control signal SN_CTRL is high. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, the first node N1 is low, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2. Since the third node N3 is high and the third transistor M3 is turned off, the high level of the frequency control signal SN_CTRL can be stored at the second capacitor C2.

[0137] During the Tb stage, the first output signal SN_NEXT1 is at a high level and has a rising edge. The frequency control signal SN_CTRL changes from a high level to a low level. At this time, the first node N1 is at a high level, and both the first transistor M1 and the second transistor M2 are turned off. Meanwhile, the third node N3 is at a low level, and the third transistor M3 is turned on. The potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 is transmitted to the output terminal through the third transistor M3, making the second output signal SN_OUT high, which is a valid pulse.

[0138] During the Tc phase, the first output signal SN_NEXT1 is low, and there is no rising edge for it. The frequency control signal SN_CTRL is also low. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, the first node N1 is low, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2. Since the third node N3 is high, the third transistor M3 is turned off, and the low level of the frequency control signal SN_CTRL can be stored at the second capacitor C2.

[0139] Furthermore, Figure 21 is another driving timing diagram of the second control unit in the shift register shown in Figure 19. Referring to Figures 19 and 21, the working principle and process of the second control unit 20 in the shift register of this application embodiment will be described below:

[0140] A valid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned on, connected, and working. An invalid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned off, cut off, and not working. In Figure 21, the valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both high level, and the invalid pulses are both low level. The valid pulse of the frequency control signal SN_CTRL is high level, and the invalid pulse is low level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. The first voltage signal V1 is a low level signal VGL, and the fixed voltage signal V' is a high level signal VGH or a low level signal VGL.

[0141] During the Td phase, the first output signal SN_NEXT1 is low and has no rising edge. The frequency control signal SN_CTRL is high. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, the first node N1 is low, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2. Since the third node N3 is high and the third transistor M3 is turned off, the high level of the frequency control signal SN_CTRL can be stored at the second capacitor C2.

[0142] During the Te stage, the first output signal SN_NEXT1 is low, and there is no rising edge. The frequency control signal SN_CTRL transitions from high to low. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, the first node N1 is low, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2. Since the third node N3 is still high, the third transistor M3 remains off.

[0143] During the Tf phase, the first output signal SN_NEXT1 is high and has a rising edge. The frequency control signal SN_CTRL is low. At this time, the first node N1 is high, and both the first transistor M1 and the second transistor M2 are turned off. Meanwhile, the third node N3 is low and the third transistor M3 is turned on. The potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 is transmitted to the output terminal through the third transistor M3, making the second output signal SN_OUT low.

[0144] During the Tg phase, the first output signal SN_NEXT1 is low, and there is no rising edge. The frequency control signal SN_CTRL is also low. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, the first node N1 is low, the second transistor M2 is turned on, and the frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2. Since the third node N3 is high, the third transistor M3 is turned off, and the low level of the frequency control signal SN_CTRL can be stored at the second capacitor C2.

[0145] Optionally, Figure 22 is a schematic diagram of the circuit structure of another shift register provided in an embodiment of this application. As shown in Figure 22, the second control unit 20 of the shift register 110 includes a first control unit 21, a second control unit 22, a third control unit 23, and a second node N2. The first control unit 10 also includes a third node N3, the potential of the third node N3 being out of phase with the first output signal SN_NEXT1. The first control unit 21 receives the potential signal of the first node N1 and the first voltage signal V1, and is configured to control the second output signal SN_OUT to output an invalid pulse. The second control unit 22 receives the potential signal of the first node N1 and the frequency control signal SN_CTRL, and is configured to control the potential of the second node N2. The third control unit 23 receives the potential signal of the second node N2, the potential signal of the third node N3, and the second voltage signal V2, and is configured to control the second output signal SN_OUT to output a valid pulse. One of the first voltage signal V1 and the second voltage signal V2 is a high-level signal VGH, and the other is a low-level signal VGL.

[0146] The first control unit 21 receives the potential signal and the first voltage signal V1 from the first node N1. That is, under the control of the potential signal and the first voltage signal V1 of the first node N1, the second output signal SN_OUT can be output as an invalid pulse. The second node N2 can be understood as the node controlled by the second control unit 22, and also the node controlling the output of the third control unit 23. Under the control of the potential signal and the frequency control signal SN_CTRL of the first node N1, the potential of the second node N2 can change, thereby changing the output potential of the third control unit 23 controlled by the potential signal of the second node N2 and the second voltage signal V2, generating the second output signal SN_OUT, so that the second output signal SN_OUT can be output as a valid pulse. It is understandable that the first voltage signal V1 participates in the control process of the second output signal SN_OUT outputting invalid pulses, and the second voltage signal V2 participates in the control process of the second output signal SN_OUT outputting valid pulses. For example, VGH is the voltage value of the high-level signal in the first voltage signal V1 and the second voltage signal V2, and VGL is the voltage value of the low-level signal in the first voltage signal V1 and the second voltage signal V2. Therefore, by controlling the output of the first voltage signal V1 or the second voltage signal V2, the switching between the high-level signal and the low-level signal of the second output signal SN_OUT, that is, the switching between valid pulses and invalid pulses, can be realized.

[0147] For example, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The first control unit 21 can be set to turn on when the first output signal SN_NEXT1 is a valid pulse and turn off when the first output signal SN_NEXT1 is an invalid pulse. The first control unit 21 shown in Figure 22 includes a first transistor M1, for example, a P-type transistor. At this time, a valid pulse of the first output signal SN_NEXT1 is a low-level signal, and an invalid pulse is a high-level signal; that is, when the first output signal SN_NEXT1 is a low-level signal, the first transistor M1 in the first control unit 21 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the first transistor M1 in the first control unit 21 is turned off.

[0148] At this time, the first output signal SN_NEXT1 is also essentially a control signal for the first control unit 21, connected to the control terminal of the first control unit 21, and controls the first control unit 21 to be turned on or off through the first output signal SN_NEXT1. Optionally, when the first control unit 21 is turned on, the level signal corresponding to the first voltage signal V1 can be used to generate the second output signal SN_OUT, and at this time the second output signal SN_OUT outputs an invalid pulse. For example, the invalid pulses of the first voltage signal V1 and the second output signal SN_OUT can both be low-level signals VGL.

[0149] Similarly, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The second control unit 22 can be set to turn on when the first output signal SN_NEXT1 is a valid pulse and turn off when the first output signal SN_NEXT1 is an invalid pulse. The second control unit 22 shown in Figure 22 includes a second transistor M2 and a second capacitor C2, for example, a P-type transistor. At this time, a valid pulse of the first output signal SN_NEXT1 is a low-level signal, and an invalid pulse is a high-level signal. That is, when the first output signal SN_NEXT1 is a low-level signal, the second transistor M2 in the second control unit 22 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the second transistor M2 in the second control unit 22 is turned off.

[0150] At this time, the first output signal SN_NEXT1 is essentially the control signal of the second control unit 22, connected to the control terminal of the second control unit 22, and controls the conduction or de-conduction of the second control unit 22 through the first output signal SN_NEXT1. Optionally, when the second control unit 22 is turned on, the level signal corresponding to the frequency control signal SN_CTRL can be used to generate the potential signal of the second node N2, and the potential signal of the second node N2 can also be stored in the second capacitor C2. Furthermore, the potential signal of the second node N2 can also essentially be the turn-on signal of the third control unit 23, connected to the control terminal of the third control unit 23, and controls the conduction or de-conduction of the third control unit 23 through the potential signal of the second node N2. Afterwards, it can be set that when the potential signal of the second node N2 is a valid pulse, the third control unit 23 is turned on; when the potential signal of the second node N2 is an invalid pulse, the third control unit 23 is turned off. The third control unit 23 shown in Figure 22 includes a third transistor M3, for example, a P-type transistor. At this time, the effective pulse of the potential signal of the second node N2 is a low-level signal, and the invalid pulse is a high-level signal. That is, when the potential signal of the second node N2 is a low-level signal, the third transistor M3 in the third control unit 23 is turned on; when the potential signal of the second node N2 is a high-level signal, the third transistor M3 in the third control unit 23 is turned off.

[0151] In this embodiment, the node in the first control unit 10 is essentially brought out as the third node N3. The specific location and connection relationship of the third node N3 in the first control unit 10 will be described in detail later and will not be explained here. Furthermore, the potential of the third node N3 is out of phase with the first output signal SN_NEXT1. Therefore, when the first output signal SN_NEXT1 is a valid pulse, the potential signal of the third node N3 is an invalid pulse, and when the first output signal SN_NEXT1 is an invalid pulse, the potential signal of the third node N3 is a valid pulse. For example, the potential signal of the third node N3 can be the turn-on signal of the third control unit 23, connected to one end of the third control unit 23, controlling whether the potential signal at the other end of the third control unit 23 is generated. Optionally, when the third control unit 23 is turned on, the potential signal corresponding to the third node N3 and the second voltage signal V2 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT outputs a valid pulse. For example, all valid pulses of the second output signal SN_OUT can be high-level signals.

[0152] Optionally, continuing to refer to FIG22, the first control unit 21 includes a first transistor M1, the control terminal of the first transistor M1 is electrically connected to the first node N1, the first terminal of the first transistor M1 receives a first voltage signal V1, and the second terminal of the first transistor M1 outputs an invalid pulse of the second output signal SN_OUT.

[0153] Optionally, continuing to refer to FIG22, the first control unit 21 further includes a first capacitor C1, the first plate of the first capacitor C1 being connected to the control terminal of the first transistor M1, and the second plate of the first capacitor C1 being connected to the second terminal of the first transistor M1.

[0154] Optionally, referring to FIG22, the second control unit 22 includes a second transistor M2 and a second capacitor C2; the control terminal of the second transistor M2 is electrically connected to the first node N1, the first terminal of the second transistor M2 receives the frequency control signal SN_CTRL, the second terminal of the second transistor M2 is electrically connected to the first plate of the second capacitor C2 and the second node N2 respectively, and the second plate of the second capacitor C2 receives the fixed potential signal V'.

[0155] Optionally, continuing to refer to Figure 22, the third control unit 23 includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; the control terminal of the fourth transistor M4 is electrically connected to the second node N2, the first terminal of the fourth transistor M4 is electrically connected to the third node N3, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the fifth transistor M5 and the control terminal of the sixth transistor M6, respectively; the control terminal of the fifth transistor M5 is electrically connected to the first node N1, and the second terminal of the fifth transistor M5 receives a third voltage signal V3; the third voltage signal V3 has the same potential as the effective pulse of the first output signal SN_NEXT1; the first terminal of the sixth transistor M6 receives a second voltage signal V2, and the second terminal of the sixth transistor M6 outputs the effective pulse of the second output signal SN_OUT.

[0156] For example, any one of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. For example, the control terminal of the fourth transistor M4 is electrically connected to the second node N2, the first terminal of the fourth transistor M4 is electrically connected to the third node N3, and the second terminal of the fourth transistor M4 is electrically connected to the first terminal of the fifth transistor M5 and the control terminal of the sixth transistor M6, respectively. That is, when the fourth transistor M4 is turned on, the potential signal at the third node N3 can be output to the first terminal of the fifth transistor M5, and at the same time, the potential signal at the third node N3 can also be output to the control terminal of the sixth transistor M6. Furthermore, the control terminal of the fifth transistor M5 is electrically connected to the first node N1. The potential of the third node N3 is out of phase with the first output signal SN_NEXT1, and the potential of the first node N1 is in phase with the first output signal SN_NEXT1. The third voltage signal V3 is at the same potential as the effective pulse of the first output signal SN_NEXT1. Thus, when the fifth transistor M5 is turned on, the potential signal at the third node N3 at the first terminal of the fifth transistor M5 and the third voltage signal V3 at the second terminal of the fifth transistor M5 can both be high-level signals VGH. Also, the control terminal of the sixth transistor M6 is electrically connected to the third node N3. The first terminal of the sixth transistor M6 receives the second voltage signal V2. That is, when the sixth transistor M6 is turned on, the level signal corresponding to the second voltage signal V2 can be used to generate the second output signal SN_OUT. At this time, the second output signal SN_OUT outputs an effective pulse. For example, the second voltage signal V2 can be VGH, and the effective pulse of the second output signal SN_OUT can be the high-level signal VGH.

[0157] Referring again to Figure 22, the third control unit 23 further includes a third capacitor C3. The first plate of the third capacitor C3 is electrically connected to the control terminal of the sixth transistor M6. The second plate of the third capacitor C3 is connected to the control terminal of the sixth transistor M6 as the gate and the first terminal of the sixth transistor M6 as the source. Thus, the two ends of the third capacitor C3 are connected between the gate and the source of the sixth transistor M6, so that a voltage difference is formed between the gate and the source of the sixth transistor M6, and the voltage difference is lower than the threshold voltage of the sixth transistor M6, thereby ensuring that the sixth transistor M6 is in the conducting state.

[0158] Optionally, continuing to refer to Figure 22, the second voltage signal V2 and the third voltage signal V3 are voltage signals at the same potential.

[0159] When the fifth transistor M5 is turned on, the potential signal at the third node N3 at the first terminal of the fifth transistor M5 and the third voltage signal V3 at the second terminal of the fifth transistor M5 can both be high-level signals VGH. When the sixth transistor M6 is turned on, the level signal corresponding to the second voltage signal V2 can be used to generate the second output signal SN_OUT, and at this time, the second output signal SN_OUT outputs a valid pulse. For example, the second voltage signal V2 can be VGH, and the valid pulse of the second output signal SN_OUT can be a high-level signal. That is, the second voltage signal V2 and the third voltage signal V3 can both be high-level signals VGH.

[0160] Figure 23 is a timing diagram of a drive for the second control unit in the shift register shown in Figure 22. Referring to Figures 22 and 23, the working principle and process of the second control unit 20 in the shift register according to an embodiment of this application will be described below:

[0161] A valid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned on, connected, and working. An invalid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned off, cut off, and not working. In Figure 23, the valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both high level, and the invalid pulses are both low level. The valid pulse of the frequency control signal SN_CTRL is low level, and the invalid pulse is high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. The first voltage signal V1 is a low level signal VGL, the second voltage signal V2 is a high level signal VGH, the third voltage signal V3 is a high level signal VGH, and the fixed voltage signal V' is a high level signal VGH.

[0162] During the Th phase, the first output signal SN_NEXT1 is low, and there is no rising edge. The frequency control signal SN_CTRL is also low. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, with the first node N1 low, the second transistor M2 and the fifth transistor M5 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, which in turn turns on the fourth transistor M4. Furthermore, the third voltage signal V3 is transmitted to the control terminal of the sixth transistor M6 through the fifth transistor M5 (or, since the third node N3 is high), the sixth transistor M6 is turned off. The potential signal of the frequency control signal SN_CTRL can then be stored at the second capacitor C2.

[0163] During stage Ti, the first output signal SN_NEXT1 is at a high level and has a rising edge. The frequency control signal SN_CTRL changes from low to high. At this time, the first node N1 is at a high level, and the first transistor M1, the second transistor M2, and the fifth transistor M5 are all turned off. The potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 causes the fourth transistor M4 to turn on. At the same time, the third node N3 is at a low level. The third node N3 is transmitted to the control terminal of the sixth transistor M6 through the fourth transistor M4. The sixth transistor M6 turns on, and the second voltage signal V2 is transmitted to the output terminal through the sixth transistor M6, making the second output signal SN_OUT high.

[0164] During phase Tj, the first output signal SN_NEXT1 is low, and there is no rising edge. The frequency control signal SN_CTRL is also low. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, with the first node N1 low, the second transistor M2 and the fifth transistor M5 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, which in turn turns on the fourth transistor M4. Furthermore, the third voltage signal V3 is transmitted to the control terminal of the sixth transistor M6 through the fifth transistor M5 (or, since the third node N3 is high), the sixth transistor M6 is turned off. Thus, the potential signal of the frequency control signal SN_CTRL is still stored at the second capacitor C2.

[0165] Figure 24 is another driving timing diagram of the second control unit in the shift register shown in Figure 22. Referring to Figures 22 and 24, the working principle and process of the second control unit 20 in the shift register of this application embodiment will be described below:

[0166] A valid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned on, connected, and working. An invalid pulse can be understood as the control of the corresponding connected unit, circuit, etc. to be turned off, cut off, and not working. In Figure 24, the valid pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both high level, and the invalid pulses are both low level. The valid pulse of the frequency control signal SN_CTRL is low level, and the invalid pulse is high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. The first voltage signal V1 is a low level signal VGL, the second voltage signal V2 is a high level signal VGH, the third voltage signal V3 is a high level signal VGH, and the fixed voltage signal V' is a high level signal VGH.

[0167] During the Tk phase, the first output signal SN_NEXT1 is low and has no rising edge. The frequency control signal SN_CTRL is high. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, with the first node N1 low, the second transistor M2 and the fifth transistor M5 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, causing the fourth transistor M4 to turn off. Furthermore, the third voltage signal V3 is transmitted to the control terminal of the sixth transistor M6 through the fifth transistor M5, causing the sixth transistor M6 to turn off. The potential signal of the frequency control signal SN_CTRL can then be stored at the second capacitor C2.

[0168] During stage T1, the first output signal SN_NEXT1 is at a high level, and there is a rising edge to the first output signal SN_NEXT1. The frequency control signal SN_CTRL is at a high level. At this time, the first node N1 is at a high level, and the first transistor M1, the second transistor M2, and the fifth transistor M5 are all turned off. The potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 still causes the fourth transistor M4 to be turned off. At the same time, the third voltage signal V3 stored at the third capacitor C3 causes the sixth transistor M6 to be turned off. Then, the level of the second output signal SN_OUT is floated to the low level of stage Tk.

[0169] During the Tm phase, the first output signal SN_NEXT1 is low, has no rising edge, and the frequency control signal SN_CTRL is high. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, with the first node N1 low, the second transistor M2 and the fifth transistor M5 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, which in turn turns on the fourth transistor M4. Furthermore, the third voltage signal V3 is transmitted to the control terminal of the sixth transistor M6 through the fifth transistor M5 (or, due to the third node N3 being high), the sixth transistor M6 is turned off. Thus, the potential signal of the frequency control signal SN_CTRL is still stored at the second capacitor C2.

[0170] Optionally, continuing to refer to Figures 5 and 19, and to Figures 6 and 22, when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, neither the first control unit 21 nor the third control unit 23 outputs anything, and the second output signal SN_OUT maintains the level state of the second output signal SN_OUT when the first output signal SN_NEXT1 is an invalid pulse.

[0171] In this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for ensuring that when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the transistor inside the first control unit 21 is not turned on, and the first control unit 21 does not output. Therefore, the first control unit 21 cannot control the second output signal SN_OUT to output an invalid pulse. Simultaneously, the transistor inside the third control unit 23 is not turned on, and the third control unit 23 does not output. Therefore, the third control unit 23 cannot control the second output signal SN_OUT to output a valid pulse. Thus, the second output signal SN_OUT needs to maintain the same level state as when the first output signal SN_NEXT1 is an invalid pulse; that is, the second output signal SN_OUT maintains the output of an invalid pulse. When neither the first control unit 21 nor the third control unit 23 outputs, the output of the second output signal SN_OUT can be floated at the level state of the previous moment.

[0172] Optionally, based on Figure 22, Figure 25 is a schematic diagram of the circuit structure of another shift register provided in the embodiment of this application. As shown in Figure 25, the second control unit 20 further includes a fourth control unit 24. The fourth control unit 24 receives at least the potential signal of the first node N1 and controls the second output signal SN_OUT to output an invalid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL.

[0173] It is understandable that when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL, the floating level state of the second output signal SN_OUT is unstable and easily affected by other level signals. If the output of the second output signal SN_OUT changes from an invalid pulse to a valid pulse at this time, it will affect the operation of the corresponding pixel circuit 200 and the accuracy of partition refresh. Therefore, this embodiment additionally sets a fourth control unit 24, which, at least through the potential signal of the first node N1, is responsible for controlling the output of the second output signal SN_OUT to be an invalid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the invalid pulse of the frequency control signal SN_CTRL. At this time, the invalid pulse corresponding to the second output signal SN_OUT is output under the control of the fourth control unit 24, rather than the floating level state of the second output signal SN_OUT, and is less susceptible to interference from other level signals, making the second output signal SN_OUT more stable.

[0174] Referring again to Figure 25, the fourth control unit 24 is also configured to control the second output signal SN_OUT, and output a valid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL and the first output signal SN_NEXT1 is a valid pulse.

[0175] In this embodiment, a fourth control unit 24 is additionally provided. This control unit, at least through the potential signal of the first node N1, is responsible for controlling the second output signal SN_OUT to output a valid pulse when the first voltage edge of the first output signal SN_NEXT1 overlaps with the valid pulse of the frequency control signal SN_CTRL and the first output signal SN_NEXT1 is a valid pulse. At this time, the valid pulse corresponding to the second output signal SN_OUT is the result of the combined action of the fourth control unit 24 and / or the third control unit 23, which further ensures the output of the valid pulse corresponding to the second output signal SN_OUT.

[0176] Optionally, continuing to refer to Figure 25, the fourth control unit 24 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and a fourth capacitor C4; the control terminal of the seventh transistor M7 is electrically connected to the first node N1, the first terminal of the seventh transistor M7 receives the fourth voltage signal V4, and the second terminal of the seventh transistor M7 is electrically connected to the first terminals of the eighth transistor M8 and the ninth transistor M9, respectively; the second terminal of the eighth transistor M8 receives the fifth voltage signal V5, and the conduction state of the eighth transistor M8 is synchronized with the conduction state of the third control unit 23; the control terminal of the ninth transistor M9 receives the sixth voltage signal V6, and the ninth transistor... The second terminal of transistor M9 is connected to the control terminal of the tenth transistor M10 and the first plate of the fourth capacitor C4, respectively. The first terminal of the tenth transistor M10 receives the seventh voltage signal V7. The second terminal of the tenth transistor M10 is electrically connected to the second plate of the fourth capacitor C4 and outputs the second output signal SN_OUT. The fourth voltage signal V4 has the same potential as the invalid pulse of the second output signal SN_OUT. The fifth voltage signal V5 has the same potential as the valid pulse of the second output signal SN_OUT. The sixth voltage signal V6 is configured to control the ninth transistor M9 to be normally open. The seventh voltage signal V7 has the same potential as the invalid pulse of the second output signal SN_OUT.

[0177] Any one of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. For example, the control terminal of the seventh transistor M7 is electrically connected to the first node N1. The first terminal of the seventh transistor M7 receives the fourth voltage signal V4. The second terminal of the seventh transistor M7 is electrically connected to the first terminals of the eighth transistor M8 and the ninth transistor M9, respectively. That is, when the seventh transistor M7 is turned on, the fourth voltage signal V4 can be output to the first terminal of the eighth transistor M8, and simultaneously, the fourth voltage signal V4 can be output to the first terminal of the ninth transistor M9. Furthermore, the conduction state of the eighth transistor M8 is synchronized with the conduction state of the third control unit 23. For example, the control terminal of the eighth transistor M8 and the control terminals of the transistors in the third control unit 23 are controlled by the same level signal, and both the eighth transistor M8 and the transistors in the third control unit 23 are, for example, P-type transistors, thereby ensuring that the eighth transistor M8 and the third control unit 23 are synchronously turned on or off. The second terminal of the eighth transistor M8 receives the fifth voltage signal V5. That is, when the eighth transistor M8 is turned on, the fifth voltage signal V5 at the second terminal of the eighth transistor M8 is output to the first terminal of the eighth transistor M8. The control terminal of the ninth transistor M9 receives the sixth voltage signal V6. The second terminal of the ninth transistor M9 is connected to the control terminal of the tenth transistor M10 and the first plate of the fourth capacitor C4. The sixth voltage signal V6 is configured to control the ninth transistor M9 to be normally open. That is, when the ninth transistor M9 is turned on and the seventh transistor M7 is turned on, the fourth voltage signal V4 at the first terminal of the ninth transistor M9 can be output to the second terminal of the ninth transistor M9, i.e., output to the control terminal of the tenth transistor M10. Simultaneously, the fourth capacitor C4 can also store the level signal at the control terminal of the tenth transistor M10. Alternatively, the sixth voltage signal V6 is configured to control the ninth transistor M9 to be normally open. When the ninth transistor M9 is turned on, and the eighth transistor M8 is also turned on, the fifth voltage signal V5 at the first terminal of the ninth transistor M9 can be output to the second terminal of the ninth transistor M9, that is, output to the control terminal of the tenth transistor M10. Thus, the tenth transistor M10 can be turned on or off accordingly based on the conversion between the fourth voltage signal V4 and the fifth voltage signal V5. The fourth voltage signal V4 has the same potential as the invalid pulse of the second output signal SN_OUT. For example, if the invalid pulse of the second output signal SN_OUT can be a low-level signal VGL, then the fourth voltage signal V4 can be a low-level signal VGL. The fifth voltage signal V5 has the same potential as the valid pulse of the second output signal SN_OUT. For example, if the valid pulse of the second output signal SN_OUT can be a high-level signal VGH, then the fifth voltage signal V5 can be a high-level signal VGH.Furthermore, the first terminal of the tenth transistor M10 receives the seventh voltage signal V7, and the second terminal of the tenth transistor M10 is electrically connected to the second plate of the fourth capacitor C4. The second terminal of the tenth transistor M10 can also output a second output signal SN_OUT. That is, when the tenth transistor M10 is turned on, the seventh voltage signal V7 at the first terminal of the tenth transistor M10 can be output to the second terminal of the tenth transistor M10, thereby causing the second output signal SN_OUT to be output. When the tenth transistor M10 is turned off, the second terminal of the tenth transistor M10 is electrically connected to the second plate of the fourth capacitor C4, and the level signal at the control terminal of the tenth transistor M10 stored in the fourth capacitor C4 can also be released, causing the second output signal SN_OUT to be output. The seventh voltage signal V7 and the invalid pulse of the second output signal SN_OUT have the same potential. For example, if the invalid pulse of the second output signal SN_OUT can be a low-level signal VGL, then the seventh voltage signal V7 can be a low-level signal VGL.

[0178] In one specific embodiment, optionally, continuing to refer to FIG25, the first voltage signal V1, the fourth voltage signal V4, the sixth voltage signal V6, and the seventh voltage signal V7 are signals with the same potential; the fifth voltage signal V5 and the second voltage signal V2 are signals with the same potential. In another specific embodiment, optionally, continuing to refer to FIG25, at least two of the fourth voltage signal V4, the sixth voltage signal V6, and the seventh voltage signal V7 are voltage signals with the same potential.

[0179] This embodiment essentially multiplexes at least two high-level signals or at least two low-level signals, thereby saving the number of high-level or low-level signal lines, which facilitates wiring arrangement, simplifies the circuit structure of the shift register 110, and reduces the complexity of the shift register 110. For example, the first voltage signal V1, the fourth voltage signal V4, the sixth voltage signal V6, and the seventh voltage signal V7 can all be low-level signals VGL, and the fifth voltage signal V5 and the second voltage signal V2 can both be high-level signals VGH.

[0180] Figure 26 is a timing diagram of a drive for the second control unit in the shift register shown in Figure 25. Referring to Figures 25 and 26, the working principle and process of the second control unit 20 in the shift register according to an embodiment of this application will be described below:

[0181] In Figure 26, the effective pulses of the first output signal SN_NEXT1 and the second output signal SN_OUT are both at a high level, and the invalid pulses are both at a low level. The effective pulses of the frequency control signal SN_CTRL are at a low level, and the invalid pulses are at a high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. The first voltage signal V1 is a low level signal VGL, the second voltage signal V2 is a high level signal VGH, the third voltage signal V3 is a high level signal VGH, the fixed voltage signal V' is a high level signal VGH, the fourth voltage signal V4 is a low level, the fifth voltage signal V5 is a high level, the sixth voltage signal V6 is a low level, and the seventh voltage signal V7 is a low level.

[0182] During stage Tn, the first output signal SN_NEXT1 is low and has no rising edge. The frequency control signal SN_CTRL is high. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, with the first node N1 low, the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, thereby turning off the fourth transistor M4. Furthermore, the third voltage signal V3 is transmitted to the control terminals of the sixth transistor M6 and the eighth transistor M8 through the fifth transistor M5, respectively, turning off the sixth transistor M6 and the eighth transistor M8. Furthermore, the ninth transistor M9 is normally open (the sixth voltage signal V6 at the control terminal of the ninth transistor M9 is always a low-level signal VGL). The fourth voltage signal V4 is transmitted sequentially through the seventh transistor M7 and the ninth transistor M9 to the control terminal of the tenth transistor M10, causing the tenth transistor M10 to conduct, further keeping the second output signal SN_OUT low. At this time, the fourth capacitor C4 can store the low-level signal VGL of the fourth voltage signal V4, and / or, the fourth capacitor C4 can store the low-level signal VGL of the seventh voltage signal V7.

[0183] During the To phase, the first output signal SN_NEXT1 is high, and it has a rising edge. The frequency control signal SN_CTRL is also high. At this time, the first node N1 is high, and the first transistor M1, the second transistor M2, and the fifth transistor M5 are all off. The potential signal of the frequency control signal SN_CTRL stored at the second capacitor C2 still causes the fourth transistor M4 to be off. Simultaneously, the third voltage signal V3 stored at the third capacitor C3 causes the sixth transistor M6 to be off. Therefore, the level of the second output signal SN_OUT is floated at the low level of the Tk phase. Furthermore, with the first node N1 high, the fifth transistor M5 and the seventh transistor M7 are off, the ninth transistor M9 is normally open, and the low-level signal VGL stored at the fourth capacitor C4 can be released to the output terminal, keeping the second output signal SN_OUT low. This further ensures that the low level of the second output signal SN_OUT will not drift, preventing an abnormally high output level of the second output signal SN_OUT.

[0184] During the Tp phase, the first output signal SN_NEXT1 is low and has no rising edge. The frequency control signal SN_CTRL is high. At this time, the first node N1 is low, the first transistor M1 is turned on, and the first voltage signal V1 is transmitted to the output terminal through the first transistor M1, causing the second output signal SN_OUT to be low. Simultaneously, with the first node N1 low, the second transistor M2 and the fifth transistor M5 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, which in turn turns on the fourth transistor M4. Furthermore, the third voltage signal V3 is transmitted to the control terminal of the sixth transistor M6 through the fifth transistor M5 (or, due to the third node N3 being high), the sixth transistor M6 is turned off. Furthermore, when the first node N1 is low, the second transistor M2, the fifth transistor M5, and the seventh transistor M7 are turned on. The frequency control signal SN_CTRL is transmitted to the second node N2 through the second transistor M2, thereby turning off the fourth transistor M4. The third voltage signal V3 is transmitted to the control terminals of the sixth transistor M6 and the eighth transistor M8 through the fifth transistor M5, respectively, turning off the sixth transistor M6 and the eighth transistor M8. The ninth transistor M9 is normally open (the sixth voltage signal V6 at the control terminal of the ninth transistor M9 is always a low-level signal VGL). The fourth voltage signal V4 is transmitted sequentially through the seventh transistor M7 and the ninth transistor M9 to the control terminal of the tenth transistor M10, turning on the tenth transistor M10 and further keeping the second output signal SN_OUT low. At this time, the fourth capacitor C4 can store the low-level signal VGL of the fourth voltage signal V4, and / or, the fourth capacitor C4 can store the low-level signal VGL of the seventh voltage signal V7.

[0185] The previous embodiment showed the internal structure of the second control unit 20 in the shift register 110 and the working principle of outputting the second output signal SN_OUT according to the first output signal SN_NEXT1 and the frequency control signal SN_CTRL of the first control unit 10. The internal structure of the first control unit 10 and the working principle of controlling the first output signal SN_NEXT1 are described below.

[0186] Optionally, referring to Figures 19, 22, and 25, the first control unit 10 includes a fifth control unit 11, a sixth control unit 12, and a seventh control unit 13. The fifth control unit 11 is configured to receive a first input signal SN_IN1, an eighth voltage signal V8, a ninth voltage signal V9, and a clock signal CK, and control the potential of the fourth node N4 and the fifth node N5. One end of the sixth control unit 12 receives a tenth voltage signal V10, and the other end of the sixth control unit 12 is configured to output a first output signal SN_NEXT1. The control terminal of the sixth control unit 12 is electrically connected to the fourth node N4. One end of the seventh control unit 13 receives an eleventh voltage signal V11, and the other end of the seventh control unit 13 is configured to output the first output signal SN_NEXT1. The control terminal of the seventh control unit 13 is electrically connected to the fifth node N5. One of the eighth voltage signal V8 and the ninth voltage signal V9 is a high-level signal VGH, and the other is a low-level signal VGL. One of the tenth voltage signal V10 and the eleventh voltage signal V11 is a high-level signal VGH, and the other is a low-level signal VGL.

[0187] For example, the fifth control unit 11 can receive the first input signal SN_IN1, the eighth voltage signal V8, the ninth voltage signal V9, and the clock signal CK, and control the potential of the fourth node N4 and the fifth node N5, so as to determine whether the first output signal SN_NEXT1 is a valid pulse or an invalid pulse based on the potential of the fourth node N4 and the fifth node N5. The control terminal of the sixth control unit 12 is electrically connected to the fourth node N4. One end of the sixth control unit 12 receives the tenth voltage signal V10, and the other end of the sixth control unit 12 is set to output the first output signal SN_NEXT1. That is, when the sixth control unit 12 is turned on, the tenth voltage signal V10 at one end of the sixth control unit 12 is output to the other end of the sixth control unit 12 to form the output of the first output signal SN_NEXT1. At this time, the potential signal output by the first output signal SN_NEXT1 is the same as that of the tenth voltage signal V10. The control terminal of the seventh control unit 13 is electrically connected to the fifth node N5. One end of the seventh control unit 13 receives the eleventh voltage signal V11, and the other end of the seventh control unit 13 is set to output the first output signal SN_NEXT1. That is, when the seventh control unit 13 is turned on, the eleventh voltage signal V11 at one end of the seventh control unit 13 is output to the other end of the seventh control unit 13 to form the output of the first output signal SN_NEXT1. At this time, the potential signal output by the first output signal SN_NEXT1 is the same as the eleventh voltage signal V11.

[0188] One of the eighth voltage signal V8 and the ninth voltage signal V9 is a high-level signal VGH, and the other is a low-level signal VGL. It can be understood that the eighth voltage signal V8 and the ninth voltage signal V9 participate in the control process of the second output signal SN_OUT outputting a valid pulse or an invalid pulse, respectively. For example, VGH is the voltage value of the high-level signal in the eighth voltage signal V8 and the ninth voltage signal V9, and VGL is the voltage value of the low-level signal in the eighth voltage signal V8 and the ninth voltage signal V9. Therefore, by controlling the output of the eighth voltage signal V8 and the ninth voltage signal V9, the switching between the high-level signal and the low-level signal of the second output signal SN_OUT, that is, the switching between valid pulses and invalid pulses, can be realized. Similarly, one of the tenth voltage signal V10 and the eleventh voltage signal V11 is a high-level signal VGH, and the other is a low-level signal VGL. It can be understood that the tenth voltage signal V10 and the eleventh voltage signal V11 participate in the control process of the second output signal SN_OUT outputting a valid pulse or an invalid pulse, respectively. For example, VGH is the voltage value of the high-level signal in the tenth voltage signal V10 and the eleventh voltage signal V11, and VGL is the voltage value of the low-level signal in the tenth voltage signal V10 and the eleventh voltage signal V11. Therefore, by controlling the output of the tenth voltage signal V10 and the eleventh voltage signal V11, the switching between the high-level and low-level signals of the second output signal SN_OUT, that is, the switching between valid pulses and invalid pulses, can be realized.

[0189] Optionally, referring to Figures 19, 22 and 25, the eighth voltage signal V8 and the tenth voltage signal V10 are voltage signals at the same potential; the ninth voltage signal V9 and the eleventh voltage signal V11 are voltage signals at the same potential.

[0190] This embodiment essentially multiplexes at least two high-level signals or at least two low-level signals, thereby saving the number of high-level or low-level signal lines, which facilitates wiring arrangement, simplifies the circuit structure of the shift register 110, and reduces the complexity of the shift register 110. For example, the eighth voltage signal V8 and the tenth voltage signal V10 can both be low-level signals VGH, and the ninth voltage signal V9 and the eleventh voltage signal V11 can both be high-level signals VGL.

[0191] Optionally, continuing to refer to Figures 19, 22, and 25, the fifth control unit 11 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a fifth capacitor C5; the first terminal of the eleventh transistor M11 is electrically connected to the control terminal of the twelfth transistor M12 and receives the first input signal SN_IN1; the control terminal of the eleventh transistor M11, the first plate of the fifth capacitor C5, and the first terminal of the thirteenth transistor M13 are electrically connected to receive the clock signal CK; the second terminal of the eleventh transistor M11 is respectively connected to the tenth transistor M14, the twelfth transistor M15, the thirteenth transistor M15, and the thirteenth transistor C5. The first terminal of transistor M14 is electrically connected to the control terminal of transistor M15; the first terminal of transistor M12 is electrically connected to the second plate of capacitor C5 and the control terminal of transistor M13, respectively; the second terminal of transistor M12 is electrically connected to the first terminal of transistor M15 and receives the eighth voltage signal V8; the second terminals of transistors M13 and M15 are both electrically connected to the fourth node N4; the second terminal of transistor M14 is electrically connected to the fifth node N5; the control terminal of transistor M14 receives the ninth voltage signal V9.

[0192] For example, any one of the eleventh transistor M11, twelfth transistor M12, thirteenth transistor M13, fourteenth transistor M14, and fifteenth transistor M15 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. For example, the control terminal of the eleventh transistor M11 receives the clock signal CK, the first terminal of the eleventh transistor M11 receives the first input signal SN_IN1, and the second terminal of the eleventh transistor M11 is electrically connected to the first terminal of the fourteenth transistor M14 and the control terminal of the fifteenth transistor M15, respectively. That is, when the eleventh transistor M11 is turned on, the first input signal SN_IN1 at the first terminal of the eleventh transistor M11 can be output to the first terminal of the fourteenth transistor M14, and at the same time, the first input signal SN_IN1 at the first terminal of the eleventh transistor M11 can be output to the control terminal of the fifteenth transistor M15. The control terminal of the twelfth transistor M12 receives the first input signal. The first terminal of the twelfth transistor M12 is electrically connected to the second plate of the fifth capacitor C5. The second terminal of the twelfth transistor M12 receives the eighth voltage signal V8. That is, when the twelfth transistor M12 is turned on, the eighth voltage signal V8 at the second terminal of the twelfth transistor M12 can be output to the first terminal of the twelfth transistor M12. At the same time, the fifth capacitor C5 can store the eighth voltage signal V8. The control terminal of the thirteenth transistor M13 is electrically connected to the first terminal of the twelfth transistor M12 and the second plate of the fifth capacitor C5. The first terminal of the thirteenth transistor M13 receives the clock signal CK. The second terminal of the thirteenth transistor M13 is electrically connected to the fourth node N4. That is, when the thirteenth transistor M13 is turned on, the eighth voltage signal V8 stored in the fifth capacitor C5 can be output to the fourth node N4 to facilitate the subsequent output of the first output signal SN_NEXT1. The control terminal of the fourteenth transistor M14 receives the ninth voltage signal V9. The first terminal of the fourteenth transistor M14 is electrically connected to the second terminal of the eleventh transistor M11. The second terminal of the fourteenth transistor M14 is electrically connected to the fifth node N5. That is, when the fourteenth transistor M14 is turned on, the potential signal at the second terminal of the eleventh transistor M11 can be output to the fifth node N5 so as to facilitate the subsequent output of the first output signal SN_NEXT1.

[0193] Optionally, continuing to refer to Figures 19, 22 and 25, the sixth control unit 12 includes a sixteenth transistor M16 and a sixth capacitor C6; the control terminal of the sixteenth transistor M16 and the first plate of the sixth capacitor C6 are both electrically connected to the fourth node N4, the first terminal of the sixteenth transistor M16 and the second plate of the sixth capacitor C6 are electrically connected and receive the tenth voltage signal V10, and the second terminal of the sixteenth transistor M16 outputs the first output signal SN_NEXT1.

[0194] For example, the sixteenth transistor M16 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. For example, the sixteenth transistor M16 can be a P-type transistor. The gate of the sixteenth transistor M16 is electrically connected to the fourth node N4. The source of the sixteenth transistor M16 receives the tenth voltage signal V10. The drain of the sixteenth transistor M16 outputs the first output signal SN_NEXT1. The two ends of the sixth capacitor C6 are connected between the gate and the source of the sixteenth transistor M16, so that a voltage difference is formed between the gate and the source of the sixteenth transistor M16. This voltage difference is lower than the threshold voltage of the sixteenth transistor M16, thereby ensuring that the sixteenth transistor M16 is in the conducting state.

[0195] Optionally, continuing to refer to Figures 19, 22, and 25, the seventh control unit 13 includes a seventeenth transistor M17 and a seventh capacitor C7; the control terminal of the seventeenth transistor M17 and the first plate of the seventh capacitor C7 are both electrically connected to the fifth node N5; the first terminal of the seventeenth transistor M17 receives the eleventh voltage signal V11; and the second terminal of the seventeenth transistor M17 is electrically connected to the second plate of the seventh capacitor C7 and outputs the first output signal SN_NEXT1.

[0196] For example, the seventeenth transistor M17 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. For example, the seventeenth transistor M17 can be a P-type transistor. The gate of the seventeenth transistor M17 is electrically connected to the fifth node N5. The source of the seventeenth transistor M17 receives the eleventh voltage signal V11. The drain of the seventeenth transistor M17 outputs the first output signal SN_NEXT1. The two ends of the seventh capacitor C7 are connected between the gate and the source of the seventeenth transistor M17, so that a voltage difference is formed between the gate and the source of the seventeenth transistor M17. This voltage difference is lower than the threshold voltage of the seventeenth transistor M17, thereby ensuring that the seventeenth transistor M17 is in the conducting state.

[0197] Furthermore, the first node N1 in the first control unit 10 can be the node where the sixteenth transistor M16 and the seventeenth transistor M17 are electrically connected, as illustrated in Figures 19, 22, and 25. The first node N1 can also be the fourth node N4 (the potential signals output by the first node N1 and the fourth node N4 are the same), or the first node N1 can be the fifth node N5 (the potential signals output by the first node N1 and the fifth node N5 are the same). In this embodiment, the first node N1 is illustrated as the node where the sixteenth transistor M16 and the seventeenth transistor M17 are electrically connected. In practice, it can also include schematic diagrams of the electrical connection relationships of other first nodes N1.

[0198] Figure 27 is a timing diagram of the drive of the first control unit in a shift register according to an embodiment of this application. The working principle and process of the first control unit 10 in the shift register according to an embodiment of this application will be described below with reference to Figures 19, 22, 25, and 27:

[0199] In Figure 27, the effective pulses of the first input signal SN_IN1, the clock signal CK, and the first output signal SN_NEXT1 are all at a high level, and the invalid pulses are all at a low level. In addition, the eighth voltage signal V8 and the tenth voltage signal V8 are both at a high level (VGH), and the ninth voltage signal V9 and the eleventh voltage signal V11 are both at a low level (VGL).

[0200] During the Tq phase, the first input signal SN_IN1 is low and the clock signal CK is low. At this time, the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the fourteenth transistor M14 is normally open (the ninth voltage signal V9 at the control terminal of the fourteenth transistor M14 is always low). The first input signal SN_IN1 is transmitted to the fifth node N5 through the eleventh transistor M11 and the fourteenth transistor M14 in sequence. The fifth node N5 is low, so the seventeenth transistor M17 is turned on. The eleventh voltage signal V11 is transmitted to the first output signal SN_NEXT1 through the seventeenth transistor M17, making the first output signal SN_NEXT1 low, that is, the first node N1 is low. Simultaneously, the eighth voltage signal V8 is transmitted to the thirteenth transistor M13 through the twelfth transistor M12, causing the thirteenth transistor M13 to turn off. The first input signal SN_IN1 is transmitted to the fifteenth transistor M15 through the eleventh transistor M11, causing the fifteenth transistor M15 to turn on. The eighth voltage signal V8 is also transmitted to the third node N3 through the fifteenth transistor M15, causing the third node N3 to be at a high level, thereby turning off the sixteenth transistor M16.

[0201] During the Tr phase, the first input signal SN_IN1 is low, and the clock signal CK is high. At this time, the twelfth transistor M12 is turned on, the fourteenth transistor M14 is normally open, and the potential signal of the fourth node N4 is floated at the low level of the Tq phase. Then, the fifteenth transistor M15 and the seventeenth transistor M17 are turned on, and the eleventh voltage signal V11 is transmitted to the first output signal SN_NEXT1 through the seventeenth transistor M17, making the first output signal SN_NEXT1 low, that is, the first node N1 is low. In addition, the eighth voltage signal V8 is also transmitted to the third node N3 through the fifteenth transistor M15, making the third node N3 high, and thus the sixteenth transistor M16 is turned off.

[0202] During the Ts phase, the first input signal SN_IN1 is high, and the clock signal CK is high. At this time, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are off, the fourteenth transistor M14 is normally on, and the potential signal of the fourth node N4 is floated at the low level of the Tr phase. Then, the fifteenth transistor M15 and the seventeenth transistor M17 are turned on, and the eleventh voltage signal V11 is transmitted to the first output signal SN_NEXT1 through the seventeenth transistor M17, making the first output signal SN_NEXT1 low, that is, the first node N1 is low. In addition, the eighth voltage signal V8 is also transmitted to the third node N3 through the fifteenth transistor M15, making the third node N3 high, and thus the sixteenth transistor M16 is turned off.

[0203] During the Tt phase, the first input signal SN_IN1 is high, and the clock signal CK is low. At this time, the twelfth transistor M12 is off, the eleventh transistor M11 and the thirteenth transistor M13 are on, and the fourteenth transistor M14 is normally open. The first input signal SN_IN1 is transmitted to the fifteenth transistor M15 through the eleventh transistor M11, causing the fifteenth transistor M15 to turn off. Simultaneously, the first input signal SN_IN1 is transmitted to the seventeenth transistor M17 through the eleventh transistor M11 and the fourteenth transistor M14, causing the seventeenth transistor M17 to turn off. Furthermore, the clock signal CK is transmitted to the third node N3 through the fifteenth transistor M15, causing the third node N3 to go low. Consequently, the sixteenth transistor M16 turns on, and the tenth voltage signal V10 is transmitted to the first output signal SN_NEXT1 through the sixteenth transistor M16, causing the first output signal SN_NEXT1 to go high, which means the first node N1 is high.

[0204] During the Tu phase, the first input signal SN_IN1 is high, and the clock signal CK is high. At this time, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are off, the fourteenth transistor M14 is normally on, and the potential signal of the fourth node N4 is floated at the high level of the Tt phase, so the fifteenth transistor M15 and the seventeenth transistor M17 are off. Meanwhile, the potential signal of the third node N3 is floated at the low level of the Tt phase, so the sixteenth transistor M16 is turned on, and the tenth voltage signal V10 is transmitted to the first output signal SN_NEXT1 through the sixteenth transistor M16, making the first output signal SN_NEXT1 high, which also means that the first node N1 is high.

[0205] During the Tv phase, the first input signal SN_IN1 is low, and the clock signal CK is high. At this time, the twelfth transistor M12 is turned on, the eleventh transistor M11 and the thirteenth transistor M13 are turned off, the fourteenth transistor M14 is normally open, and the potential signal of the fourth node N4 is floated at the high level of the Tu phase, so the fifteenth transistor M15 and the seventeenth transistor M17 are turned off. Also, the potential signal of the third node N3 is floated at the low level of the Tu phase, so the sixteenth transistor M16 is turned on, and the tenth voltage signal V10 is transmitted to the first output signal SN_NEXT1 through the sixteenth transistor M16, making the first output signal SN_NEXT1 high, which also means that the first node N1 is high.

[0206] Furthermore, referring to Figure 27, the potential signals of the fourth node N4 and the fifth node N5 are simultaneously identical to the potential signal of the first output signal SN_NEXT1. Therefore, the fourth node N4 can be reused as the first node N1 as defined in this application, and the fifth node N5 can also be reused as the first node N1 as defined in this application, which is consistent with the meaning that the potential of the first node N1 is synchronized with the first output signal SN_NEXT1 as defined in this application. Also, the potential signal of the third node N3 is simultaneously opposite to the potential signal of the first output signal SN_NEXT1, which is consistent with the meaning that the potential of the third node N3 is out of phase with the first output signal SN_NEXT1 as defined in this application.

[0207] Optionally, Figure 28 is a schematic diagram of the circuit structure of another shift register provided in an embodiment of this application, and Figure 29 is a timing diagram of another driving phase of the multi-stage shift register in the driving circuit shown in Figure 3. As shown in Figures 28 and 29, the first control unit 10 is further configured to control the third output signal SN_NEXT2. The third output signal SN_NEXT2 of the i-th stage shift register 110 is the second input signal SN_IN2 of the j-th stage shift register 110. Within a preset duration, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse, and a second valid pulse that are sequentially adjacent. During the time period of the effective pulse and the second effective pulse, the third output signal SN_NEXT2 is an effective pulse, and the voltage edge of the third output signal SN_NEXT2 transitioning from an invalid level to an effective level is synchronized with the voltage edge of the first effective pulse transitioning from an invalid level to an effective level; the voltage edge of the third output signal SN_NEXT2 transitioning from an effective level to an invalid level is synchronized with the voltage edge of the second effective pulse transitioning from an effective level to an invalid level; the second control unit 20 receives the potential signal of the first node N1, the frequency control signal SN_CTRL and the third output signal SN_NEXT2, and controls the second output signal SN_OUT.

[0208] In one specific embodiment, the first output signal SN_NEXT1 can be exemplified as the DVH signal of the bias adjustment module, which requires bias adjustment of the driving transistor both before and after the data writing phase. Thus, before and after the data writing phase, the first output signal SN_NEXT1 needs to output two adjacent valid pulse signals to ensure the bias adjustment of the driving transistor. That is, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse, and a second valid pulse that are sequentially adjacent. To avoid the second valid pulse being unable to output when the corresponding frequency control signal SN_CTRL is invalid during the voltage edge of the second valid pulse transitioning from invalid to valid level, thus preventing the formation of the corresponding second output signal SN_OUT, a third output signal SN_NEXT2 needs to be additionally set. The voltage edge of the third output signal SN_NEXT2 transitioning from invalid to valid level is limited to being synchronized with the voltage edge of the first valid pulse transitioning from invalid to valid level; the voltage edge of the third output signal SN_NEXT2 transitioning from valid to invalid level is also limited to being synchronized with the voltage edge of the second valid pulse transitioning from valid to invalid level.

[0209] Optionally, continuing to refer to FIG28, the first control unit 10 includes an eighth control unit 14, which is configured to receive a second input signal SN_IN2, a twelfth voltage signal V12 and a clock signal CK, and control a third output signal SN_NEXT2; wherein, the twelfth voltage signal V12 has the same potential as the invalid pulse of the third output signal SN_NEXT2.

[0210] The eighth control unit 14 can receive the second input signal SN_IN2, the twelfth voltage signal V12, and the clock signal CK, and control the output of the third output signal SN_NEXT2. For example, the invalid pulses of the twelfth voltage signal V12 and the third output signal SN_NEXT2 can both be the low-level signal VGL.

[0211] Optionally, continuing to refer to Figure 28, the eighth control unit 14 includes an eighteenth transistor M18 and an eighth capacitor C8; the first terminal of the eighteenth transistor M18 receives the second input signal SN_IN2, the second terminal of the eighteenth transistor M18 is electrically connected to the first plate of the eighth capacitor C8 and outputs the third output signal SN_NEXT2; the second plate of the eighth capacitor C8 receives the twelfth voltage signal V12.

[0212] For example, the eighteenth transistor M18 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal corresponding to its control terminal is a low-level signal, and the invalid pulse is a high-level signal. For example, the eighteenth transistor M18 can be a P-type transistor. The gate of the eighteenth transistor M18 is electrically connected to the clock signal CK. The source of the eighteenth transistor M18 receives the second input signal SN_IN2. The drain of the eighteenth transistor M18 outputs the third output signal SN_NEXT2. The two ends of the eighth capacitor C8 are connected between the third output signal SN_NEXT2 and the twelfth voltage signal V12, making the third output signal SN_NEXT2 more stable.

[0213] Optionally, continuing to refer to Figures 28 and 29, the first control unit 10 further includes a sixth node N6, the potential signal output of the sixth node N6 is the third output signal SN_NEXT2, and the third output signal SN_NEXT2 of the i-th stage shift register 110 is the second input signal SN_IN2 of the j-th stage shift register 110; within a preset time range, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse, and a second valid pulse that are sequentially adjacent; within the time period of the first valid pulse, the first invalid pulse, and the second valid pulse, the third output signal SN_NEXT2 is a valid pulse, and the voltage edge of the third output signal SN_NEXT2 transitioning from invalid to valid level is synchronized with the voltage edge of the first valid pulse transitioning from invalid to valid level; the voltage edge of the third output signal SN_NEXT2 transitioning from valid to valid level is synchronized with the voltage edge of the first valid pulse transitioning from invalid to valid level; the voltage edge of the third output signal SN_NEXT2 transitioning from invalid to valid level is synchronized with the voltage edge of the first valid pulse transitioning from invalid to valid level; the voltage edge of the third output signal SN_NEXT2 transitioning from invalid to valid level is synchronized with the voltage edge of the first valid pulse transitioning from invalid to valid level. The voltage edge of the flat invalid level transition is synchronized with the voltage edge of the second valid pulse transitioning from valid level to invalid level; the second control unit 20 includes a first control unit 21, a second control unit 22, a third control unit 23, and a second node N2; the first control unit 21 receives the potential signal and the first voltage signal V1 of the first node N1, and is configured to control the output of the second output signal SN_OUT as an invalid pulse; the second control unit 22 receives the potential signal and the frequency control signal SN_CTRL of the sixth node N6, and is configured to control the potential of the second node N2; the third control unit 23 receives at least the potential signal and the second voltage signal V2 of the second node N2, and is configured to control the output of the second output signal SN_OUT as a valid pulse; one of the first voltage signal V1 and the second voltage signal V2 is a high-level signal VGH, and the other is a low-level signal VGL.

[0214] In one specific embodiment, the first output signal SN_NEXT1 can be exemplified as the DVH signal of the bias adjustment module, which requires bias adjustment of the driving transistor both before and after the data writing phase. Thus, before and after the data writing phase, the first output signal SN_NEXT1 needs to output two adjacent valid pulse signals to ensure the bias adjustment of the driving transistor. That is, the first output signal SN_NEXT1 includes a first valid pulse, a first invalid pulse, and a second valid pulse that are sequentially adjacent. To avoid the second valid pulse being unable to output when the corresponding frequency control signal SN_CTRL is invalid during the voltage edge of the second valid pulse transitioning from invalid to valid level, thus preventing the formation of the corresponding second output signal SN_OUT, a third output signal SN_NEXT2 needs to be additionally set. The voltage edge of the third output signal SN_NEXT2 transitioning from invalid to valid level is limited to being synchronized with the voltage edge of the first valid pulse transitioning from invalid to valid level; the voltage edge of the third output signal SN_NEXT2 transitioning from valid to invalid level is also limited to being synchronized with the voltage edge of the second valid pulse transitioning from valid to invalid level.

[0215] The sixth node N6 can be understood as the connection point that establishes the electrical connection between the first control unit 10 and the second control unit 20. Meanwhile, the second control unit 20 includes a first control unit 21, a second control unit 22, and a third control unit 23. The first control unit 21 receives the potential signal and the first voltage signal V1 from the first node N1; that is, under the control of the potential signal and the first voltage signal V1 of the first node N1, the second output signal SN_OUT can be output as an invalid pulse. The second node N2 can be understood as the node controlled by the second control unit 22, and also the node that controls the output of the third control unit 23. Under the control of the potential signal and the frequency control signal SN_CTRL of the sixth node N6, the potential of the second node N2 can change, thereby changing the output potential of the third control unit 23, which is controlled by the potential signal and the second voltage signal V2 of the second node N2, generating the second output signal SN_OUT, so that the second output signal SN_OUT can be output as a valid pulse. It is understandable that the first voltage signal V1 participates in the control process of the second output signal SN_OUT outputting invalid pulses, and the second voltage signal V2 participates in the control process of the second output signal SN_OUT outputting valid pulses. For example, VGH is the voltage value of the high-level signal in the first voltage signal V1 and the second voltage signal V2, and VGL is the voltage value of the low-level signal in the first voltage signal V1 and the second voltage signal V2. Therefore, by controlling the output of the first voltage signal V1 or the second voltage signal V2, the switching between the high-level signal and the low-level signal of the second output signal SN_OUT, that is, the switching between valid pulses and invalid pulses, can be realized.

[0216] For example, the potential signal of the first node N1 is synchronized with the first output signal SN_NEXT1. The first control unit 21 can be set to turn on when the first output signal SN_NEXT1 is a valid pulse and turn off when the first output signal SN_NEXT1 is an invalid pulse. The first control unit 21 shown in Figure 28 includes a first transistor M1, for example, a P-type transistor. At this time, a valid pulse of the first output signal SN_NEXT1 is a low-level signal, and an invalid pulse is a high-level signal; that is, when the first output signal SN_NEXT1 is a low-level signal, the first transistor M1 in the first control unit 21 is turned on; when the first output signal SN_NEXT1 is a high-level signal, the first transistor M1 in the first control unit 21 is turned off.

[0217] At this time, the first output signal SN_NEXT1 is essentially a control signal for the first control unit 21, connected to the control terminal of the first control unit 21. The first output signal SN_NEXT1 controls the first control unit 21 to be turned on or off. Optionally, when the first control unit 21 is turned on, the level signal corresponding to the first voltage signal V1 can be used to generate the second output signal SN_OUT. At this time, the second output signal SN_OUT outputs an invalid pulse. For example, the invalid pulses of the first voltage signal V1 and the second output signal SN_OUT can both be low-level signals VGL.

[0218] Similarly, the second control unit 22 can be turned on when the potential signal of the sixth node N6 is a valid pulse, and turned off when the potential signal of the sixth node N6 is an invalid pulse. At this time, the third output signal SN_NEXT2 is essentially a control signal for the second control unit 22, connected to the control terminal of the second control unit 22, and controls the on / off state of the second control unit 22 through the third output signal SN_NEXT2. Optionally, when the second control unit 22 is turned on, the level signal corresponding to the frequency control signal SN_CTRL can be used to generate the potential signal of the second node N2.

[0219] Subsequently, the third control unit 23 can be turned on when the potential signal of the second node N2 is a valid pulse, and turned off when the potential signal of the second node N2 is an invalid pulse. At this time, the potential signal of the second node N2 is essentially the control signal of the third control unit 23, connected to the control terminal of the third control unit 23, and the conduction or deactivation of the third control unit 23 is controlled by the potential signal of the second node N2. Optionally, when the third control unit 23 is turned on, the level signal corresponding to the second voltage signal V2 can be used to generate the second output signal SN_OUT, and at this time the second output signal SN_OUT outputs a valid pulse. For example, the valid pulses of the second voltage signal V2 and the second output signal SN_OUT can both be high-level signals VGH.

[0220] Optionally, referring to Figures 28 and 29, the second control unit 22 includes a second transistor M2 and a second capacitor C2; the control terminal of the second transistor M2 is electrically connected to the sixth node N6, the first terminal of the second transistor M2 receives the frequency control signal SN_CTRL, the second terminal of the second transistor M2 is electrically connected to the first plate of the second capacitor C2 and the second node N2 respectively, and the second plate of the second capacitor C2 receives the fixed potential signal V'.

[0221] For example, the second transistor M2 can be configured as a P-type transistor. In this case, the effective pulse of the potential signal at the sixth node N6 is a low-level signal, and the invalid pulse is a high-level signal. For example, the first terminal of the second transistor M2 receives the frequency control signal SN_CTRL, and the second terminal of the second transistor M2 is electrically connected to the second node N2. That is, when the second transistor M2 is turned on, the potential signal of the frequency control signal SN_CTRL can be generated at the second node N2. Simultaneously, the second terminal of the second transistor M2 is electrically connected to the second capacitor C2, which can also store the potential signal of the frequency control signal SN_CTRL. When the second transistor M2 is turned off, the potential signal of the frequency control signal SN_CTRL stored in the second capacitor C2 can be released to the second node N2, so that the second node N2 remains floating with the potential signal of the frequency control signal SN_CTRL. When the second transistor M2 is turned off, regardless of whether the frequency control signal SN_CTRL at the first terminal of the second transistor M2 is an effective pulse or an invalid pulse, the potential signal at the second terminal of the second transistor M2 remains the potential signal of the frequency control signal SN_CTRL. The function of the second transistor M2 is to write the frequency control signal SN_CTRL to the second node N2 after a complete pulse signal is output from the sixth node N6. This prevents the sixth node N6 from outputting a valid pulse when the frequency control signal SN_CTRL changes, thus avoiding an incomplete second output signal SN_OUT. In other words, the configuration of the second transistor M2 and the second capacitor C2 is fundamental to solving the problem of incomplete pulse signal output caused by the truncation of the potential signal at the second node N2 by the frequency control signal SN_CTRL, thereby resolving the issue of incomplete pulse signal output caused by the truncation of the valid pulse of the second output signal SN_OUT by the frequency control signal SN_CTRL.

[0222] As shown in Figure 29, the effective pulses of the first output signal SN_NEXT1_m, the third output signal SN_NEXT2_m, and the second output signal SN_OUT are all at a high level, and the invalid pulses are all at a low level. Meanwhile, the effective pulse of the frequency control signal SN_CTRL is at a low level, and the invalid pulses are all at a high level. The first voltage edge of the first output signal SN_NEXT1 is the rising edge. Taking the first output signal SN_NEXT1_m and the third output signal SN_NEXT2_m of the m-th stage shift register 110 as an example, in this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting the first effective pulse when the first voltage edge (rising edge) of the first effective pulse of the first output signal SN_NEXT1 overlaps with the effective pulse (low level) of the frequency control signal SN_CTRL, and when the first voltage edge (rising edge) of the third output signal SN_NEXT2 is synchronized with the rising edge of the first effective pulse of the first output signal SN_NEXT1, forming the second output signal SN_OUT (high level). Subsequently, after the first valid pulse of the first output signal SN_NEXT1 is output, during the output of the first invalid pulse and the second valid pulse, when the falling edge of the third output signal SN_NEXT2 is synchronized with the falling edge of the second valid pulse of the first output signal SN_NEXT1, the second control unit 20 outputs a second valid pulse, forming the second output signal SN_OUT (high level). In this embodiment, the frequency control signal SN_CTRL and the second control unit 20 are responsible for controlling the time period corresponding to the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 to be completely within the valid pulse (low level) time period of the frequency control signal SN_CTRL, and the time period corresponding to the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 and the time period corresponding to the falling edge of the second valid pulse to be completely within the valid pulse (high level) time period of the third output signal SN_NEXT2, thereby forming two consecutive valid pulses (high level) output of the second output signal SN_OUT.

[0223] Taking the first output signal SN_NEXT1_n and the third output signal SN_NEXT2_n of the nth stage shift register 110 as an example, in this embodiment of the application, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse to form the second output signal SN_OUT (low level) when the first voltage edge (rising edge) of the first valid pulse of the first output signal SN_NEXT1 overlaps with the invalid pulse (high level) of the frequency control signal SN_CTRL. Furthermore, taking the first output signal SN_NEXT1_y and the third output signal SN_NEXT2_y of the y-th stage shift register 110 as examples, in this embodiment of the application, the frequency control signal SN_CTRL and the second control unit 20 are responsible for outputting an invalid pulse when the first output signal SN_NEXT1 is an invalid pulse (low level), that is, when the first output signal SN_NEXT1 has no first voltage edge, to form the second output signal SN_OUT (low level).

[0224] Optionally, referring further to Figures 19, 22, 25 and 28, the first control unit 10 and / or the second control unit 20 include a plurality of transistors, all of which are P-type channels.

[0225] P-type transistors are simple to manufacture and occupy less frame space, which helps save frame space and avoids risks such as low mobility, weak output capability, and circuit structure failure.

[0226] Based on the same inventive concept, this application also provides a display device. Figure 30 is a structural schematic diagram of a display device provided in an embodiment of this application. As shown in Figure 30, the display device includes a display panel 1 and a housing 2 provided in any embodiment of this application. Therefore, the display device provided in this application has the corresponding effects of the display panel provided in the embodiment of this application, which will not be described again here. Exemplarily, the display device can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and this application does not limit it to such devices.

Claims

1. A display panel, comprising: The driving circuit includes N cascaded shift registers, where N ≥ 2; The shift register includes: A first control unit and a second control unit, wherein the first control unit and the second control unit are electrically connected; The first control unit is configured to control the first output signal, where the first output signal of the i-th stage shift register is the first input signal of the j-th stage shift register, 1≤i≤N, 2≤j≤N; the first control unit includes a first node, and the potential of the first node is synchronized with the first output signal. The second control unit is configured to receive at least a frequency control signal and a potential signal from the first node, and to control the second output signal; The process of the first output signal transitioning from an invalid level to an effective level is the first voltage edge; When the first voltage edge of the first output signal overlaps with the effective pulse of the frequency control signal, the second output signal is an effective pulse.

2. The display panel according to claim 1, wherein, When the first voltage edge of the first output signal overlaps with an invalid pulse of the frequency control signal, the second output signal is an invalid pulse.

3. The display panel according to claim 1, wherein, When the first output signal is an invalid pulse, the second output signal is also an invalid pulse.

4. The display panel according to claim 1, wherein, The pulse change frequency of the first output signal is F1, and the pulse change frequency of the second output signal is F2; ​​wherein, F1≥F2.

5. The display panel according to claim 4, wherein, When the first voltage edge of the first output signal overlaps with the effective pulse of the frequency control signal, or when the first output signal is an invalid pulse, F1 = F2; When the first voltage edge of the first output signal overlaps with an invalid pulse of the frequency control signal, F1 > F2.

6. The display panel according to claim 1 further includes a pixel circuit, wherein the second output signal of the driving circuit is a control signal of a preset module of the pixel circuit; In response to the second output signal being a valid pulse, the preset module is activated; In response to the second output signal being an invalid pulse, the preset module is turned off.

7. The display panel according to claim 6, wherein, The operation of the display panel includes a first mode and a second mode; The frequency control signal is set to at least one of the following: In the first mode, the pulse variation frequency of the frequency control signal is Fc1; in the second mode, the pulse variation frequency of the frequency control signal is Fc2, where Fc1 ≠ Fc2; or, In the first mode, the effective pulse duration of the frequency control signal is Wc1, and in the second mode, the effective pulse duration of the frequency control signal is Wc2, wherein Wc1 ≠ Wc2.

8. The display panel according to claim 7, wherein, In the first mode, the pulse change frequency of the second output signal is Fs1, and in the second mode, the pulse change frequency of the second output signal is Fs2; wherein, Fs1≠Fs2.

9. The display panel according to claim 1, wherein, The second control unit includes a first control unit, a second control unit, a third control unit, and a second node; The first control unit further includes a third node, the potential of which is out of phase with the first output signal; The first control unit is configured to receive the potential signal and the first voltage signal of the first node, and control the second output signal to output an invalid pulse; The second control unit is configured to receive the potential signal and the frequency control signal from the first node, and control the potential of the second node; The third control unit is configured to receive the potential signal of the second node, the potential signal of the third node, and the second voltage signal, and control the second output signal to output a valid pulse; or, The second control unit is configured to receive the potential signal and the frequency control signal from the first node, and control the potential of the second node; The third control unit is configured to receive the potential signal of the second node and the potential signal of the third node, and control the second output signal to output a valid pulse; One of the first voltage signal and the second voltage signal is a high-level signal, and the other is a low-level signal.

10. The display panel according to claim 9, wherein, The first control unit includes a first transistor, the control terminal of the first transistor is electrically connected to the first node, the first terminal of the first transistor is configured to receive the first voltage signal, and the second terminal of the first transistor is configured to output an invalid pulse of the second output signal.

11. The display panel according to claim 10, wherein, The first control unit further includes a first capacitor, the first plate of the first capacitor being connected to the control terminal of the first transistor, and the second plate of the first capacitor being connected to the second terminal of the first transistor.

12. The display panel according to claim 9, wherein, The second control unit includes a second transistor and a second capacitor; The control terminal of the second transistor is electrically connected to the first node. The first terminal of the second transistor is configured to receive the frequency control signal. The second terminal of the second transistor is electrically connected to the first plate of the second capacitor and the second node, respectively. The second plate of the second capacitor receives a fixed potential signal.

13. The display panel according to claim 9, wherein, The third control unit includes a third transistor, the control terminal of the third transistor is electrically connected to the third node, the first terminal of the third transistor is electrically connected to the second node, and the second terminal of the third transistor is configured to output an effective pulse of the second output signal.

14. The display panel according to claim 9, wherein, The third control unit includes a fourth transistor, a fifth transistor, and a sixth transistor; The control terminal of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the first terminal of the fifth transistor and the control terminal of the sixth transistor, respectively. The control terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is configured to receive a third voltage signal; the third voltage signal has the same potential as the effective pulse of the first output signal. The first terminal of the sixth transistor is configured to receive the second voltage signal, and the second terminal of the sixth transistor is configured to output a valid pulse of the second output signal.

15. The display panel according to claim 14, wherein, The third control unit further includes a third capacitor, the first plate of which is electrically connected to the control terminal of the sixth transistor, and the second plate of which is electrically connected to the first terminal of the sixth transistor.

16. The display panel according to claim 14, wherein, The second voltage signal and the third voltage signal are voltage signals at the same potential.

17. The display panel according to claim 9, wherein, When the first voltage edge of the first output signal overlaps with the invalid pulse of the frequency control signal, neither the first control unit nor the third control unit outputs anything, and the second output signal maintains the level state of the second output signal when the first output signal is an invalid pulse.

18. The display panel according to claim 9, wherein, The second control unit further includes a fourth control unit, which is configured to receive at least the potential signal of the first node and control the second output signal to output an invalid pulse when the first voltage edge of the first output signal overlaps with the invalid pulse of the frequency control signal.

19. The display panel according to claim 18, wherein, The fourth control unit is further configured to control the second output signal to output a valid pulse when the first voltage edge of the first output signal overlaps with the valid pulse of the frequency control signal and the first output signal is a valid pulse.

20. The display panel according to claim 18, wherein, The fourth control unit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a fourth capacitor; The control terminal of the seventh transistor is electrically connected to the first node, the first terminal of the seventh transistor is configured to receive the fourth voltage signal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the eighth transistor and the first terminal of the ninth transistor, respectively. The second terminal of the eighth transistor receives the fifth voltage signal, and the conduction state of the eighth transistor is synchronized with the conduction state of the third control unit. The control terminal of the ninth transistor is configured to receive the sixth voltage signal, and the second terminal of the ninth transistor is connected to the control terminal of the tenth transistor and the first plate of the fourth capacitor, respectively. The first terminal of the tenth transistor is configured to receive the seventh voltage signal, and the second terminal of the tenth transistor is electrically connected to the second plate of the fourth capacitor and configured to output the second output signal. The fourth voltage signal has the same potential as the invalid pulse of the second output signal, the fifth voltage signal has the same potential as the valid pulse of the second output signal, the sixth voltage signal is configured to control the ninth transistor to be normally open, and the seventh voltage signal has the same potential as the invalid pulse of the second output signal.

21. The display panel according to claim 20, wherein, The first voltage signal, the fourth voltage signal, the sixth voltage signal, and the seventh voltage signal are signals with the same potential; The fifth voltage signal and the second voltage signal are signals with the same potential.

22. The display panel according to claim 20, wherein, At least two of the fourth voltage signal, the sixth voltage signal, and the seventh voltage signal are voltage signals at the same potential.

23. The display panel according to claim 1, wherein, The first control unit includes a fifth control unit, a sixth control unit, a seventh control unit, a fourth node, and a fifth node; The fifth control unit is configured to receive the first input signal, the eighth voltage signal, the ninth voltage signal, and the clock signal, and to control the potential of the fourth node and the potential of the fifth node. One end of the sixth control unit is configured to receive the tenth voltage signal, and the other end of the sixth control unit is configured to output the first output signal. The control terminal of the sixth control unit is electrically connected to the fourth node. One end of the seventh control unit is configured to receive the eleventh voltage signal, and the other end of the seventh control unit is configured to output the first output signal. The control terminal of the seventh control unit is electrically connected to the fifth node. One of the eighth voltage signal and the ninth voltage signal is a high-level signal, and the other is a low-level signal; One of the tenth voltage signal and the eleventh voltage signal is a high-level signal, and the other is a low-level signal.

24. The display panel according to claim 23, wherein, The eighth voltage signal and the tenth voltage signal are voltage signals at the same potential; the ninth voltage signal and the eleventh voltage signal are voltage signals at the same potential.

25. The display panel according to claim 23, wherein, The fifth control unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a fifth capacitor; The first terminal of the eleventh transistor and the control terminal of the twelfth transistor are electrically connected and configured to receive the first input signal. The control terminal of the eleventh transistor, the first plate of the fifth capacitor, and the first terminal of the thirteenth transistor are electrically connected and configured to receive the clock signal. The second terminal of the eleventh transistor is electrically connected to the first terminal of the fourteenth transistor and the control terminal of the fifteenth transistor, respectively. The first terminal of the twelfth transistor is electrically connected to the second plate of the fifth capacitor and the control terminal of the thirteenth transistor, respectively. The second terminal of the twelfth transistor is electrically connected to the first terminal of the fifteenth transistor and is configured to receive the eighth voltage signal. The second terminal of the thirteenth transistor and the second terminal of the fifteenth transistor are both electrically connected to the fourth node; The second terminal of the fourteenth transistor is electrically connected to the fifth node, and the control terminal of the fourteenth transistor is configured to receive the ninth voltage signal.

26. The display panel according to claim 23, wherein, The sixth control unit includes a sixteenth transistor and a sixth capacitor; The control terminal of the sixteenth transistor and the first plate of the sixth capacitor are both electrically connected to the fourth node. The first terminal of the sixteenth transistor and the second plate of the sixth capacitor are electrically connected and configured to receive the tenth voltage signal. The second terminal of the sixteenth transistor is configured to output the first output signal.

27. The display panel according to claim 23, wherein, The seventh control unit includes a seventeenth transistor and a seventh capacitor; The control terminal of the seventeenth transistor and the first plate of the seventh capacitor are both electrically connected to the fifth node. The first terminal of the seventeenth transistor is configured to receive the eleventh voltage signal, and the second terminal of the seventeenth transistor is electrically connected to the second plate of the seventh capacitor and configured to output the first output signal.

28. The display panel according to claim 9, wherein, The first control unit is also configured to control a third output signal, wherein the third output signal of the i-th stage shift register is the second input signal of the j-th stage shift register; Within a preset duration, the first output signal includes a first valid pulse, a first invalid pulse, and a second valid pulse that are sequentially adjacent. During the time period of the first valid pulse, the first invalid pulse, and the second valid pulse, the third output signal is a valid pulse, and the voltage edge of the third output signal transitioning from an invalid level to a valid level is synchronized with the voltage edge of the first valid pulse transitioning from an invalid level to a valid level. The voltage edge of the third output signal transitioning from an active level to an inactive level is synchronized with the voltage edge of the second active pulse transitioning from an active level to an inactive level. The second control unit is configured to receive the potential signal of the first node, the frequency control signal and the third output signal, and control the second output signal.

29. The display panel according to claim 28, wherein, The first control unit further includes an eighth control unit, which is configured to receive the second input signal, the twelfth voltage signal and the clock signal, and control the third output signal; The twelfth voltage signal has the same potential as the invalid pulse of the third output signal.

30. The display panel according to claim 29, wherein, The eighth control unit includes an eighteenth transistor and an eighth capacitor; The first terminal of the eighteenth transistor is configured to receive the second input signal, and the second terminal of the eighteenth transistor is electrically connected to the first plate of the eighth capacitor and configured to output the third output signal; the second plate of the eighth capacitor is configured to receive the twelfth voltage signal.

31. The display panel according to claim 1, wherein, At least one of the first control unit and the second control unit includes a plurality of transistors, all of which are P-type channels.

32. A display device comprising a display panel and a housing as described in any one of claims 1-31.

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