Scanning signal line driving circuit and display device

Abstract

The present invention provides a scan signal line driving circuit that can suppress the degradation of the characteristics of the stabilization elements of the stabilization circuits provided in each stage of a shift register circuit. [Solution] Each stage of the shift register circuit of the scanning signal line drive circuit includes first, second, and third transistors and a stabilization circuit that suppresses fluctuations in the potential of the first internal node and the first output terminal during the non-selection period. The stabilization circuit includes at least one of a fourth transistor whose gate is electrically connected to the second internal node, one of its source and drain is electrically connected to the first internal node, and the other is supplied with a first reference potential, and a fifth transistor whose gate is electrically connected to the second internal node, one of its source and drain is electrically connected to the first output terminal, and the other is supplied with a second reference potential. During at least a portion of the vertical retrace period, the potential of the second internal node is lower than the potential of the first internal node, the potential of the first output terminal, the first reference potential, and the second reference potential.

Description

Technical Field

[0001] The present invention relates to a scanning signal line driving circuit and a display device.

Background Art

[0002] In the non-display area (sometimes called the peripheral area) of the active matrix substrate included in the display device, peripheral circuits such as a driving circuit may be formed monolithically (integrally). By forming the peripheral circuits monolithically, it is possible to realize narrowing of the non-display area (narrowing of the frame margin) and cost reduction by simplifying the mounting process. For example, in the non-display area, a scanning signal line driving circuit may be formed monolithically, and a display signal line driving circuit may be mounted by a COG (Chip on Glass) method. The scanning signal line driving circuit formed monolithically is called a GDM (Gate Driver Monolithic) circuit or a GOA (Gate On Array) circuit.

[0003] The scanning signal line driving circuit outputs a scanning signal to these scanning signal lines so that a plurality of scanning signal lines are sequentially selected in each vertical scanning period. Therefore, the scanning signal line driving circuit includes a shift register circuit having a number of stages corresponding to the number of scanning signal lines. Each stage of the shift register circuit is composed of a circuit (sometimes called a "unit circuit") including a plurality of thin film transistors (TFTs). The unit circuit includes a TFT (sometimes called an "output element") that is electrically connected to an output terminal and controls the output of the scanning signal to the scanning wiring.

[0004] In each stage of the shift register circuit, it is preferable that the output scanning signal is surely maintained at a low level during a period when the corresponding scanning signal line is not selected (referred to as a "non-selection period"). Therefore, it has been proposed to provide a stabilization circuit in each stage of the shift register circuit to more surely maintain the scanning signal output during the non-selection period at a low level. Such a stabilization circuit is disclosed in, for example, Patent Document 1.

Prior Art Documents

[0005] [Patent Document 1] International Publication No. 2017 / 006815 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] However, among the TFTs that make up the stabilization circuit, the TFT that operates during the non-selective period (hereinafter also referred to as the "stabilization element") has a high operating duty cycle, so its characteristics degrade quickly. Therefore, there is a concern that the stabilization circuit's effect may not be fully achieved as the characteristics of the stabilization element deteriorate. In addition, it is possible that the balance of the circuit operation may be disrupted if the degradation rate of the stabilization element and the output element differs. For example, there is a concern that while the stabilization element degrades and generates minute noise, the output element, which has maintained sufficient capability, may pick up that minute noise and malfunction.

[0007] Embodiments of the present invention have been made in view of the above problems, and their object is to provide a scanning signal line driving circuit that can suppress the degradation of the characteristics of the stabilization elements of the stabilization circuit provided in each stage of the shift register circuit. [Means for solving the problem]

[0008] This specification discloses scanning signal line driving circuits and display devices as described in the following sections.

[0009] [Item 1] A scanning signal line driving circuit that supplies scanning signals to multiple scanning signal lines provided by a display device, It features a shift register circuit with multiple stages, Each of the aforementioned stages is The first clock terminal to which the first clock signal is input, A set terminal into which a set signal is input, The reset terminal to which the reset signal is input, A first output terminal that outputs a scanning signal, A first transistor having its gate electrically connected to a first internal node, one of its source and drain electrically connected to the clock terminal, and the other of its source and drain electrically connected to the first output terminal, A second transistor having its gate electrically connected to the set terminal and its source or drain electrically connected to the first internal node, A third transistor having its gate electrically connected to the reset terminal, one of its source and drain electrically connected to the first internal node, and the other of its source and drain electrically connected to a first reference voltage source, A stabilization circuit electrically connected to the first internal node and the first output terminal, which suppresses potential fluctuations of the first internal node and the first output terminal during the non-selective period, It has, The aforementioned stabilization circuit is A fourth transistor whose gate is electrically connected to a second internal node, whose source and drain are electrically connected to the first internal node, and to which a first reference potential is applied to the other source and drain, The system includes at least one of a fifth transistor, the gate of which is electrically connected to the second internal node, the source and drain of which one is electrically connected to the first output terminal, and the source and drain of which a second reference potential is given, which is the same as or different from the first reference potential. A scanning signal line drive circuit configured such that, during at least a portion of the vertical retrace period among the effective display period and the vertical retrace period included in the vertical scanning period, the potential of the second internal node is lower than the potential of the first internal node, the potential of the first output terminal, the first reference potential, and the second reference potential.

[0010] [Item 2] The stabilization circuit includes at least the fourth transistor among the fourth and fifth transistors, The source and the other drain of the fourth transistor are electrically connected to the first reference voltage source. The aforementioned stabilization circuit is The present invention further comprises a sixth transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to a second reference voltage source. The scanning signal line drive circuit according to item 1, wherein the potential of the second reference voltage source is substantially the same as the potential of the first reference voltage source during the effective display period and lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period.

[0011] [Item 3] The aforementioned stabilization circuit is The system further comprises a seventh transistor, one of which is electrically connected as a source and drain to a first charge source for supplying charge to the second internal node, and the other of which is electrically connected as a source and drain to the second internal node. The scanning signal line driving circuit according to item 2, wherein the potential of the first charge source is lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period.

[0012] [Item 4] The aforementioned stabilization circuit is The scanning signal line drive circuit according to item 2 or 3, further comprising an eighth transistor whose gate is electrically connected to the set terminal, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the second reference voltage source.

[0013] [Item 5] Each of the aforementioned stages is A second output terminal outputs a signal to drive other stages at the same timing as the scanning signal is output from the first output terminal, A ninth transistor having a gate electrically connected to the first internal node, one of a source and a drain electrically connected to the clock terminal, and the other of the source and the drain electrically connected to the second output terminal; The scan signal line driving circuit according to any one of items 1 to 4, further comprising .

[0014] [Item 6] Each of the plurality of stages The scan signal line driving circuit according to item 5, further comprising a tenth transistor having a gate electrically connected to the second internal node, one of a source and a drain electrically connected to the second output terminal, and the other of the source and the drain electrically connected to the first reference voltage source.

[0015] [Item 7] Each of the plurality of stages The scan signal line driving circuit according to any one of items 1 to 6, further comprising an eleventh transistor having a gate supplied with a signal output from another stage, one of a source and a drain electrically connected to the first output terminal, and the other of the source and the drain electrically connected to the first reference voltage source.

[0016] [Item 8] The stabilization circuit includes at least the fifth transistor among the fourth transistor and the fifth transistor, Each of the plurality of stages has a tenth transistor having a gate electrically connected to the second internal node, one of a source and a drain electrically connected to the second output terminal, and the other of the source and the drain electrically connected to the first reference voltage source, the other of the source and the drain of the fifth transistor is electrically connected to a third reference voltage source, The scan signal line driving circuit according to item 5, wherein the potential of the third reference voltage source is higher than the potential of the first reference voltage source.

[0017] [Item 9] Each of the aforementioned stages is The scanning signal line drive circuit according to item 8, further comprising an eleventh transistor to which a signal output from another stage is applied to the gate, one of which is electrically connected to the first output terminal and the other of which is electrically connected to the third reference voltage source.

[0018] [Item 10] The stabilization circuit includes both the fourth transistor and the fifth transistor, A scanning signal line drive circuit according to any one of items 1 to 9, wherein the other source and drain of the fourth transistor and the other source and drain of the fifth transistor are electrically connected to the first reference voltage source, and the first reference potential and the second reference potential are the same.

[0019] [Item 11] Each of the aforementioned stages is A second clock terminal to which a second clock signal having the same phase as or a phase shifted from the first clock signal is input, A third clock terminal to which a third clock signal having a phase shifted from the second clock signal is input, It further possesses, The aforementioned stabilization circuit is A 12th transistor whose gate is electrically connected to the second clock terminal and whose source and drain are electrically connected to the second internal node, A 13th transistor whose gate is electrically connected to the third clock terminal, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the second reference voltage source, A scanning signal line drive circuit as described in item 2, further comprising the above.

[0020] [Item 12] The aforementioned stabilization circuit is A 14th transistor whose gate is electrically connected to a third internal node, whose source and drain are electrically connected to the first internal node, and to which the first reference potential is applied to the other source and drain, A 15th transistor whose gate is electrically connected to the third internal node, whose source and drain are electrically connected to the first output terminal, and to which the second reference potential is applied to the other source and drain, A 16th transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the third internal node, and whose other source and drain are electrically connected to the second reference voltage source, The present invention further comprises a 17th transistor, one of which is electrically connected as a source and drain to a second charge source for supplying charge to the third internal node, and the other of which is electrically connected as a source and drain to the third internal node. The potential of the second charge source is lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period. The scan signal line drive circuit according to item 3, wherein in one of two consecutive vertical scanning periods, the potential of the first charge source is higher than the potential of the second charge source, and in the other of the two consecutive vertical scanning periods, the potential of the second charge source is higher than the potential of the first charge source.

[0021] [Item 13] The aforementioned stabilization circuit is A 14th transistor whose gate is electrically connected to a third internal node, whose source and drain are electrically connected to the first internal node, and to which the first reference potential is applied to the other source and drain, A 15th transistor whose gate is electrically connected to the third internal node, whose source and drain are electrically connected to the first output terminal, and to which the second reference potential is applied to the other source and drain, A 18th transistor, with one of its source and drain electrically connected to a first charge source for supplying charge to the second internal node, and the other of its source and drain electrically connected to the second internal node, A 19th transistor, in which the gate and one of the source and drain are electrically connected to the second internal node, and the other of the source and drain is electrically connected to the first charge source, A 20th transistor, with one of its source and drain electrically connected to a second charge source for supplying charge to the third internal node, and the other of its source and drain electrically connected to the third internal node, A 21st transistor, in which the gate and one of the source and drain are electrically connected to the third internal node, and the other of the source and drain is electrically connected to the second charge source, A 22nd transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the third internal node, A 23rd transistor whose gate is electrically connected to the set terminal, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the third internal node, It further possesses, The potential of the first charge source and the potential of the second charge source are lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period. The scan signal line drive circuit according to item 3, wherein in one of two consecutive vertical scanning periods, the potential of the first charge source is higher than the potential of the second charge source, and in the other of the two consecutive vertical scanning periods, the potential of the second charge source is higher than the potential of the first charge source.

[0022] [Item 14] It has multiple pixels arranged in a matrix that includes multiple pixel rows and multiple pixel columns, Each of the scan signal lines is associated with one of the aforementioned row of pixels, A scan signal line drive circuit according to any one of items 1 to 13, which supplies scan signals to the plurality of scan signal lines, A display device equipped with the following features. [Effects of the Invention]

[0023] According to embodiments of the present invention, a scanning signal line driving circuit can be provided that can suppress the degradation of the characteristics of the stabilization elements of the stabilization circuits provided in each stage of the shift register circuit. [Brief explanation of the drawing]

[0024] [Figure 1] This is a schematic plan view showing a liquid crystal display device 100 according to an embodiment of the present invention. [Figure 2] This diagram shows the circuit configuration for outputting the scanning signal. [Figure 3] This is a circuit diagram showing an example of the configuration of each stage in the shift register circuit SR. [Figure 4] This is an example of a timing chart used to explain the operation of the shift register circuit SR. [Figure 5] This is a schematic diagram showing another example of a shift register circuit (shift register circuit SRA). [Figure 6] This is a schematic diagram showing yet another example of a shift register circuit (a shift register circuit SRB). [Figure 7] This is an example of a timing chart used to explain the operation of a shift register circuit (SRB). [Figure 8] This is a schematic diagram showing yet another example of a shift register circuit (shift register circuit SRC). [Figure 9] This is an example of a timing chart used to explain the operation of the shift register circuit SRC. [Figure 10] This is a schematic diagram showing yet another example of a shift register circuit (shift register circuit SRD). [Figure 11]This is an example of a timing chart used to explain the operation of the shift register circuit SRD. [Figure 12] This is a schematic diagram showing yet another example of a shift register circuit (shift register circuit SRE). [Figure 13] This is an example of a timing chart used to explain the operation of a shift register circuit (SRE). [Figure 14] This is a schematic diagram showing yet another example of a shift register circuit (shift register circuit SRF). [Figure 15] This is an example of a timing chart used to explain the operation of a shift register circuit (SRF). [Modes for carrying out the invention]

[0025] A scanning signal line driving circuit according to an embodiment of the present invention is a scanning signal line driving circuit that supplies scanning signals to a plurality of scanning signal lines provided by a display device, and comprises a shift register circuit having a plurality of stages. Each of the plurality of stages includes a first clock terminal to which a first clock signal is input, a set terminal to which a set signal is input, a reset terminal to which a reset signal is input, a first output terminal to which a scanning signal is output, a first transistor whose gate is electrically connected to a first internal node, one of its source and drain is electrically connected to a clock terminal, and the other of its source and drain is electrically connected to a first output terminal, a second transistor whose gate is electrically connected to a set terminal, and either its source or drain is electrically connected to a first internal node, a third transistor whose gate is electrically connected to a reset terminal, one of its source and drain is electrically connected to a first internal node, and the other of its source and drain is electrically connected to a first reference voltage source, and a stabilization circuit electrically connected to the first internal node and the first output terminal to suppress fluctuations in the potential of the first internal node and the first output terminal during the non-selective period. The stabilization circuit includes at least one of a fourth transistor whose gate is electrically connected to a second internal node, one of its source and drain is electrically connected to a first internal node, and a first reference potential is provided to the other of its source and drain; and a fifth transistor whose gate is electrically connected to a second internal node, one of its source and drain is electrically connected to a first output terminal, and a second reference potential that is the same as or different from the first reference potential is provided to the other of its source and drain, wherein during at least a portion of the retrace period of the effective display period and retrace period included in one vertical scanning period, the potential of the second internal node is lower than the potential of the first internal node, the potential of the first output terminal, the first reference potential, and the second reference potential.

[0026] Each stage of a shift register circuit has a transistor, which is a switching element, and a typical example of this is a TFT. The scanning signal line driving circuit according to an embodiment of the present invention is a GOA circuit and is composed of a single-polarity (i.e., n-type or p-type) TFT. In the following, a GOA circuit composed of an n-type TFT will be described as an example. Note that the electrical connections of the source and drain of a p-type TFT are reversed compared to the electrical connections of the source and drain of an n-type TFT.

[0027] For example, multiphase clock signals such as 4-phase, 6-phase, and 8-phase signals are used as clock signals. The scan signal output from one stage of the shift register circuit can be input to other stages of the circuit as a set signal or reset signal.

[0028] Embodiments of the present invention will be described below with reference to the drawings. In the following, a liquid crystal display device will be given as an example of a display device according to the embodiments of the present invention, but the display device according to the embodiments of the present invention is not limited to a liquid crystal display device.

[0029] First, the overall configuration of the liquid crystal display device 100 according to an embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a schematic plan view showing the liquid crystal display device 100.

[0030] As shown in Figure 1, the liquid crystal display device 100 has a plurality of pixels P arranged in a matrix containing a plurality of pixel rows and a plurality of pixel columns. The liquid crystal display device 100 is an active-matrix liquid crystal display device, and each pixel P has a thin-film transistor (TFT) 10 and a liquid crystal capacitance Clc. Each pixel P may further have an auxiliary capacitance Cs (not shown) electrically connected in parallel with the liquid crystal capacitance Clc. A detailed explanation of the auxiliary capacitance Cs is omitted here. The liquid crystal capacitance Clc is composed of, for example, a pixel electrode (not shown) formed on the active matrix substrate 110 and a common electrode (also called a counter electrode; not shown) arranged to face the pixel electrode via a liquid crystal layer (not shown). The common electrode is formed on, for example, a counter substrate 112 arranged to face the active matrix substrate 110. The region AA where the plurality of pixels P are arranged is called the "active region" or "display region".

[0031] The liquid crystal display device 100 further has a plurality of scan signal lines (also called "gate bus lines") GB, each associated with one of a plurality of pixel rows, and a plurality of display signal lines (also called "source bus lines") SB, each associated with one of a plurality of pixel columns. The gate electrode of the TFT 10 of each pixel P is electrically connected to the scan signal line GB associated with the pixel row in which the pixel is contained, and the source electrode of the TFT 10 of each pixel P is electrically connected to the display signal line SB associated with the pixel column in which the pixel is contained.

[0032] The liquid crystal display device 100 further includes a scan signal line drive circuit (hereinafter also referred to as a "gate drive circuit") 120 that supplies scan signals to a plurality of scan signal lines GB, and a display signal line drive circuit (hereinafter also referred to as a "source drive circuit") 140 that supplies display signals to a plurality of display signal lines SB.

[0033] The gate drive circuit 120 is a GOA circuit and is formed on the active matrix substrate 110, similar to the pixel electrodes, TFT 10, scan signal line GB, display signal line SB, etc. The active matrix substrate 110 can be fabricated, as is well known, for example, by depositing and patterning conductive layers (metal layers), semiconductor layers, and insulating layers on a glass substrate using known methods. The source drive circuit 140 may be mounted on the active matrix substrate 110 as a source drive IC, for example, or a flexible substrate on which the source drive IC is mounted may be connected to the active matrix substrate 110.

[0034] The gate drive circuit 120 and the source drive circuit 140 are controlled by a control circuit (not shown). The control circuit includes a display control circuit and a power supply circuit, which are composed of a timing controller. The display control circuit supplies the necessary control signals to the gate drive circuit 120 and the source drive circuit 140, respectively, and the power supply circuit supplies the necessary power supply voltage to the gate drive circuit 120 and the source drive circuit 140, respectively. The configuration and operation of the control circuit are well known, so a detailed explanation is omitted.

[0035] Next, the configuration of the gate drive circuit 120 will be explained with reference to Figure 2. Figure 2 is a diagram showing the circuit configuration for outputting a scan signal. As shown in Figure 2, the gate drive circuit 120 is composed of a shift register circuit SR, and the shift register circuit SR has multiple stages (sometimes called "unit circuits"). A scan signal G is output from each stage of the shift register circuit SR to the corresponding scan signal line GB. In Figure 2, the scan signal corresponding to the nth pixel row is represented as G(n), and the nth stage of the shift register circuit SR is represented as SR(n).

[0036] Each stage of the shift register circuit SR has the following input terminals: a clock terminal CLK, a set terminal Set, a reset terminal Reset, a first reference voltage terminal Vs1, a second reference voltage terminal Vs2, and a charge supply terminal Vd. For convenience of explanation, in this specification, the same reference designation may be used for the reference designation of the terminals and for the signals input to or output from the terminals. Each stage of the shift register circuit SR also has an output terminal G.

[0037] The clock signal CLK is input to the clock terminal CLK. In the illustrated example, the clock signal CLK is the 4-phase clock signals CLK1, CLK2, CLK3, and CLK4. The set signal Set is input to the set terminal Set. The reset signal Reset is input to the reset terminal Reset. The scan signals G generated in other stages are used as the set signal Set and the reset signal Reset. In the illustrated example, the scan signal G(n-2) generated two stages prior is used as the set signal Set for the nth stage SR(n), and the scan signal G(n+3) generated three stages later is used as the reset signal Reset.

[0038] The first reference voltage terminal Vs1 receives the first reference voltage signal Vs1. In this specification, being electrically connected to the first reference voltage terminal Vs1 is sometimes expressed as "being electrically connected to the first reference voltage source," and the first reference voltage signal Vs1 is sometimes expressed as "the potential Vs1 of the first reference voltage source." The second reference voltage terminal Vs2 receives the second reference voltage signal Vs2. In this specification, being electrically connected to the second reference voltage terminal Vs2 is sometimes expressed as "being electrically connected to the second reference voltage source," and the second reference voltage signal Vs2 is sometimes expressed as "the potential Vs2 of the second reference voltage source." The charge supply terminal Vd is electrically connected to a charge supply source, which will be described later. In this specification, the potential of the charge supply source is sometimes expressed as Vd.

[0039] The output terminal G outputs a scan signal G. The output scan signal G is supplied to the corresponding scan signal line GB.

[0040] Next, with reference to Figure 3, the specific circuit configuration of each stage of the shift register circuit SR will be explained. Figure 3 is a circuit diagram showing an example configuration of the nth stage SR(n). As shown in Figure 3, each stage of the shift register circuit SR has a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor C.

[0041] The first transistor M1, the second transistor M2, the third transistor M3, and the capacitor C are electrically connected by a common node netA. This node netA will be referred to as the "first internal node" below.

[0042] The gate of the first transistor M1 is electrically connected to the first internal node netA. The drain of the first transistor M1 is electrically connected to the clock terminal CLK. The source of the first transistor M1 is electrically connected to the output terminal G. The first transistor M1 has the function of outputting the voltage of the clock signal CLK to the output terminal G.

[0043] The gate and drain of the second transistor M2 are diode-connected and electrically connected to the set terminal Set. The source of the second transistor M2 is electrically connected to the first internal node netA. The second transistor M2 has the function of raising the potential of the first internal node netA.

[0044] The gate of the third transistor M3 is electrically connected to the reset terminal Reset. The drain of the third transistor M3 is electrically connected to the first internal node netA. The source of the third transistor M3 is electrically connected to the first reference voltage terminal Vs1 (i.e., to the first reference voltage source). The third transistor M3 has the function of lowering the potential of the first internal node netA.

[0045] One end of capacitor C is electrically connected to the first internal node netA. The other end of capacitor C is electrically connected to the output terminal G. Capacitor C is a so-called bootstrap capacitor that maintains the potential of the first internal node netA, which rises when the second transistor M2 is ON.

[0046] Each stage of the shift register circuit SR further includes a stabilization circuit SC. The stabilization circuit SC is electrically connected to the first internal node netA and the output terminal G, and suppresses fluctuations in the potential of the first internal node netA and the output terminal G during the non-selective period. In other words, the stabilization circuit SC is provided to more reliably maintain the potential of the first internal node netA and the output terminal G at a low level during the non-selective period.

[0047] In the example shown in Figure 3, the stabilization circuit SC has a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are electrically connected by a common node netB. This node netB will be referred to as the "second internal node" below.

[0048] The gate of the fourth transistor M4 is electrically connected to the second internal node netB. The drain of the fourth transistor M4 is electrically connected to the first internal node netA. The source of the fourth transistor M4 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). The fourth transistor M4 has the function of maintaining the potential of the first internal node netA at a low level during the non-selective period.

[0049] The gate of the fifth transistor M5 is electrically connected to the second internal node netB. The drain of the fifth transistor M5 is electrically connected to the output terminal G. The source of the fifth transistor M5 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). The fifth transistor M5 has the function of maintaining the potential of the output terminal G at a low level during the non-selective period.

[0050] When the potential supplied to the source of the fourth transistor M4 is called the "first reference potential" and the potential supplied to the source of the fifth transistor M5 is called the "second reference potential", in the example shown in Figure 3, since both the source of the fourth transistor M4 and the source of the fifth transistor M5 are electrically connected to the first reference voltage source, the first reference potential and the second reference potential are the same potential.

[0051] The gate of the sixth transistor M6 is electrically connected to the first internal node netA. The drain of the sixth transistor M6 is electrically connected to the second internal node netB. The source of the sixth transistor M6 is electrically connected to the second reference voltage terminal Vs2 (in other words, to the second reference voltage source). The sixth transistor M6 has the function of lowering the potential of the second internal node netB.

[0052] The gate and drain of the seventh transistor M7 are diode-connected and electrically connected via the charge supply terminal Vd to a charge source for supplying charge to the second internal node netB. The source of the seventh transistor M7 is electrically connected to the second internal node netB. The seventh transistor M7 has the function of raising the potential of the second internal node netB.

[0053] The operation of the shift register circuit SR will be explained with reference to Figure 4. Figure 4 is an example of a timing chart for explaining the operation of the shift register circuit SR. Here, "frame" refers to the period during which one image is displayed in display area AA, and is sometimes called the "vertical scan period". The reciprocal of the vertical scan period is sometimes called the vertical frequency, and for example, in the case of 120Hz drive, 120 images are displayed per second, and this is sometimes expressed as 120fps (120 frames / sec). A frame has a beginning and an end, and does not simply represent a length of time. The timing of the end of a frame is the same as the timing of the beginning of the next frame. When expressing the length of time of a frame, it is called 1 frame period or 1 vertical scan period (1V). The period from when an arbitrary pixel row (scan signal line GB) is selected in a given frame until that pixel row (scan signal line GB) is selected in the next frame corresponds to 1 frame period (1 vertical scan period). Also, within a frame, the period from when one pixel row is selected until the next pixel row is selected is called 1 horizontal scan period (1H). The vertical scan period includes the "effective display period," which is the period from when the first pixel row is selected until the writing of the last pixel row is completed, and the "vertical retrace period."

[0054] At time t1, the set signal Set changes from a low level to a high level. Hereafter, the change from a low level to a high level is called the "rising edge," and the change from a high level to a low level is called the "falling edge." In this case, the set signal Set is the scan signal G(n-2) output from two stages prior. When the set signal Set rises, the second transistor M2 turns on, and charging (precharging) of capacitor C begins. As a result, the potential of the first internal node netA changes to the precharge voltage. The precharge voltage is the voltage obtained by subtracting the threshold voltage (Vth) of the second transistor M2 from the high-level voltage of the set signal Set. This turns on the first transistor M1. The period from time t1 to time t2 is called the "set period." During the set period, the clock signal CLK is at a low level, so the signal level output from the first transistor M1 is at a low level. That is, the scan signal Gn remains at a low level without changing.

[0055] At time t2, the clock signal CLK rises. When the clock signal CLK rises and the potential of the first internal node netA rises, the second transistor M2 turns off, independent of the voltage level of the set signal Set. This is because the source potential of the second transistor M2 rises and the gate potential becomes relatively low. In the example shown in Figure 4, the set signal Set falls, and the second transistor M2 turns off. Furthermore, since the reset signal Reset remains at a low level, the third transistor M3 remains off. As a result, the first internal node netA becomes floating. At time t2, when the clock signal CLK rises, the charge stored in capacitor C maintains the voltage across capacitor C, that is, the potential difference between the first internal node netA and the output terminal G(n). Therefore, when the potential of the drain of the first transistor M1 rises, the potential of the first internal node netA also rises to above the input voltage. This is the bootstrap of the first internal node netA. During the bootstrap process, the potential of the first internal node netA rises to a level even higher than the high level of the clock signal CLK. As a result, the first transistor M1 remains in the ON state, and the signal level output from the first transistor M1 becomes high. The period from time t2 to time t3 is called the "bootstrap period." During the bootstrap period, a high-level scan signal G(n) is output. The period obtained by adding the bootstrap period to the set period corresponds to the charging period of capacitor C.

[0056] At time t3, the clock signal CLK falls. At this time, the first transistor M1 remains ON. The potential of the drain of the first transistor M1 decreases, and consequently, the potential of the output terminal G(n) also decreases. In addition, as the potential of the output terminal G(n) decreases, the potential of the first internal node netA also decreases to the level at which it was during the set period. The period from time t3 to time t4 is called the "bootstrap release period".

[0057] At time t4, the reset signal Reset rises, which turns on the third transistor M3. Here, the reset signal Reset is the scan signal G(n+3) output from three stages later. The charge held in capacitor C is discharged, and the potential of the first internal node netA drops to a low level and is reset. The period from time t4 to time t5 when the reset signal Reset falls is called the "reset period".

[0058] During the effective display period, when the first internal node netA is at a low level and the second internal node netB is at a high level (the period before time t1 and the period after time t4), the fourth transistor M4 and the fifth transistor M5 are turned on. As a result, the potential of the first internal node netA and the output terminal G(n) is drawn to the potential Vs1 of the first reference voltage source, so that the potential of the first internal node netA and the output terminal G(n) can be more reliably maintained at a low level during the non-selective period.

[0059] Furthermore, in this embodiment, the potential Vs2 of the second reference voltage source is substantially the same as the potential Vs1 of the first reference voltage source during the effective display period, and is lower than the potential Vs1 of the first reference voltage source for at least a portion of the vertical retrace period (a portion of the vertical retrace period in the example shown in Figure 4). Also, the potential Vd of the charge supply source is lower than the potential Vs1 of the first reference voltage source for at least a portion of the vertical retrace period (a portion of the vertical retrace period in the example shown in Figure 4). Therefore, for at least a portion of the vertical retrace period (a portion of the vertical retrace period in the example shown in Figure 4), the potential of the second internal node netB is lower than the potential of the first internal node netA, the potential of the output terminal G(n), the first reference potential (here, the potential Vs1 of the first reference voltage source), and the second reference potential (here, the potential Vs1 of the first reference voltage source). As a result, the fourth transistor M4 and the fifth transistor M5, which are stabilizing elements, are subjected to a load in the opposite direction to that of other periods for at least a portion of the vertical retrace period. Therefore, the effects of the load on the stabilizing element during other periods are offset by the reverse load during at least a portion of the vertical retrace period, thus suppressing the degradation of the stabilizing element's characteristics.

[0060] Figure 4 shows an example where the potential of the second internal node netB is lower than the potential of the first internal node netA, etc., for a portion of the vertical retrace period. However, the potential of the second internal node netB may be lower than the potential of the first internal node netA, etc., for the entire vertical retrace period. Furthermore, the length of the period (period TL in Figure 4) during which the potential of the second internal node netB is lower than the potential of the first internal node netA, the output terminal G(n), the first reference potential, and the second reference potential is not particularly limited. However, from the viewpoint of sufficiently suppressing the degradation of the characteristics of the stabilizing element, it is preferable to set the stabilizing element to be subjected to a reverse load of approximately the same magnitude as the load applied during the effective display period. For example, if the load on the element is expressed as the product of the applied voltage V and the applied time T, it is preferable that a negative applied voltage VL is applied for an application time TL such that the relationship VH × TH = VL × TL is satisfied during the vertical retrace period, relative to the positive applied voltage VH and its application time TH during the effective display period. When it is difficult to set sufficient VL and TL due to constraints such as ensuring an effective display period or power supply limitations, setting the largest possible VL and TL under such constraints can maximize the effect of suppressing the degradation of the stabilizing element's characteristics.

[0061] Furthermore, although Figure 4 shows an example in which the stabilization circuit SC has both the fourth transistor M4 and the fifth transistor M5, the stabilization circuit SC only needs to have at least one of the fourth transistor M4 and the fifth transistor M5. In other words, either the fourth transistor M4 or the fifth transistor M5 may be omitted.

[0062] Figure 5 shows another example of a shift register circuit. The shift register circuit SRA shown in Figure 5 differs from the shift register circuit SR shown in Figure 3 in that the stabilization circuit SC in each stage (Figure 5 illustrates the nth stage SRA(n)) has an eighth transistor M8.

[0063] The gate of the eighth transistor M8 is electrically connected to the set terminal Set. The drain of the eighth transistor M8 is electrically connected to the second internal node netB. The source of the eighth transistor M8 is electrically connected to the second reference voltage terminal Vs2 (in other words, to the second reference voltage source). The eighth transistor M8 turns on in response to the rising edge of the set signal Set and has the function of lowering the potential of the second internal node netB. The timing chart for explaining the operation of the shift register circuit SRA may be the same as the timing chart shown in Figure 4, for example, so its illustration is omitted here.

[0064] In the shift register circuit SRA shown in Figure 5, the stabilization circuit SC has an eighth transistor M8, which allows for more reliable shutdown of the second internal node netB, thereby further improving reliability.

[0065] Figure 6 shows yet another example of a shift register circuit. The shift register circuit SRB shown in Figure 6 differs from the shift register circuit SRA shown in Figure 5 in that each stage (the nth stage SRB(n) is illustrated in Figure 6) has an additional output terminal Q and a ninth transistor M9.

[0066] Output terminal Q outputs a signal Q that drives other stages at the same timing as the scan signal G is output from output terminal G. In Figure 6, the signal output from output terminal Q of the nth row stage SRB(n) is represented as Q(n). Signal Q is input to other stages as a set signal Set or a reset signal Reset. Here, for the nth stage SRB(n), the signal Q(n-2) generated two stages prior is used as the set signal Set, and the signal Q(n+3) generated three stages later is used as the reset signal Reset. Hereafter, output terminal G may be referred to as the "first output terminal" and output terminal Q as the "second output terminal".

[0067] The gate of the ninth transistor M9 is electrically connected to the first internal node netA. The drain of the ninth transistor M9 is electrically connected to the clock terminal CLK. The source of the ninth transistor M9 is electrically connected to the second output terminal Q. The ninth transistor M9 has the function of outputting the voltage of the clock signal CLK to the second output terminal Q.

[0068] Furthermore, the shift register circuit SRB shown in Figure 6 differs from the shift register circuit SRA shown in Figure 5 in that each stage has a 10th transistor M10 and an 11th transistor M11.

[0069] The gate of the 11th transistor M11 is electrically connected to the reset terminal Reset. The drain of the 11th transistor M11 is electrically connected to the first output terminal G. The source of the 11th transistor M11 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). The 11th transistor M11 has the function of lowering the potential of the first output terminal G.

[0070] Note that while this example shows the gate of the 11th transistor M11 connected to the reset terminal Reset, the gate of the 11th transistor M11 does not necessarily have to be connected to the reset terminal Reset. The gate of the 11th transistor M11 only needs to be supplied with a signal output from another stage that is high level during the bootstrap release period or reset period. For example, it can be supplied with a scan signal G or signal Q that is connected to the first output terminal G or second output terminal Q of a stage after that stage and is high level during the bootstrap release period or reset period.

[0071] The gate of the 10th transistor M10 is electrically connected to the second internal node netB. The drain of the 10th transistor M10 is electrically connected to the second output terminal Q. The source of the 10th transistor M10 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). The 10th transistor M10 has the function of maintaining the potential of the second output terminal Q at a low level during the non-selective period and constitutes a stabilization circuit SC.

[0072] Figure 7 is an example of a timing chart to explain the operation of the shift register circuit SRB. As shown in Figure 7, in the shift register circuit SRB, the signal Q that drives the other stage is output from the second output terminal Q at the same timing as the scan signal G is output from the first output terminal G.

[0073] As described above, in the shift register circuit SRB, a second output terminal Q, which outputs a signal Q to drive other stages, is provided separately from the first output terminal G, which outputs a scan signal G. Since the capacitance connected to the second output terminal Q is smaller than the capacitance connected to the first output terminal G, which is electrically connected to the corresponding scan signal line GB, providing a second output terminal Q separately from the first output terminal G makes it possible to drive the gate drive circuit 120 at a higher speed.

[0074] Furthermore, in the shift register circuit SRB, during the period when the first internal node netA is at a low level and the second internal node netB is at a high level (the period before time t1 and the period after time t4), the 10th transistor M10 is turned ON, and the potential of the second output terminal Q is drawn to the potential Vs1 of the first reference voltage source. Therefore, the potential of the second output terminal Q can be more reliably maintained at a low level during the non-selective period. In addition, the shift register circuit SRB is provided with an 11th transistor M11, which allows the potential of the first output terminal G to be more reliably lowered to a low level. A signal that becomes high level during the bootstrap release period or reset period is applied to the gate of the 11th transistor M11, so the degradation of the characteristics of the 11th transistor M11 is suppressed during the non-selective period. Therefore, the function of the 11th transistor M11 in lowering the first output terminal G can be suitably maintained.

[0075] Figure 8 shows yet another example of a shift register circuit. The shift register circuit SRC shown in Figure 8 differs from the shift register circuit SRB shown in Figure 6 in that the sources of the fifth transistor M5 and the eleventh transistor M11 in each stage (Figure 8 illustrates the nth stage SRC(n)) are electrically connected to the third reference voltage terminal Vs3 (in other words, to the third reference voltage source). The potential Vs3 of the third reference voltage source is higher than the potential Vs1 of the first reference voltage source. Therefore, in the shift register circuit SRC, the first reference potential supplied to the source of the fourth transistor M4 and the second reference potential supplied to the source of the fifth transistor M5 are different potentials.

[0076] Figure 9 is an example of a timing chart to explain the operation of the shift register circuit SRC. As shown in Figure 9, in the shift register circuit SRC, the low level of the scan signal G during the set period (the period from time t1 to time t2) and the bootstrap release period (the period from time t3 to time t4) is even lower than the low level of the scan signal G during other periods (before time t1 and after time t4). In other words, the scan signal G undershoots before and after the bootstrap period (the period from time t2 to time t3). The undershoot of the scan signal G during the bootstrap release period allows for faster falling of the scan signal G, which in turn enables faster driving of the display device and improved display quality.

[0077] Figure 10 shows yet another example of a shift register circuit. Each stage of the shift register circuit SRB shown in Figure 6 has a single clock terminal CLK into which the clock signal is input. In contrast, each stage of the shift register circuit SRD shown in Figure 10 (Figure 10 illustrates the nth stage SRD(n)) has three clock terminals CLK(m), CLK(m-1), and CLK(m+1) into which the clock signal is input.

[0078] For the sake of explanation, in the following, the clock terminals CLK(m), CLK(m-1), and CLK(m+1) will be referred to as the "first clock terminal," "second clock terminal," and "third clock terminal," respectively, and the clock signals input to the clock terminals CLK(m), CLK(m-1), and CLK(m+1) will be referred to as the "first clock signal," "second clock signal," and "third clock signal," respectively.

[0079] The first clock terminal CLK(m) corresponds to the clock terminal CLK of the shift register circuit SRB shown in Figure 6, and is electrically connected to the drain of the first transistor M1 and the drain of the ninth transistor M9. Here, the first clock signal input to the first clock terminal CLK(m) is the m-th phase clock signal.

[0080] The second clock signal input to the second clock terminal CLK(m-1) is, in this case, the (m-1) phase clock signal and has a phase shift from the first clock signal.

[0081] The third clock signal input to the third clock terminal CLK(m+1) is, in this case, the (m+1)th phase clock signal, and has the opposite phase to the second clock signal.

[0082] Furthermore, the shift register circuit SRD differs from the shift register circuit SRB shown in Figure 6 in that each stage of the stabilization circuit SC has the 12th transistor M12 and the 13th transistor M13 instead of the 7th transistor M7.

[0083] The gate and drain of the 12th transistor M12 are diode-connected and electrically connected to the second clock terminal CLK(m-1). The source of the 12th transistor M12 is electrically connected to the second internal node netB. The 12th transistor M12 has the function of raising the potential of the second internal node netB.

[0084] The gate of transistor M13 is electrically connected to the third clock terminal CLK(m+1). The drain of transistor M13 is electrically connected to the second internal node netB. The source of transistor M13 is electrically connected to the second reference voltage terminal Vs2 (in other words, to the second reference voltage source). Transistor M13 has the function of lowering the potential of the second internal node netB.

[0085] Figure 11 is an example of a timing chart to explain the operation of the shift register circuit SRD. As shown in Figure 11, in the shift register circuit SRD, the rising and falling edges of the second internal node netB are periodically repeated during the non-selective period. In other words, the second internal node netB is AC. This reduces the load on the stabilizing element during the non-selective period, further suppressing the degradation of the stabilizing element's characteristics and improving reliability.

[0086] In this example, the second clock signal has a phase shift from the first clock signal, but the second clock signal may have the same phase as the first clock signal. Also, in this example, the third clock signal has the opposite phase to the second clock signal, but the third clock signal does not necessarily have to have the opposite phase to the second clock signal; it is sufficient if it has a phase shift from the second clock signal. Focusing on the selection period of that stage, the second clock signal is a signal that rises at the same time as or earlier than the rising edge of the first clock signal, and the third clock signal is a signal that rises at a later time than the rising edge of the first clock signal.

[0087] Figure 12 shows yet another example of a shift register circuit. The shift register circuit SRE shown in Figure 12 differs from the shift register circuit SRB shown in Figure 6 in that the stabilization circuit SC in each stage (Figure 12 illustrates the nth stage SRE(n)) has the 14th transistor M14, the 15th transistor M15, the 16th transistor M16, the 17th transistor M17, the 24th transistor M24, and the 25th transistor M25.

[0088] The aforementioned transistors M14 (14th), M15 (15th), M16 (16th), M17 (17th), M24 (24th), and M25 (25th) are electrically connected by a common node, netC. ​​This node, netC, will be referred to below as the "third internal node."

[0089] The gate of the 14th transistor M14 is electrically connected to the third internal node netC. ​​The drain of the 14th transistor M14 is electrically connected to the first internal node netA. The source of the 14th transistor M14 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). The 14th transistor M4 has the function of maintaining the potential of the first internal node netA at a low level during the non-selective period.

[0090] The gate of transistor M15 is electrically connected to the third internal node netC. ​​The drain of transistor M15 is electrically connected to the first output terminal G. The source of transistor M15 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). Transistor M15 has the function of maintaining the potential of the first output terminal G at a low level during the non-selective period.

[0091] When the potential supplied to the source of the 14th transistor M14 is called the "first reference potential" and the potential supplied to the source of the 15th transistor M15 is called the "second reference potential", in the example shown in Figure 12, since both the source of the 14th transistor M14 and the source of the 15th transistor M15 are electrically connected to the first reference voltage source, the first reference potential and the second reference potential are the same potential.

[0092] The gate of transistor M16 is electrically connected to the first internal node netA. The drain of transistor M16 is electrically connected to the third internal node netC. ​​The source of transistor M16 is electrically connected to the second reference voltage terminal Vs2 (in other words, to the second reference voltage source). Transistor M16 has the function of lowering the potential of the third internal node netC.

[0093] The gate and drain of transistor M17 are diode-connected and electrically connected via the charge supply terminal Vd' to a charge source for supplying charge to the third internal node netC. ​​The source of transistor M17 is electrically connected to the third internal node netC. ​​Transistor M17 has the function of raising the potential of the third internal node netC. ​​In the following description, the charge source for supplying charge to the second internal node netB may be referred to as the "first charge source," and the charge source for supplying charge to the third internal node netC may be referred to as the "second charge source."

[0094] The gate of transistor M24 is electrically connected to the set terminal Set. The drain of transistor M24 is electrically connected to the third internal node netC. ​​The source of transistor M24 is electrically connected to the second reference voltage terminal Vs2 (in other words, to the second reference voltage source). Transistor M24 turns on in response to the rising edge of the set signal Set and has the function of lowering the potential of the third internal node netC.

[0095] The gate of transistor M25 is electrically connected to the third internal node netC. ​​The drain of transistor M25 is electrically connected to the second output terminal Q. The source of transistor M25 is electrically connected to the first reference voltage terminal Vs1 (in other words, to the first reference voltage source). Transistor M25 has the function of maintaining the potential of the second output terminal Q at a low level during the non-selective period.

[0096] Figure 13 is an example timing chart illustrating the operation of the shift register circuit SRE. As shown in Figure 13, during the effective display period of one of two consecutive vertical scan periods, the potential Vd of the first charge source is high and the potential Vd' of the second charge source is low (i.e., the potential Vd of the first charge source is higher than the potential Vd' of the second charge source). Also, during the effective display period of the other of the two consecutive vertical scan periods, the potential Vd' of the second charge source is high and the potential Vd of the first charge source is low (i.e., the potential Vd' of the second charge source is higher than the potential Vd of the first charge source). In other words, in the shift register circuit SRE, a vertical scanning period alternates between a period in which the potential Vd of the first charge source is high and the potential Vd' of the second charge source is low during the effective display period, and a period in which the potential Vd' of the second charge source is high and the potential Vd of the first charge source is low during the effective display period.

[0097] Therefore, during the vertical scanning period when the potential Vd of the first charge source is high during the effective display period, the fourth transistor M4, fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, and eleventh transistor M11, which are electrically connected to the second internal node netB, function as a stabilization circuit. Also, during the vertical scanning period when the potential Vd' of the second charge source is high during the effective display period, the fourteenth transistor M14, fifteenth transistor M15, sixteenth transistor M16, seventeenth transistor M17, twenty-fourth transistor M24, and twenty-fifth transistor M25, which are electrically connected to the third internal node netC, function as a stabilization circuit.

[0098] The potential Vd' of the second charge source is lower than the potential Vs1 of the first reference voltage source for at least a portion of the vertical retrace period (a portion of the vertical retrace period in the example shown in Figure 13). Therefore, for at least a portion of the vertical retrace period (a portion of the vertical retrace period in the example shown in Figure 13), the potential of the third internal node netC is lower than the potential of the first internal node netA, the potential of the output terminal G(n), the first reference potential (here, the potential Vs1 of the first reference voltage source), and the second reference potential (here, the potential Vs1 of the first reference voltage source). For the same reasons as the fourth transistor M4 and fifth transistor M5, which are stabilizing elements controlled by the second internal node netB, characteristic degradation is suppressed for the 14th transistor M14 and the 15th transistor M15, which are stabilizing elements controlled by the third internal node netC.

[0099] Furthermore, as can be seen from the explanation already given, in the shift register circuit SRE shown in Figure 13, the stabilization circuit SC is divided into two systems, and one system and the other system function alternately, which further suppresses the degradation of the characteristics of the stabilization elements and can further improve reliability.

[0100] Figure 14 shows yet another example of a shift register circuit. The shift register circuit SRF shown in Figure 14 differs from the shift register circuit SRE shown in Figure 12 in that the stabilization circuit SC in each stage (Figure 14 illustrates the nth stage SRF(n)) has the 18th transistor M18, 19th transistor M19, 20th transistor M20, 21st transistor M21, 22nd transistor M22, and 23rd transistor M23 instead of the 6th transistor M6, 7th transistor M7, 8th transistor M8, 16th transistor M16, and 17th transistor M17.

[0101] The gate and drain of transistor 18 M18 are diode-connected and electrically connected via the charge supply terminal Vd to the first charge source for supplying charge to the second internal node netB. The source of transistor 18 M18 is electrically connected to the second internal node netB. Transistor 18 M18 has the function of raising the potential of the second internal node netB.

[0102] The gate and drain of transistor 19 M19 are diode-connected and electrically connected to the source of transistor 18 M18 (i.e., electrically connected to the second internal node netB). The source of transistor 19 M19 is electrically connected to the first charge source via the charge supply terminal Vd. Transistor 19 M19 has the function of lowering the potential of the second internal node netB during periods when the potential Vd of the first charge source is lower than the potential of the second internal node netB.

[0103] The gate and drain of transistor 20 M20 are diode-connected and electrically connected via the charge supply terminal Vd' to a second charge source for supplying charge to the third internal node netC. ​​The source of transistor 20 M20 is electrically connected to the third internal node netC. ​​Transistor 20 M20 has the function of raising the potential of the third internal node netC.

[0104] The gate and drain of transistor 21 M21 are diode-connected and electrically connected to the source of transistor 20 M20 (i.e., electrically connected to the third internal node netC). The source of transistor 21 M21 is electrically connected to the second charge source via the charge supply terminal Vd'. Transistor 21 M21 has the function of lowering the potential of the third internal node netC during periods when the potential Vd' of the second charge source is lower than the potential of the third internal node netC.

[0105] The gate of transistor M22 is electrically connected to the first internal node netA. The drain of transistor M22 is electrically connected to the second internal node netB. The source of transistor M22 is electrically connected to the third internal node netC. ​​Transistor M22 turns on in response to the rising edge of the first internal node netA, electrically connecting the second internal node netB and the third internal node netC.

[0106] The gate of transistor M23 is electrically connected to the set terminal Set. The drain of transistor M23 is electrically connected to the second internal node netB. The source of transistor M23 is electrically connected to the third internal node netC. ​​Transistor M23 turns on in response to the rising edge of the set signal Set, electrically connecting the second internal node netB and the third internal node netC.

[0107] Figure 15 is an example of a timing chart to illustrate the operation of the shift register circuit SRF. As shown in Figure 15, in one of two consecutive vertical scanning periods, the potential Vd of the first charge source is higher than the potential Vd' of the second charge source, and in the other effective display period, the potential Vd' of the second charge source is higher than the potential Vd of the first charge source. Then, vertical scanning periods in which the potential Vd of the first charge source is high and the potential Vd' of the second charge source is low in the effective display period alternate, and vertical scanning periods in which the potential Vd' of the second charge source is high and the potential Vd of the first charge source is low in the effective display period are repeated alternately.

[0108] Therefore, during the vertical scanning period when the potential Vd of the first charge source is high during the effective display period, the fourth transistor M4 and the fifth transistor M5, which are electrically connected to the second internal node netB, function as stabilizing elements. During the vertical scanning period when the potential Vd' of the second charge source is high during the effective display period, the fourteenth transistor M14 and the fifteenth transistor M15, which are electrically connected to the third internal node netC, function as stabilizing elements.

[0109] Thus, in the shift register circuit SRF shown in Figure 14, the stabilization circuit SC is doubled, resulting in improved reliability. Furthermore, since the second reference voltage signal Vs2 is not required in the shift register circuit SRF, the input signal can be reduced.

[0110] Furthermore, in the shift register circuit SRF shown in Figure 14, the potentials Vd of the first charge source and Vd' of the second charge source are lower than the potential Vs1 of the first reference voltage source for at least a portion of the vertical retrace period. Therefore, for at least a portion of the vertical retrace period, the potentials of the second internal node netB and the third internal node netC are lower than the potential of the first internal node netA, the potential of the output terminal G(n), the first reference potential (here, the potential Vs1 of the first reference voltage source), and the second reference potential (here, the potential Vs1 of the first reference voltage source). As a result, the characteristic degradation of the stabilizing elements, the fourth transistor M4, the fifth transistor M5, the fourteenth transistor M14, and the fifteenth transistor M15, is suppressed. [Industrial applicability]

[0111] According to embodiments of the present invention, a scanning signal line driving circuit can be provided that can suppress the degradation of the characteristics of the stabilization elements of the stabilization circuit provided in each stage of the shift register circuit. The scanning signal line driving circuit according to embodiments of the present invention is suitably used in display devices such as liquid crystal displays. [Explanation of symbols]

[0112] 100 LCD display device 110 Active Matrix Substrate 112 Opposing substrate 120 Scanning signal line drive circuit 140 Display signal line drive circuit P pixels AA Active Area (Display Area) GB scan signal line SB display signal line CLK clock terminal Set terminals Reset Reset terminal Vs1 First reference voltage terminal Vs2 Second reference voltage terminal Vs3 Third reference voltage terminal Vd, Vd' Charge supply terminal SR Shift Register Circuit netA 1st Internal Node netB 2nd Internal Node netC 3rd Internal Node M1 First Transistor M2 Second Transistor M3 Third Transistor M4 4th transistor M5 5th transistor M6 6th transistor M7 7th transistor M8 8th transistor M9 9th transistor M10 Transistor 10 M11 Transistor 11 M12 Transistor 12 M13 Transistor 13 M14 14th Transistor M15 Transistor 15 M16 Transistor 16 M17 Transistor 17 M18 Transistor 18 M19 Transistor 19 M20 Transistor 20 M21 Transistor 21 M22 Transistor 22 M23 Transistor 23 M24 Transistor 24 M25 Transistor 25

Claims

1. A scanning signal line driving circuit that supplies scanning signals to multiple scanning signal lines provided by a display device, It features a shift register circuit with multiple stages, Each of the aforementioned stages is The first clock terminal to which the first clock signal is input, A set terminal into which a set signal is input, The reset terminal to which the reset signal is input, A first output terminal that outputs a scanning signal, A first transistor having its gate electrically connected to a first internal node, one of its source and drain electrically connected to the clock terminal, and the other of its source and drain electrically connected to the first output terminal, A second transistor having its gate electrically connected to the set terminal and its source or drain electrically connected to the first internal node, A third transistor having its gate electrically connected to the reset terminal, one of its source and drain electrically connected to the first internal node, and the other of its source and drain electrically connected to a first reference voltage source, A stabilization circuit electrically connected to the first internal node and the first output terminal, which suppresses potential fluctuations of the first internal node and the first output terminal during the non-selective period, It has, The stabilization circuit is, A fourth transistor whose gate is electrically connected to a second internal node, whose source and drain are electrically connected to the first internal node, and to which a first reference potential is applied to the other source and drain, The system includes at least one of a fifth transistor, the gate of which is electrically connected to the second internal node, the source and drain of which one is electrically connected to the first output terminal, and the source and drain of which a second reference potential is provided, which is the same as or different from the first reference potential. A scanning signal line drive circuit is configured such that, during at least a portion of the vertical retrace period, which is part of the effective display period and the vertical retrace period included in the vertical scanning period, the potential of the second internal node is lower than the potential of the first internal node, the potential of the first output terminal, the first reference potential, and the second reference potential.

2. The stabilization circuit includes at least the fourth transistor among the fourth and fifth transistors, The source and the other drain of the fourth transistor are electrically connected to the first reference voltage source. The stabilization circuit is, The present invention further comprises a sixth transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to a second reference voltage source. The scanning signal line driving circuit according to claim 1, wherein the potential of the second reference voltage source is substantially the same as the potential of the first reference voltage source during the effective display period, and is lower than the potential of the first reference voltage source during at least a portion of the vertical retrace period.

3. The stabilization circuit is, The system further comprises a seventh transistor, one of which is electrically connected as a source and drain to a first charge source for supplying charge to the second internal node, and the other of which is electrically connected as a source and drain to the second internal node. The scanning signal line driving circuit according to claim 2, wherein the potential of the first charge source is lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period.

4. The stabilization circuit is, The scanning signal line drive circuit according to claim 2, further comprising an eighth transistor whose gate is electrically connected to the set terminal, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the second reference voltage source.

5. Each of the aforementioned stages is A second output terminal outputs a signal to drive other stages at the same timing as the scanning signal is output from the first output terminal, A ninth transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the clock terminal, and whose other source and drain are electrically connected to the second output terminal, The scanning signal line driving circuit according to claim 1, further comprising the above.

6. Each of the aforementioned stages is The scanning signal line driving circuit according to claim 5, further comprising a tenth transistor whose gate is electrically connected to the second internal node, whose source and drain are electrically connected to the second output terminal, and whose other source and drain are electrically connected to the first reference voltage source.

7. Each of the aforementioned stages is The scanning signal line driving circuit according to claim 1, further comprising an eleventh transistor to which a signal output from another stage is applied at the gate, one of its source and drain is electrically connected to the first output terminal, and the other of its source and drain is electrically connected to the first reference voltage source.

8. The stabilization circuit includes at least the fifth transistor among the fourth and fifth transistors, Each of the aforementioned stages is The present invention further comprises a tenth transistor whose gate is electrically connected to the second internal node, whose source and drain are electrically connected to the second output terminal, and whose other source and drain are electrically connected to the first reference voltage source. The source and the other drain of the fifth transistor are electrically connected to a third reference voltage source. The scanning signal line driving circuit according to claim 5, wherein the potential of the third reference voltage source is higher than the potential of the first reference voltage source.

9. Each of the aforementioned stages is The scanning signal line driving circuit according to claim 8, further comprising an eleventh transistor to which a signal output from another stage is applied to the gate, one of its source and drain is electrically connected to the first output terminal, and the other of its source and drain is electrically connected to the third reference voltage source.

10. The stabilization circuit includes both the fourth transistor and the fifth transistor, The scanning signal line driving circuit according to claim 1, wherein the other source and drain of the fourth transistor and the other source and drain of the fifth transistor are each electrically connected to the first reference voltage source, and the first reference potential and the second reference potential are the same.

11. Each of the aforementioned stages is A second clock terminal to which a second clock signal having the same phase as or a phase shifted from the first clock signal is input, A third clock terminal to which a third clock signal having a phase shifted from the second clock signal is input, It further possesses, The stabilization circuit is, A 12th transistor whose gate is electrically connected to the second clock terminal and whose source and drain are electrically connected to the second internal node, A thirteenth transistor whose gate is electrically connected to the third clock terminal, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the second reference voltage source, The scanning signal line driving circuit according to claim 2, further comprising the above.

12. The stabilization circuit is, A 14th transistor whose gate is electrically connected to a third internal node, whose source and drain are electrically connected to the first internal node, and to which the first reference potential is applied to the other source and drain, A 15th transistor whose gate is electrically connected to the third internal node, whose source and drain are electrically connected to the first output terminal, and to which the second reference potential is applied to the other source and drain, A 16th transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the third internal node, and whose other source and drain are electrically connected to the second reference voltage source, The present invention further comprises a 17th transistor, one of which is electrically connected as a source and drain to a second charge source for supplying charge to the third internal node, and the other of which is electrically connected as a source and drain to the third internal node. The potential of the second charge source is lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period. The scanning signal line driving circuit according to claim 3, wherein in the effective display period of one of two consecutive vertical scanning periods, the potential of the first charge source is higher than the potential of the second charge source, and in the other effective display period, the potential of the second charge source is higher than the potential of the first charge source.

13. The stabilization circuit is, A 14th transistor whose gate is electrically connected to a third internal node, whose source and drain are electrically connected to the first internal node, and to which the first reference potential is applied to the other source and drain, A 15th transistor whose gate is electrically connected to the third internal node, whose source and drain are electrically connected to the first output terminal, and to which the second reference potential is applied to the other source and drain, A 18th transistor, in which one of its source and drain is electrically connected to a first charge source for supplying charge to the second internal node, and the other of its source and drain is electrically connected to the second internal node, A 19th transistor having its gate and one of its source and drain electrically connected to the second internal node, and the other of its source and drain electrically connected to the first charge source, A 20th transistor, in which one of its source and drain is electrically connected to a second charge source for supplying charge to the third internal node, and the other of its source and drain is electrically connected to the third internal node, A 21st transistor having its gate and one of its source and drain electrically connected to the third internal node, and the other of its source and drain electrically connected to the second charge source, A 22nd transistor whose gate is electrically connected to the first internal node, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the third internal node, A 23rd transistor whose gate is electrically connected to the set terminal, whose source and drain are electrically connected to the second internal node, and whose other source and drain are electrically connected to the third internal node, It further possesses, The potential of the first charge source and the potential of the second charge source are lower than the potential of the first reference voltage source for at least a portion of the vertical retrace period. The scanning signal line driving circuit according to claim 3, wherein in the effective display period of one of two consecutive vertical scanning periods, the potential of the first charge source is higher than the potential of the second charge source, and in the other effective display period, the potential of the second charge source is higher than the potential of the first charge source.

14. It has multiple pixels arranged in a matrix that includes multiple pixel rows and multiple pixel columns, Each of the scan signal lines is associated with one of the aforementioned row of pixels, A scanning signal line driving circuit according to any one of claims 1 to 13, which supplies scanning signals to the plurality of scanning signal lines, A display device equipped with the following features.

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