Driver chip, display module, and display device

Abstract

A driver chip (300), a display module (10), and a display device (1). The display module (10) comprises: a display panel (100), a first gate driver circuit (201), and the driver chip (300). The first gate driver circuit (201) comprises a plurality of cascaded first shift registers (210), and signal output ends of the first shift registers (210) are electrically connected to reset control ends (Reset_H, Reset_H1, Reset_H2, Reset_P) of at least one reset sub-circuit in a pixel circuit (110). The driver chip (300) is configured to input a first clock signal to a clock signal end of the first gate driver circuit (201) within a refresh frame phase, and input a second clock signal to the clock signal end of the first gate driver circuit (201) within a holding frame phase, wherein the frequency of the second clock signal is less than the frequency of the first clock signal.

Description

Driver chips, display modules and display devices Cross-references to related applications

[0001] This application claims priority to Chinese patent application No. 202411750149.1, filed on November 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a driver chip, display module and display device. Background Technology

[0003] With the development of organic light-emitting display technology, the pixel circuits of display modules are gradually transitioning from LTPS (Low Temperature Poly-Silicon) technology to LTPO (Low Temperature Polycrystalline Oxide) technology. However, compared to LTPS pixel circuits, LTPO pixel circuits require more gate driving circuits to complete the driving process, which can easily lead to an increase in the power consumption of the display module. Summary of the Invention

[0004] This disclosure provides a driver chip, a display module, and a display device through some embodiments, which helps to reduce the power consumption of the display module.

[0005] In a first aspect of this disclosure, a display module is provided, comprising: a display panel including a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including a light-emitting device and a pixel circuit electrically connected to the light-emitting device; a first gate driving circuit including a plurality of cascaded first shift registers, the signal output terminal of the first shift registers being electrically connected to a reset control terminal of at least one reset sub-circuit in the pixel circuit; and a driving chip electrically connected to the first gate driving circuit, the driving chip being configured to: in the case that the current display cycle includes a refresh frame phase and a hold frame phase, input a first clock signal to a clock signal terminal of the first gate driving circuit during the refresh frame phase; and input a second clock signal to a clock signal terminal of the first gate driving circuit during the hold frame phase, the frequency of the second clock signal being less than the frequency of the first clock signal.

[0006] In some embodiments, the hold frame phase includes a first time period, a second time period, and a third time period set sequentially. The second clock signal includes a first sub-clock signal, a second sub-clock signal, and a third sub-clock signal. The driver chip is configured to: input a first sub-clock signal to the clock signal terminal of the first gate driving circuit during the first time period, wherein the frequency of the first sub-clock signal is less than the frequency of the first clock signal; input a second sub-clock signal to the clock signal terminal of the first gate driving circuit during the second time period, wherein the frequency of the second sub-clock signal is greater than the frequency of the first sub-clock signal and less than the frequency of the first clock signal; and input a third sub-clock signal to the clock signal terminal of the first gate driving circuit during the third time period, wherein the frequency of the third sub-clock signal is less than the frequency of the second sub-clock signal.

[0007] In some embodiments, the first sub-clock signal and the third sub-clock signal are first constant-level signals, the voltage value of the first constant-level signal is approximately the same as the low-level voltage value of the first clock signal; the frequency of the second sub-clock signal is one-M times the frequency of the first clock signal, where M is an even number.

[0008] In some embodiments, the frequency of the second clock signal is one-N times the frequency of the first clock signal, where N is an even number.

[0009] In some embodiments, the display module further includes a light-emitting driving circuit, the signal output terminal of which is electrically connected to the light-emitting control terminal in the pixel circuit; the driving chip is electrically connected to the light-emitting driving circuit and configured to: input a first frame start signal to the signal input terminal of the first gate driving circuit and input a light-emitting frame start signal to the signal input terminal of the light-emitting driving circuit; wherein, when the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the first frame start signal is greater than or equal to the current refresh frequency of the display panel and less than or equal to the refresh frequency of the light-emitting frame start signal; or, the first frame start signal is a second constant level signal in the hold frame phase, and the voltage of the second constant level signal is approximately the same as the high-level voltage value of the first frame start signal.

[0010] In some embodiments, the refresh frame phase includes a refresh frame, the hold frame phase includes multiple hold frames, the first frame start signal starts from the refresh frame, and is refreshed once every at least one hold frame, so that the refresh frequency of the first frame start signal is greater than the current refresh frequency of the display panel and less than the refresh frequency of the light emission frame start signal.

[0011] In some embodiments, the pixel circuit includes a driving sub-circuit, a compensation sub-circuit, a data writing sub-circuit, a storage sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a third reset sub-circuit. The control terminal of the driving sub-circuit is connected to a first node, a first connection terminal is connected to a second node, and a second connection terminal is connected to a third node. The control terminal of the compensation sub-circuit is connected to a second scan control terminal, a first connection terminal is connected to the first node, and a second connection terminal is connected to the third node. The first connection terminal of the storage sub-circuit is connected to a first power supply voltage terminal, and a second connection terminal is connected to the first node. The control terminal of the first reset sub-circuit is connected to a first reset control terminal, a first connection terminal is connected to a first initial voltage terminal, and a second connection terminal is connected to the third node. The control terminal of the second reset sub-circuit is connected to a second reset control terminal, a first connection terminal is connected to a second initial voltage terminal, and a second connection terminal is connected to the light-emitting device. The anode; the control terminal of the third reset sub-circuit is connected to the third reset control terminal, and the first connection terminal is connected to the third initial voltage terminal; the control terminal of the data writing sub-circuit is connected to the first scan control terminal, and the first connection terminal is connected to the data voltage terminal; the second connection terminal of the data writing sub-circuit and the third reset sub-circuit is connected to the second node; the control terminals of the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are connected to the light-emitting control terminal; the first connection terminal of the first light-emitting control sub-circuit is connected to the first power supply voltage terminal, and the second connection terminal is connected to the second node; the first connection terminal of the second light-emitting control sub-circuit is connected to the third node, and the second connection terminal is connected to the anode of the light-emitting device. At least one of the first reset control terminal, the second reset control terminal, and the third reset control terminal is electrically connected to the signal output terminal of the first shift register.

[0012] In some embodiments, the signal output terminal of the first shift register is electrically connected to the first reset control terminal, the second reset control terminal, and the third reset control terminal, respectively.

[0013] In some embodiments, the signal output terminal of the first shift register is electrically connected to the second reset control terminal and the third reset control terminal, respectively. The display module further includes a second gate driving circuit, which includes a plurality of cascaded second shift registers. The signal output terminal of the second shift register is electrically connected to the first reset control terminal. The driving chip is electrically connected to the second gate driving circuit and is configured to: input a third clock signal to the clock signal terminal of the second gate driving circuit during the refresh frame phase; and input a fourth clock signal to the clock signal terminal of the second gate driving circuit during the hold frame phase, wherein the frequency of the fourth clock signal is less than the frequency of the third clock signal and the frequency of the second clock signal.

[0014] In some embodiments, the driver chip is further configured to: input a first frame start signal to the signal input terminal of the first gate driving circuit, and input a second frame start signal to the signal input terminal of the second gate driving circuit. Wherein, if the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the second frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal and the second frame start signal are a second constant-level signal during the hold frame phase, and the voltage of the second constant-level signal is approximately the same as the high-level voltage value of the first frame start signal.

[0015] In some embodiments, the signal output terminal of the first shift register is electrically connected to the third reset control terminal. The display module further includes a second gate driving circuit and a third gate driving circuit. The second gate driving circuit includes a plurality of cascaded second shift registers, and the signal output terminal of the second shift register is electrically connected to the first reset control terminal. The third gate driving circuit includes a plurality of cascaded third shift registers, and the signal output terminal of the third shift register is electrically connected to the second reset control terminal. The driving chip is electrically connected to the second gate driving circuit and the third gate driving circuit respectively, and is configured to: input a third clock signal to the clock signal terminal of the second gate driving circuit and input a fifth clock signal to the clock signal terminal of the third gate driving circuit during the refresh frame phase; and input a fourth clock signal to the clock signal terminal of the second gate driving circuit and input a sixth clock signal to the clock signal terminal of the third gate driving circuit during the hold frame phase. Wherein, the frequency of the fourth clock signal is less than the frequency of the third clock signal, the frequency of the sixth clock signal is less than the frequency of the fifth clock signal, and the frequencies of the fourth clock signal and the sixth clock signal are less than or equal to the frequency of the second clock signal.

[0016] In some embodiments, the driver chip is further configured to: input a first frame start signal to the signal input terminal of the first gate driving circuit, input a second frame start signal to the signal input terminal of the second gate driving circuit, and input a third frame start signal to the signal input terminal of the third gate driving circuit. Wherein, if the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the second frame start signal and the third frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal, the second frame start signal, and the third frame start signal are second constant-level signals during the hold frame phase, and the voltage of the second constant-level signal is approximately the same as the high-level voltage value of the first frame start signal.

[0017] In some embodiments, the display module further includes: a fourth gate driving circuit, comprising a plurality of cascaded fourth shift registers, the signal output terminal of which is electrically connected to the first scan control terminal; a fifth gate driving circuit, comprising a plurality of cascaded fifth shift registers, the signal output terminal of which is electrically connected to the second scan control terminal; a light-emitting driving circuit, comprising a plurality of cascaded sixth shift registers, the signal output terminal of which is electrically connected to the light-emitting control terminal; and the driving chip is electrically connected to the fourth gate driving circuit, the fifth gate driving circuit, and the light-emitting driving circuit, respectively.

[0018] In some embodiments, the substrate includes a display area, a first border area, and a second border area. The first border area is located on a first side of the display area, and the second border area is located on a second side of the display area. The first side and the second side are opposite sides. The plurality of sub-pixels are located in the display area. A fourth gate driving circuit is disposed in the first border area and the second border area. A fifth gate driving circuit, a first gate driving circuit, and a third gate driving circuit are disposed in the first border area. The fifth gate driving circuit is located on the side of the fourth gate driving circuit that is away from the display area, and the third gate driving circuit is located on the side of the fifth gate driving circuit that is away from the display area. The first gate driving circuit is located on the side of the third gate driving circuit that is away from the display area. A second gate driving circuit and a light-emitting driving circuit are disposed in the second border area. The second gate driving circuit is located on the side of the fourth gate driving circuit that is away from the display area, and the light-emitting driving circuit is located on the side of the second gate driving circuit that is away from the display area.

[0019] In a second aspect of this disclosure, a driver chip is provided, including a memory and a processor. The memory stores a computer program executable on the processor, the computer program being executed by the processor of the following steps: when the current display cycle includes a refresh frame phase and a hold frame phase, during the refresh frame phase, inputting a first clock signal to a clock signal terminal of a first gate driving circuit; during the hold frame phase, inputting a second clock signal to a clock signal terminal of the first gate driving circuit, the frequency of the second clock signal being less than the frequency of the first clock signal; wherein the first gate driving circuit includes a plurality of cascaded first shift registers, the signal output terminals of the first shift registers being electrically connected to a reset control terminal of at least one reset sub-circuit in the pixel circuit of the display panel.

[0020] In a third aspect of this disclosure, a display device is provided, including the display module provided in the first aspect.

[0021] The above description is merely an overview of the technical solutions of some embodiments of this disclosure. In order to better understand the technical means of the embodiments of this disclosure and to implement them in accordance with the contents of the specification, and to make the embodiments of this disclosure more obvious and easy to understand, specific implementation methods of some embodiments of this disclosure are given below. Attached Figure Description

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the embodiments disclosed herein. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0023] Figure 1 shows a schematic diagram of the structure of a display device according to some embodiments of the present disclosure;

[0024] Figure 2 shows a plan view of a display panel according to some embodiments of the present disclosure;

[0025] Figure 3 shows a schematic diagram of the driving architecture of a display module according to some embodiments of the present disclosure;

[0026] Figure 4 shows a schematic diagram of the pixel circuit structure of some embodiments of the present disclosure;

[0027] Figure 5 shows a circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0028] Figure 6 shows a timing diagram of a first gate drive circuit according to some embodiments of the present disclosure;

[0029] Figure 7 shows a timing diagram of a first gate drive circuit according to some other embodiments of the present disclosure;

[0030] Figure 8 shows timing diagrams of light-emitting frame start signals and three exemplary first frame start signals according to some embodiments of the present disclosure;

[0031] Figure 9 shows a circuit diagram of a first shift register according to some embodiments of the present disclosure;

[0032] Figure 10 shows an exemplary timing diagram of the pixel circuitry in Figure 5 during frame refresh;

[0033] Figure 11 shows a circuit diagram of a pixel circuit according to some other embodiments of the present disclosure;

[0034] Figure 12 shows a circuit diagram of a second shift register according to some embodiments of the present disclosure;

[0035] Figure 13 shows an exemplary timing diagram of the pixel circuitry in Figure 11 during frame refresh;

[0036] Figure 14 shows a timing diagram of a second gate drive circuit according to some embodiments of the present disclosure;

[0037] Figure 15 shows a timing diagram of a second gate drive circuit according to some other embodiments of the present disclosure;

[0038] Figure 16 shows a circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0039] Figure 17 shows an exemplary timing diagram of the pixel circuitry in Figure 16 during frame refresh;

[0040] Figure 18 shows a timing diagram of a third gate drive circuit according to some embodiments of the present disclosure;

[0041] Figure 19 shows a timing diagram of a third gate drive circuit according to some other embodiments of the present disclosure;

[0042] Figure 20 shows a schematic diagram of the gate drive circuit layout of some embodiments of the present disclosure; and

[0043] Figure 21 shows a timing diagram of the frame start signal according to some embodiments of the present disclosure. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0045] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “At least one” includes one or more cases. The terms “including,” “comprising,” or “contains,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “electrical connection,” “connection,” or “linked,” and similar terms indicate an electrical connection, whether direct or indirect. “ / ” represents division, and “×” represents multiplication.

[0046] In some embodiments of this disclosure, the transistor can be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. In the embodiments of this disclosure, thin film transistors are used as an example for illustration.

[0047] In some embodiments of this disclosure, the control electrode of the transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first electrode and the second electrode of the transistor in some embodiments of this disclosure can be structurally indistinguishable. For example, the first electrode of the transistor can be the source, and the second electrode can be the drain.

[0048] In some embodiments of this disclosure, "operating level" refers to a voltage that enables the included operated transistor to conduct, and correspondingly, "non-operating level" refers to a level that prevents the included operated transistor from conducting (i.e., the transistor is turned off). Typically, the shift register uses a square wave pulse signal during operation, and the operating level corresponds to the level of the square wave pulse portion of the square wave pulse signal, while the non-operating level corresponds to the level of the non-square wave pulse portion.

[0049] In some embodiments of this disclosure, the first node, second node, third node, etc., do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0050] Figure 1 shows a schematic diagram of the structure of a display device according to some embodiments of the present disclosure. As shown in Figure 1, some embodiments of the present disclosure provide a display device 1, which can be any device that displays either moving (e.g., video) or fixed (e.g., still image) content, and whether it is text or an image. In some embodiments, the display device 1 can be a medium-to-large-sized display product such as a screen, television, laptop computer, or tablet computer. Of course, in other embodiments, the display device can also be a small-sized display product such as a mobile phone, personal digital assistant (PDA), or wearable device.

[0051] In some embodiments, the display device may be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, a micro light-emitting diode (Micro LED) display device, etc., and this disclosure does not specifically limit it.

[0052] In some embodiments, the display device may be a low-temperature polycrystalline oxide (LTPO) display device. LTPO display devices can support a variety of refresh rates, such as from 120 Hz to 1 Hz.

[0053] As shown in Figure 1, the display device 1 includes a display module 10. The display module 10 can be a foldable display module or a non-foldable display module, and this disclosure does not limit it.

[0054] In some embodiments, the display module 10 includes a display panel, a driver chip, and multiple gate driver circuits. It should be noted that the gate driver circuits can be integrated into the bezel area of ​​the display panel, or they can be set independently of the display panel. The gate driver circuit integrated on the display panel can be abbreviated as GOA (Gate Driver on Array).

[0055] Figure 2 shows a plan view of a display panel according to some embodiments of the present disclosure. As shown in Figure 2, the display panel 10 includes a substrate 101 and a plurality of sub-pixels p arranged in an array on the substrate 101. Each sub-pixel p includes a light-emitting device and a pixel circuit electrically connected to the light-emitting device, the pixel circuit being configured to drive the light-emitting device to emit light.

[0056] The substrate 101 may include a display area AA and a border area NA. The display area AA is the area on the display panel 100 used for displaying images, and the border area NA is the area on the display panel 100 other than the display area AA. The border area NA may be located on at least one side of the display area AA (e.g., one side, or multiple sides). For example, the border area NA may be arranged around the display area AA.

[0057] The display area AA is configured with sub-pixels p that emit multiple colors of light. For example, each sub-pixel can display a single color. For instance, sub-pixels emitting multiple colors of light may include a first sub-pixel emitting a first color of light, a second sub-pixel emitting a second color of light, and a third sub-pixel emitting a third color of light. The first, second, and third colors are the three primary colors, such as red, blue, and green.

[0058] Taking the arrangement shown in Figure 2 as an example, subpixels arranged in a row along the horizontal direction X can be called subpixels in the same row; subpixels arranged in a column along the vertical direction Y can be called subpixels in the same column. The display panel 10 also includes multiple gate lines and multiple data lines (not shown in the figure). The multiple gate lines and multiple data lines intersect each other to define multiple pixel areas distributed in an array in the display area. The gate lines are configured to connect the gate driving circuit and the pixel circuit, and the data lines are configured to transmit data voltage signals to the pixel circuit.

[0059] Figure 3 illustrates a schematic diagram of the driving architecture of a display module according to some embodiments of the present disclosure. As shown in Figure 3, the driving chip 300 is electrically connected to multiple sets of gate driving circuits 200 and configured to provide gate driving signals (also referred to as GOA signals) to the gate driving circuits 200. The multiple sets of gate driving circuits 200 are electrically connected to pixel circuits 110 respectively and configured to drive the pixel circuits 110 to control the light-emitting devices to emit light under the control of the gate driving signals. For example, the gate driving signals may include a frame start signal (STV), a clock signal (such as including at least one set of positive clock signals CK and negative clock signals CB), and a vertical external line (VEL) signal. The positive clock signal CK and the negative clock signal CB are square wave signals with alternating high and low levels. When the positive clock signal CK is low, the negative clock signal CB is high, and when the negative clock signal CB is low, the positive clock signal CK is high. In some embodiments, the high-level period and the low-level period of the positive clock signal CK may overlap with the low-level period and the high-level period of the negative clock signal CB, respectively. In other embodiments, the duration of the high-level period of the positive clock signal CK can be greater than the duration of the low-level period of the inverted clock signal CB, and the duration of the high-level period of the inverted clock signal CB can be greater than the duration of the corresponding low-level period of the positive clock signal CK. The high-level periods of the positive clock signal CK and the inverted clock signal CB can overlap. For example, when the positive clock signal CK is high, the inverted clock signal CB transitions from high to low for a certain duration before transitioning back to high. When the positive clock signal CK is low, the inverted clock signal CB is high. Conversely, when the inverted clock signal CB is high, the positive clock signal CK transitions from high to low for a certain duration before transitioning back to high. When the inverted clock signal CB is low, the positive clock signal CK is high.

[0060] In some embodiments, one driver chip 300 may be provided, and the aforementioned multiple sets of gate driving circuits 200 may be electrically connected to the same driver chip 300. In other embodiments, multiple driver chips 300 may be provided, and each driver chip 300 may be electrically connected to at least one set of gate driving circuits 200.

[0061] In some embodiments, the driver chip 300 can be a display driver integrated circuit (DDIC). In other embodiments, the driver chip 300 can also be a touch and display driver integration (TDDI). The number of gate drive circuits 200 included in the display module 1 is related to the pixel circuit 110 used. For example, for an LTPO pixel circuit, it can be driven by four sets of gate drive circuits 200, or by five sets of gate drive circuits 200, or even by six sets of gate drive circuits 200.

[0062] Figure 4 shows a schematic diagram of the structure of a pixel circuit according to some embodiments of the present disclosure. As shown in Figure 4, the pixel circuit 110 may include a storage sub-circuit 114, a driving sub-circuit 112, a compensation sub-circuit 113, a data writing sub-circuit 111, a first light emission control sub-circuit 115, a second light emission control sub-circuit 116, a first reset sub-circuit 117, a second reset sub-circuit 118, and a third reset sub-circuit 119.

[0063] The control terminal of the driving sub-circuit 112 is connected to the first node, the first connection terminal is connected to the second node, and the second connection terminal is connected to the third node. The control terminal of the compensation sub-circuit 113 is connected to the second scan control terminal Gate_N, the first connection terminal is connected to the first node, and the second connection terminal is connected to the third node. The first connection terminal of the storage sub-circuit 114 is connected to the first power supply voltage terminal ELVDD, and the second connection terminal is connected to the first node. The control terminal of the first reset sub-circuit 117 is connected to the first reset control terminal Reset1, the first connection terminal is connected to the first initial voltage terminal vinit1, and the second connection terminal is connected to the third node. The control terminal of the second reset sub-circuit 118 is connected to the second reset control terminal Reset2, the first connection terminal is connected to the second initial voltage terminal vinit2, and the second connection terminal is connected to the anode of the light-emitting device EL (i.e., connected to the fourth node N4 in Figure 4). The control terminal of the third reset sub-circuit 119 is connected to the third reset control terminal Reset3, and the first connection terminal is connected to the third initial voltage terminal vinit3. The control terminal of the data writing sub-circuit 111 is connected to the first scan control terminal Gate_P, and the first connection terminal is connected to the data voltage terminal. The second connection terminals of the data writing subcircuit 111 and the third reset subcircuit 119 are connected to the second node. The control terminals of the first light-emitting control subcircuit 115 and the second light-emitting control subcircuit 116 are connected to the light-emitting control terminal EM. The first connection terminal of the first light-emitting control subcircuit 115 is connected to the first power supply voltage terminal ELVDD, and the second connection terminal is connected to the second node. The first connection terminal of the second light-emitting control subcircuit 116 is connected to the third node, and the second connection terminal is connected to the anode of the light-emitting device EL. The cathode of the light-emitting device EL is connected to the second power supply voltage terminal VSS.

[0064] The first scan control terminal Gate_P receives the first scan signal, and the data writing sub-circuit 111 is configured to write data under the control of the first scan signal. The second scan control terminal Gate_N receives the second scan signal, and the compensation sub-circuit 113 is configured to compensate the threshold voltage of the transistors included in the driving sub-circuit 112 for the second scan signal. The first scan signal and the second scan signal have different operating levels. The light emission control terminal EM receives the light emission control signal, and the first light emission control sub-circuit 115 and the second light emission control sub-circuit 116 are configured to control the light emission of the light-emitting device EL based on the light emission control signal.

[0065] The first reset control terminal Reset1 receives a first reset signal. The first reset sub-circuit 117 is configured to write a first initial voltage Vinit1 to the third node N3 under the control of the first reset signal, thereby resetting the third node N3. The second reset control terminal Reset2 receives a second reset signal. The second reset sub-circuit 118 is configured to write a second initial voltage Vinit2 to the anode of the light-emitting device EL under the control of the second reset signal, thereby resetting the anode of the light-emitting device EL. The third reset control terminal Reset3 receives a third reset signal. The third reset sub-circuit 119 is configured to write a third initial voltage Vinit3 to the second node N2 under the control of the third reset signal, thereby resetting the second node N2.

[0066] The first scan control terminal Gate_P, the second scan control terminal Gate_N, and the light emission control terminal EM can be driven by three different gate driving circuits 200. The first reset control terminal Reset1, the second reset control terminal Reset2, and the third reset control terminal Reset3 can be the same reset control terminal, or they can be different reset control terminals. Correspondingly, the first reset signal, the second reset signal, and the third reset signal can be the same reset signal, or they can be different reset signals.

[0067] Figure 5 shows a circuit diagram of a pixel circuit according to some embodiments of the present disclosure. Figure 5 uses the example where the first reset control terminal Reset1, the second reset control terminal Reset2, and the third reset control terminal Reset3 are all the same reset control terminal Reset_H. As shown in Figure 5, the first reset sub-circuit 117 includes a first transistor T1, the compensation sub-circuit 113 includes a second transistor T2, the driving sub-circuit 112 includes a third transistor, the data writing sub-circuit 111 includes a fourth transistor T4, the first light-emitting control sub-circuit 115 includes a fifth transistor T5, the second light-emitting control sub-circuit 116 includes a sixth transistor T6, the second reset sub-circuit 118 includes a seventh transistor T7, the third reset sub-circuit 119 includes an eighth transistor T8, and the storage sub-circuit 114 includes a storage capacitor Cst1. This pixel circuit is an 8T1C pixel circuit utilizing LTPO technology, where the second transistor T2 is an N-type transistor such as an NMOS transistor, and the other transistors are P-type transistors such as PMOS transistors.

[0068] It should be noted that, for the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, one of the first and second terminals can be used as the first connection terminal of the respective sub-circuit, and the other can be used as the second connection terminal of the respective sub-circuit. The control terminal can be used as the control terminal of the respective sub-circuit.

[0069] In the pixel circuit corresponding to Figure 5, the function of the first reset sub-circuit 117 is to write the first initial voltage to the second terminal of the third transistor T3 (i.e., the third node N3 in Figure 5) during the reset phase to initialize the voltage of the second terminal of the third transistor T3. The magnitude of the first initial voltage Vinit1 affects the charging and discharging of the third node N3, thus affecting the afterimage effect. The first initial voltage Vinit1 is generally a negative voltage (i.e., less than 0). If the first initial voltage Vinit1 is too high (close to 0), it will affect the reset effect of the third transistor T3, thus affecting the afterimage effect and the display response time. If the first initial voltage Vinit1 is too negative, it will affect the voltage writing to the first node N1, resulting in a black state voltage V GMP Elevated levels can even produce bright spots in severe cases.

[0070] The function of the second reset circuit 118 is to write the second initial voltage Vinit2 into the anode of the light-emitting device EL (i.e., the fourth node N4 in Figure 5) before controlling the light-emitting device EL to emit light, so as to initialize the voltage of the anode of the light-emitting device EL, thereby improving the effect of the parasitic capacitance between the anode and cathode of the light-emitting device EL on the display.

[0071] The function of the third reset circuit 119 is to write the third initial voltage Vinit3 into the first terminal of the third transistor T3 (i.e., the second node N2 in Figure 5) during the reset phase to initialize the voltage of the first terminal of the third transistor T3, thereby improving the flickering (VRR) problem during refresh frequency switching. It is understandable that due to the hysteresis of the third transistor T3, the brightness of the display panel is prone to change when the refresh frequency switches. Writing the third initial voltage Vinit3 into the first terminal of the third transistor T3 can increase the source voltage of the third transistor T3 during the refresh frame phase, increasing the threshold voltage (Vth) offset of the third transistor T3. This ensures that the threshold voltage offset of the third transistor T3 remains consistent between the refresh frame phase and the hold frame phase, improving the problem of brightness changes when the display panel switches between different refresh frequencies, i.e., improving the VRR problem.

[0072] In related technologies, LTPO (Low-Temperature Point of Sale) technology is used to reduce the power consumption of display panels. In some applications, the display panel can switch refresh rates. One method of switching is to reduce the refresh rate from the base refresh rate (base frequency), typically by multiples thereof. Reducing the refresh rate by multiples is called frame interpolation frequency modulation. In frame interpolation, the display cycle of the base refresh rate includes refresh frames. The display cycle after reducing the refresh rate from the base refresh rate includes a refresh frame phase and a skip frame phase. The refresh frame phase includes refresh frames, and the skip frame phase includes at least one skip frame. The refresh frames and skip frames have the same duration. In other words, the refresh rate of the display panel is reduced by inserting skip frames between adjacent refresh frames. The reduction factor is changed by varying the number of skip frames inserted between adjacent refresh frames. For example, if the base refresh rate is 120Hz, inserting one skip frame reduces the refresh rate to 60Hz, inserting two skip frames reduces the refresh rate to 40Hz, and so on. Switching between two different refresh rates can be between a base refresh rate and a refresh rate that is downclocked from the base refresh rate, or it can be between two refresh rates that are downclocked from the same base refresh rate.

[0073] When the display cycle includes a refresh frame phase and a hold frame phase, the display panel completes the data writing of all rows of pixel circuits in the first refresh frame of the display cycle (e.g., 1 second). No new data is written in the subsequent hold frames. Each pixel circuit still controls the light-emitting device EL to emit light according to the voltage on its storage capacitor Cst1 and the light-emitting control signal, thereby keeping the display panel in the refresh frame display state.

[0074] The display module provided in some embodiments of this disclosure, when the display cycle includes a refresh frame stage and a hold frame stage, reduces the power consumption of the display module by down-frequency reducing the clock signal of the gate drive circuit connected to at least one reset sub-circuit in the pixel circuit during the hold frame stage, thereby reducing the power consumption of the gate drive circuit and the drive chip.

[0075] In some embodiments, the aforementioned multiple gate driving circuits 200 include a first gate driving circuit. The first gate driving circuit includes a plurality of cascaded first shift registers. The signal output terminal of the first shift register is electrically connected to the reset control terminal of at least one reset sub-circuit in the pixel circuit. For example, a first-level first shift register is electrically connected to at least one reset sub-circuit of a row of sub-pixels via a gate line. For example, the number of reset sub-circuits included in the pixel circuit can be set according to the needs of the actual product.

[0076] Taking the pixel circuit corresponding to Figure 4 as an example, the signal output terminal of the first shift register can be electrically connected to the reset control terminal of at least one of the first reset sub-circuit 117, the second reset sub-circuit 118, and the third reset sub-circuit 119. For example, it can be electrically connected to the reset control terminal of any one of the three reset sub-circuits, or simultaneously electrically connected to the reset control terminals of two of the reset sub-circuits, or electrically connected to the reset control terminals of each of the three reset sub-circuits.

[0077] The first gate driving circuit is electrically connected to the driving chip 300, which provides it with driving signals, such as clock signals and frame start signals. In some embodiments, the driving chip 300 is configured to, when the current display cycle includes a refresh frame phase and a hold frame phase, input a first clock signal to the clock signal terminal of the first gate driving circuit during the refresh frame phase; and input a second clock signal to the aforementioned clock signal terminal of the first gate driving circuit during the hold frame phase, wherein the frequency of the second clock signal is lower than the frequency of the first clock signal. It should be noted that, for ease of explanation, some embodiments of this disclosure refer to the clock signal received by the first gate driving circuit during the refresh frame phase of the same display cycle as the first clock signal, and the clock signal received during the hold frame phase as the second clock signal. It is understood that for the gate driving circuit, the higher the frequency of the input clock signal, the more times the transistor controlled by the clock signal in the gate driving circuit switches between switching states, resulting in higher energy consumption. Therefore, by down-frequency reducing the clock signal input to the first gate driving circuit during the hold frame phase compared to the refresh frame phase, the power consumption of the first gate driving circuit can be effectively reduced, and the power consumption of the driving chip 300 can also be reduced.

[0078] During the same display cycle, the clock signal received by at least one clock signal terminal of the first gate driving circuit has a lower frequency during the hold frame phase than during the refresh frame phase. The clock signal of the first gate driving circuit includes at least one set of mutually cooperating positive clock signal HCK and negative clock signal HCB. The positive clock signal HCK and negative clock signal HCB are transmitted to different clock signal terminals of the first gate driving circuit via different clock signal lines.

[0079] In some embodiments, the first clock signal may include a positive clock signal HCK and an inverted clock signal HCB for the refresh frame phase, and the second clock signal may include a positive clock signal HCK and an inverted clock signal HCB for the hold frame phase. For ease of distinction, the positive clock signal HCK for the refresh frame phase is referred to as HCK1, the inverted clock signal HCB for the refresh frame phase is referred to as HCB1, the positive clock signal HCK for the hold frame phase is referred to as HCK2, and the inverted clock signal HCB for the hold frame phase is referred to as HCB2. It is understood that HCK1 and HCK2 are clock signals transmitted on the same clock signal line for different time periods (i.e., the refresh frame phase and the hold frame phase), and HCB1 and HCB2 are clock signals transmitted on the same clock signal line for different time periods (i.e., the refresh frame phase and the hold frame phase). For example, the frequency of HCK2 may be less than the frequency of HCK1, and the frequency of HCB2 may be less than the frequency of HCB1.

[0080] In some other embodiments, the first clock signal may include the positive clock signal HCK during the refresh frame phase, and the second clock signal may include the positive clock signal HCK during the hold frame phase. The frequency of the positive clock signal HCK received by the first gate drive circuit during the hold frame phase may be less than the frequency of the positive clock signal HCK received during the refresh frame phase.

[0081] In some other embodiments, the first clock signal may include the inverted clock signal HCB of the refresh frame phase, and the second clock signal may include the inverted clock signal HCB of the hold frame phase. The frequency of the inverted clock signal HCB received by the first gate drive circuit in the hold frame phase may be less than the frequency of the inverted clock signal HCB received in the refresh frame phase.

[0082] There are several ways to downclock the clock signal of the first gate drive circuit during the hold frame stage. The goal is to ensure that the image on the display panel remains unchanged during the hold frame stage. Three exemplary downclocking methods are described below.

[0083] In the first case, the frequency of the second clock signal can be one-N times the frequency of the first clock signal. For example, N can be an even number. For example, if the frequency of the first clock signal is represented as f0, the frequency of the second clock signal can be 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, or 1 / 64 of f0, etc., as long as it can ensure the normal output of the first gate driving circuit. Figure 6 shows a timing diagram of the first gate driving circuit of some embodiments of this disclosure. Taking one display cycle as an example in Figure 6, the display cycle includes a refresh frame stage and a hold frame stage. The clock signal of the first gate driving circuit includes a set of positive clock signals HCK and negative clock signals HCB. The first clock signal includes the positive clock signal HCK and negative clock signal HCB of the refresh frame stage, and the second clock signal includes the positive clock signal HCK and negative clock signal HCB of the hold frame stage; HSTV represents the frame start signal of the first gate driving circuit; HOUT represents the output signal of the first gate driving circuit. As shown in Figure 6, after the refresh frame phase ends, the frequency of the positive clock signal HCK of the first gate drive circuit can be adjusted to one-N times that of the refresh frame phase, and the frequency of the negative clock signal HCB can also be adjusted to one-N times that of the refresh frame phase, and the adjusted frequencies can be maintained throughout the hold frame phase.

[0084] The second approach, to achieve a smoother frequency reduction, can include a transition sub-stage and a maintenance sub-stage in the hold frame phase. The transition sub-stage is located between the refresh frame phase and the maintenance sub-stage. In the transition sub-stage, the frequency of the second clock signal gradually decreases from the refresh frame phase frequency to the target frequency, and the target frequency is maintained in the maintenance sub-stage. For example, the target frequency can be 1 / L0 times the refresh frame phase frequency. The transition sub-stage can set one or more transition frequencies. Taking two transition frequencies as an example, in the transition sub-stage, the frequency of the second clock signal first decreases to 1 / L1 times the refresh frame phase frequency, then decreases from 1 / L1 times to 1 / L2 times the refresh frame phase frequency, and finally decreases to 1 / L0 times the refresh frame phase frequency in the maintenance sub-stage. For example, L0, L1, and L2 can be even numbers, with L0 > L2 > L1.

[0085] The third type involves a second clock signal with a frequency lower than that of the first clock signal, and the frequency of the second clock signal changes dynamically. For example, the hold frame stage includes a first time period, a second time period, and a third time period set sequentially. The second clock signal includes a first sub-clock signal, a second sub-clock signal, and a third sub-clock signal. The driver chip 300 is configured to: input the first sub-clock signal to the clock signal terminal of the first gate driving circuit during the first time period, where the frequency of the first sub-clock signal is lower than the frequency of the first clock signal; input the second sub-clock signal to the clock signal terminal of the first gate driving circuit during the second time period, where the frequency of the second sub-clock signal is higher than the frequency of the first sub-clock signal but lower than the frequency of the first clock signal; and input the third sub-clock signal to the clock signal terminal of the first gate driving circuit during the third time period, where the frequency of the third sub-clock signal is lower than the frequency of the second sub-clock signal. In other words, the first sub-clock signal is the clock signal received by the first gate driving circuit during the first time period, the second sub-clock signal is the clock signal received by the first gate driving circuit during the second time period, and the third sub-clock signal is the clock signal received by the first gate driving circuit during the third time period. For example, the frequencies of the first and third sub-clock signals can be 1 / 8 times f0, and the frequency of the second sub-clock signal can be 1 / 4 times f0.

[0086] In some embodiments, to further reduce the power consumption caused by frequent switching of the transistors in the first gate drive circuit, the first sub-clock signal and the third sub-clock signal can be a first constant-level signal, that is, the frequency of the first sub-clock signal and the third sub-clock signal is reduced to zero. The voltage value of the first constant-level signal can be approximately the same as the low-level voltage value of the first clock signal. The frequency of the second sub-clock signal is one-M times the frequency of the first clock signal, where M is an even number. It should be noted that "approximately the same" in this document includes both completely identical and approximately identical, where approximately identical means that the difference between the two is within an acceptable deviation range.

[0087] It should be noted that within the same display cycle, the durations of the first time period, the second time period, and the third time period, as well as the duration of the refresh frame phase, can be set according to the needs of the actual application scenario. Figure 7 shows a timing diagram of the first gate driving circuit of some other embodiments of this disclosure. In Figure 7, taking the example of switching the refresh frequency of the display panel from 60Hz (i.e., updating display data 60 times per second) to 1Hz (i.e., updating display data once per second) by inserting 59 skip frames between two adjacent refresh frames, a display cycle may include one refresh frame and 59 skip frames. The duration of the refresh frame phase is 1 / 60 of a second, and the total duration of the skip frame phase is 59 × (1 / 60) seconds. Based on this, the 59 skip frames are divided into a first time period, a second time period, and a third time period. In some embodiments, the first time period may include a series of consecutive skip frames following and adjacent to the refresh frame, the second time period may include a series of consecutive skip frames following and adjacent to the last skip frame of the first time period, and the third time period may include the remaining skip frames of the display cycle. For example, the duration of the first and third time periods can be longer than the duration of the second time period to minimize power consumption. Alternatively, the duration of the first and third time periods can be the same or different, depending on the specific application scenario.

[0088] For example, as shown in Figure 7, the first time period can be the 1st to 20th hold frames (20 frames), the second time period can be the 21st to 39th hold frames (19 frames), and the third time period can be the 40th to 59th hold frames (20 frames). Correspondingly, the duration of the first time period is 20 × (1 / 60) seconds, the duration of the second time period is 19 × (1 / 60) seconds, and the duration of the third time period is 20 × (1 / 60) seconds. It should be noted that the 19 frames in the middle of the hold frame stage in Figure 7 only show the timing of one hold frame out of these 19 hold frames.

[0089] As shown in Figure 7, after the refresh frame phase ends, the positive clock signal HCK and the negative clock signal HCB of the first gate drive circuit are pulled low to a low level, and these two clock signals are maintained at this low level for the first time period, that is, the frequency of the positive clock signal HCK and the negative clock signal HCB is reduced to the limit during the first time period. For example, the low-level voltage here can be a first voltage VGL. After the first time period ends, the frequency of the positive clock signal HCK and the negative clock signal HCB is adjusted to one-M times the refresh frame phase frequency, for example, it can be 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, or 1 / 64 times the refresh frame phase frequency, and the positive clock signal HCK and the negative clock signal HCB maintain the adjusted frequency during the second time period. At the end of the second time period, the positive clock signal HCK and the negative clock signal HCB are pulled low again and maintained at a low level during the third time period.

[0090] In some embodiments, at least one of the first time period, the second time period, and the third time period may respectively include a transition sub-time period and a maintenance sub-time period. The transition sub-time period is located between the previous time period and the maintenance sub-time period. During the transition sub-time period, the frequency of the corresponding sub-clock signal is gradually adjusted from the frequency of the previous time period to the target frequency of the current time period. Taking the second time period, which includes a transition sub-time period and a maintenance sub-time period, as an example, assuming that the target frequency of the second time period is 1 / 2 times the refresh frame stage frequency, and the clock signal of the first time period (i.e., the first sub-clock signal) is a first constant level signal, during the transition sub-time period, the second sub-clock signal can be adjusted from the first constant level signal to a high / low level signal with a frequency of 1 / 8 times that of the refresh frame stage, then adjusted from 1 / 8 times to 1 / 4 times, and then adjusted from 1 / 4 times to 1 / 2 times, and the adjusted frequency is maintained during the maintenance sub-time period.

[0091] It is understood that, in addition to providing a clock signal to the first gate driving circuit, the driver chip 300 is also configured to provide a frame start signal to the first gate driving circuit. In some embodiments, besides downclocking the clock signal of the first gate driving circuit during the hold frame phase, the refresh frequency of the frame start signal of the first gate driving circuit can also be reduced when the display panel switches from a high refresh frequency to a low refresh frequency. This reduces the refresh frequency of the reset control terminal driven by the first gate driving circuit, effectively reducing the number of times the transistors included in the corresponding reset sub-circuit are switched during the hold frame phase, thereby further reducing the power consumption of the display module.

[0092] The aforementioned multiple gate driving circuits 200 further include a light-emitting driving circuit, the signal output terminal of which is electrically connected to the light-emitting control terminal EM in the pixel circuit 110. The light-emitting driving circuit is electrically connected to the driving chip 300, which provides it with gate driving signals, such as clock signals and frame start signals. For ease of distinction, the frame start signal of the first gate driving circuit will be referred to as the first frame start signal, and the frame start signal of the light-emitting driving circuit will be referred to as the light-emitting frame start signal.

[0093] In some embodiments, the driver chip 300 is configured to: input a first frame start signal to the signal input terminal of the first gate driving circuit, and input a light emission frame start signal to the signal input terminal of the light emission driving circuit. Wherein, in the case that the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the first frame start signal is greater than or equal to the current refresh frequency of the display panel, and less than or equal to the refresh frequency of the light emission frame start signal.

[0094] It is understandable that, in the case that the current display cycle includes a refresh frame phase and a hold frame phase, the current refresh rate of the display panel is less than the aforementioned basic refresh rate. In order for the display panel to maintain the display state of the refresh frame phase during the hold frame phase, the refresh rate of the light emission control signal is consistent with the basic refresh rate.

[0095] In some embodiments, the refresh frequency of the first frame start signal can be greater than or equal to the current refresh frequency of the display panel, and less than the refresh frequency of the light-emitting frame start signal. For example, the current refresh frequency of the display panel is a first refresh frequency, the refresh frequency of the first frame start signal is a second refresh frequency, and the refresh frequency of the light-emitting frame start signal is a third refresh frequency. The first refresh frequency is less than the base refresh frequency, and the third refresh frequency is equal to the base refresh frequency. Based on the second refresh frequency being greater than or equal to the first refresh frequency, the second refresh frequency can be 1 / K times the third refresh frequency, where K is an even number; for example, it can be 1 / 2 times, 1 / 4 times, or 1 / 6 times, etc.

[0096] In some embodiments, the refresh frame phase includes a refresh frame, and the hold frame phase includes multiple hold frames. The first frame start signal can start from the refresh frame and is refreshed once every at least one hold frame, such that the refresh frequency of the first frame start signal is greater than the current refresh frequency of the display panel and less than the refresh frequency of the light emission frame start signal. The first frame start signal maintains a second constant level signal in the intervald hold frames. When the reset sub-circuit driven by the first gate drive circuit is high-level off, the voltage of the second constant level signal can be approximately the same as the high-level voltage value of the first frame start signal. For example, the voltage of the second constant level signal can be a second voltage VGH, which is greater than the first voltage VGL. That is, the first frame start signal maintains the second voltage VGH in the unrefreshed hold frames.

[0097] Figure 8 shows timing diagrams of the light-emitting frame start signals and three exemplary first frame start signals according to some embodiments of this disclosure. Figure 8 uses a base refresh frequency of 60Hz and an adjusted current refresh frequency of 1Hz as an example. The display period includes 60 frames, each frame lasting 1 / 60 second. The first frame is the refresh frame, and frames 2 through 60 are hold frames. ESTV represents the light-emitting frame start signal, which is refreshed in each of the 1st through 60th frames, i.e., it jumps to the operating level to control the light-emitting device EL to continuously emit light during the hold frames. Even without downclocking the first frame start signal, it is also refreshed in each of the 1st through 60th frames, i.e., the refresh frequency is the same as the light-emitting frame start signal, as shown by signal HSTV1 in Figure 8. When the frequency of the first frame start signal is reduced by half, the first frame start signal can be refreshed in the 1st frame (i.e., refresh frame), 3rd frame, 5th frame, ... 59th frame of the display cycle, and maintain a second constant level signal in the other hold frames. That is, it is refreshed once every other hold frame starting from the refresh frame. In other words, the refresh frequency of the first frame start signal is reduced to half of the light-emitting frame start signal, as shown by signal HSTV2 in Figure 8. When the frequency of the first frame start signal is reduced by 1 / 4, the first frame start signal can be refreshed in the 1st frame (i.e., refresh frame), 5th frame, 9th frame, ... 57th frame of the display cycle, and maintain a second constant level signal in the other hold frames. That is, it is refreshed once every three hold frames starting from the refresh frame. In other words, the refresh frequency of the first frame start signal is reduced to 1 / 4 of the light-emitting frame start signal, as shown by signal HSTV3 in Figure 8.

[0098] It should be noted that in the holding frames where the first frame start signal is refreshed, the frequency of the second clock signal is greater than zero. Taking a 1 / 4 frequency reduction of the first frame start signal as an example, during the holding frame stage, the frequency of the second clock signal is greater than zero at least in the 5th, 9th, ... 57th frames. In some embodiments, in the holding frames where the first frame start signal is not refreshed, the second clock signal can be a first constant level signal. In the holding frames where the first frame start signal is refreshed, the frequency of the second clock signal is greater than zero and less than the frequency of the first clock signal to ensure the output of the first shift register, thereby refreshing the reset control terminal of the connected reset sub-circuit.

[0099] In other embodiments, the first frame start signal may also be a second constant level signal during the hold frame phase, so that the output signal of the first gate drive circuit remains at a high level during the hold frame phase, thereby making the driven reset sub-circuit in the off state during the hold frame phase, which helps to reduce the power consumption of the display module.

[0100] In some embodiments, to reduce the number of gate drive circuits 200 to achieve a narrow bezel, the first gate drive circuit can be configured to simultaneously drive the first reset sub-circuit 117, the second reset sub-circuit 118, and the third reset sub-circuit 119. That is, the signal output terminal of the first shift register is electrically connected to the first reset control terminal, the second reset control terminal Reset2, and the third reset control terminal Reset3, respectively. For example, in the pixel circuit corresponding to FIG5, the gates of the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are connected to the same reset control terminal Reset_H and receive the same reset signal. In this case, the display module includes four groups of gate drive circuits.

[0101] Figure 9 shows a circuit diagram of a first shift register according to some embodiments of the present disclosure. Figure 9 is an exemplary circuit diagram of the first shift register when the number of gate drive circuits is four. As shown in Figure 9, the first shift register 210 may include 16 transistors, namely the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16, and three capacitors, namely C1, C2, and C3.

[0102] In this first shift register 210, the gates of the first transistor T1, the first terminal of the second transistor T2, the gates of the third transistor T3 and the fourteenth transistor T14, and the first terminals of the fourth transistor T4, the first terminal of the sixth transistor T6, and the gate of the seventh transistor T7 all serve as clock signal input terminals. The difference is that the clock signals input to the gates of the first transistor T1, the first terminal of the second transistor T2, the third transistor T3, and the fourteenth transistor T14, and the clock signals input to the first terminals of the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are respectively the positive-phase clock signal HCK and the negative-phase clock signal HCB. The input signals of the first shift register 210 also include a first frame start signal HSTV and a vertical synchronization signal VEL, and other power supply signal input terminals also input a first voltage VGL or a second voltage VGH. It should be noted that the circuit of the first shift register 210 shown in Figure 9 is only schematic; in other embodiments, other suitable shift register circuits may also be used.

[0103] Figure 10 shows an exemplary timing diagram of the pixel circuit in Figure 5 during frame refresh. As shown in Figure 10, the driving principle of the pixel circuit corresponding to Figure 5 is as follows:

[0104] During stage t1, when the light emission control signal provided by the light emission control terminal EM, the first scan signal provided by the first scan control terminal Gate_P, and the second scan signal provided by the second scan control terminal Gate_N are all at high level, and the reset signal provided by the reset control terminal Reset_H is at low level, transistors T1, T2, T7, and T8 in Figure 5 are all turned on, with transistors T7 and T8 turning on simultaneously first, followed by transistor T1; transistors T4, T5, and T6 are all turned off. Furthermore, the second initial voltage Vinit2 can be transmitted to the anode of the light-emitting device EL (i.e., the fourth node N4 in Figure 5) to reset the anode of the light-emitting device EL, meaning that the voltage of the fourth node N4 is equal to the second initial voltage Vinit2 at this time; the third initial voltage Vinit3 can be transmitted to the first terminal of the third transistor T3 (i.e., the second node N2 in Figure 5) to reset the first terminal of the third transistor T3, meaning that the voltage of the second node N2 is equal to the third initial voltage Vinit3 at this time; and the first initial voltage Vinit1 can be transmitted to the second terminal of the third transistor T3 (i.e., the third node N3 in Figure 5), and then transmitted through the second transistor T2 to the gate of the third transistor T3 (i.e., the first node N1 in Figure 5), meaning that the voltage of the first node N1 is equal to the first initial voltage Vinit1 at this time, resetting the first node N1. This t1 stage can also be called the first reset stage.

[0105] In stage t2, when the light emission control signal provided by the light emission control terminal EM, the second scan signal provided by the second scan control terminal Gate_N, and the reset signal provided by the reset control terminal Reset_H are all at high levels, and the first scan signal provided by the first scan control terminal Gate_P is at low level, transistors T2 and T4 in Figure 5 are both turned on, while transistors T1, T5, T6, T7, and T8 are all turned off. Under the holding effect of the storage capacitor Cst1, the gate of the third transistor T3 can initially maintain the first initial voltage of the previous stage, allowing the driving transistor T3 to remain on. Consequently, the data voltage signal output from the data voltage terminal Vata can be sequentially transmitted through transistors T4, T3, and T2 to the lower plate of the storage capacitor Cst1 and the gate of the third transistor T3, charging the storage capacitor Cst1 and updating the voltage at the gate of the third transistor T3 from the first initial voltage Vinit1 to the data voltage, causing the third transistor T3 to gradually turn off. This stage t2 can also be called the data writing stage.

[0106] In stage t3, when the light emission control signal provided by the light emission control terminal EM and the first scan signal provided by the first scan control terminal Gate_P are at high levels, and the reset signal provided by the reset control terminal Reset_H and the second scan signal provided by the second scan control terminal Gate_N are at low levels, transistors T1, T7, and T8 in Figure 5 are all turned on, and transistors T2, T4, T5, and T6 are all turned off, thereby resetting the second node N2, the third node N3, and the fourth node N4. This stage t3 can also be called the second reset stage.

[0107] During stage t4, when the reset signal provided by the reset control terminal Reset_H and the first scan signal provided by the first scan control terminal Gate_P are at high levels, and the light emission control signal provided by the light emission control terminal EM and the second scan signal provided by the second scan control terminal Gate_N are at low levels, transistors T5 and T6 in Figure 5 are turned on, while transistors T1, T2, T4, T7, and T8 are all turned off, thereby controlling the light-emitting device EL to emit light. This stage t4 can also be referred to as the light emission stage.

[0108] In other embodiments, the first gate drive circuit can be configured to drive the second reset sub-circuit 118 and the third reset sub-circuit 119, that is, the signal output terminal of the first shift register 210 is electrically connected to the second reset control terminal Reset2 and the third reset control terminal Reset3 in FIG4, respectively. The multiple gate drive circuits 200 also include a second gate drive circuit for driving the first reset sub-circuit 117, and the second gate drive circuit is electrically connected to the driver chip 300. The second gate drive circuit includes multiple cascaded second shift registers, and the signal output terminal of the second shift register is electrically connected to the first reset control terminal Reset1 in FIG4.

[0109] Figure 11 shows a circuit diagram of a pixel circuit according to some other embodiments of this disclosure. Unlike the pixel circuit corresponding to Figure 5, in Figure 11, the gates of the seventh transistor T7 and the eighth transistor T8 are connected to the same reset control terminal Reset_H, and the gate of the first transistor T1 is connected to the reset control terminal Reset_P. Two different gate drive circuits drive the two reset control terminals Reset_H and Reset_P respectively. That is, the second reset control terminal connected to the second reset sub-circuit 118 and the third reset control terminal connected to the third reset sub-circuit 119 are the same reset control terminal, and the first reset control terminal connected to the first reset sub-circuit 117 is another reset control terminal. In this case, the display module has five sets of gate drive circuits.

[0110] In some embodiments, the circuitry of the second shift register may differ from that of the first shift register, and the number of transistors in the second shift register may be less than the number of transistors in the first shift register. Figure 12 shows a circuit diagram of a second shift register according to some embodiments of the present disclosure. As shown in Figure 12, the second shift register 220 may include 13 transistors, namely, first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, and thirteenth transistor T13, and three capacitors, namely C1, C2, and C3. In this second shift register 220, the gates of the first transistor T1, the first terminal of the second transistor T2, the gates of the third transistor T3, the first terminals of the fourth transistor T4, the first terminal of the sixth transistor T6, and the gates of the seventh transistor T7 all serve as clock signal input terminals. The difference is that the clock signals input to the gates of the first transistor T1, the first terminal of the second transistor T2, and the gate of the third transistor T3 are clock signals, while the clock signals input to the first terminals of the fourth transistor T4, the first terminal of the sixth transistor T6, and the gate of the seventh transistor T7 are the positive clock signal PCK and the negative clock signal PCB, respectively. The input signals of the second shift register 220 also include a second frame start signal PSTV and a vertical synchronization signal VEL, and other power signal input terminals also input a first voltage VGL or a second voltage VGH. It should be noted that the circuit of the second shift register 220 shown in Figure 12 is only schematic; in other embodiments, other suitable shift register circuits may also be used.

[0111] Figure 13 shows an exemplary timing diagram of the pixel circuit of Figure 11 during a refresh frame. As shown in Figure 13, Reset_P and Reset_H are driven by different gate drive circuits, and the drive waveforms can be different to more accurately drive the different reset sub-circuits in the pixel circuit.

[0112] When the number of gate driving circuits 200 is five, in addition to inputting a clock signal to the first gate driving circuit, the driving chip 300 is also configured to: input a third clock signal to the clock signal terminal of the second gate driving circuit during the refresh frame phase; and input a fourth clock signal to the clock signal terminal of the second gate driving circuit during the hold frame phase, wherein the frequency of the fourth clock signal is lower than the frequency of the third clock signal. That is, during the hold frame phase, in addition to downclocking the clock signal of the first gate driving circuit, the clock signal of the second gate driving circuit is also downclocked, which helps to further reduce the power consumption of the display module. It should be noted that, similar to the first gate driving circuit, for ease of explanation, some embodiments of this disclosure refer to the clock signal received by the second gate driving circuit during the refresh frame phase of the same display cycle as the third clock signal, and the clock signal received during the hold frame phase as the fourth clock signal.

[0113] In some embodiments, considering the functional characteristics of the first reset circuit 117, the second reset circuit 118, and the third reset circuit 119, the frequency of the fourth clock signal can be lower than the frequency of the second clock signal, that is, the clock signal of the second gate drive circuit can be down-frequency more during the holding frame stage compared to the first gate drive circuit.

[0114] In some embodiments, the frequency of the fourth clock signal can be N1 times the frequency of the third clock signal, where N1 is an even number. Figure 14 shows a timing diagram of a second gate driving circuit according to some embodiments of the present disclosure. Figure 14 takes an example where the clock signal of the second gate driving circuit includes a set of positive clock signals PCK and negative clock signals PCB. The third clock signal includes the positive clock signal PCK and negative clock signal PCB for the refresh frame stage, and the fourth clock signal includes the positive clock signal PCK and negative clock signal PCB for the hold frame stage. In Figure 14, PSTV represents the second frame start signal of the second gate driving circuit, and POUT represents the output signal of the second gate driving circuit. As shown in Figure 14, after the refresh frame stage ends, the frequency of the positive clock signal PCK of the second gate driving circuit can be adjusted to N1 times that of the refresh frame stage, and the frequency of the negative clock signal PCB can also be adjusted to N1 times that of the refresh frame stage, and the adjusted frequency is maintained throughout the hold frame stage. For example, when the clock signals of the first gate driving circuit and the second gate driving circuit have the same frequency during the refresh frame stage, the frequency of the positive clock signal HCK and the negative clock signal HCB during the hold frame stage can be 1 / 8 times that of the refresh frame stage, while the frequency of the positive clock signal PCK and the negative clock signal PCB during the hold frame stage can be 1 / 16 times that of the refresh frame stage.

[0115] In other embodiments, the fourth clock signal can be dynamically frequency-adjusted during the hold frame phase. For example, the hold frame phase includes a first time period, a second time period, and a third time period set sequentially, and the fourth clock signal includes a fourth sub-clock signal, a fifth sub-clock signal, and a sixth sub-clock signal. The driver chip 300 is configured to input the fourth sub-clock signal to the clock signal terminal of the second gate driving circuit during the first time period, wherein the frequency of the fourth sub-clock signal is less than the frequency of the third clock signal; to input the fifth sub-clock signal to the clock signal terminal of the second gate driving circuit during the second time period, wherein the frequency of the fifth sub-clock signal is greater than the frequency of the fourth sub-clock signal and less than the frequency of the third clock signal; and to input the sixth sub-clock signal to the clock signal terminal of the second gate driving circuit during the third time period, wherein the frequency of the sixth sub-clock signal is less than the frequency of the fifth sub-clock signal. That is, the fourth sub-clock signal is the clock signal received by the second gate driving circuit during the first time period, the fifth sub-clock signal is the clock signal received by the second gate driving circuit during the second time period, and the sixth sub-clock signal is the clock signal received by the second gate driving circuit during the third time period.

[0116] Figure 15 shows a timing diagram of a second gate drive circuit according to some other embodiments of the present disclosure. Figure 15 also uses the example of the clock signal of the second gate drive circuit including a set of positive clock signals PCK and negative clock signals PCB. As shown in Figure 15, when the first time period is the 1st to 20th holding frames, the second time period is the 21st to 39th holding frames, and the third time period is the 40th to 59th holding frames, similar to the timing diagram of the first gate drive circuit shown in Figure 7, the fourth sub-clock signal (i.e., the positive clock signal PCK and negative clock signal PCB in the first time period) and the sixth sub-clock signal (i.e., the positive clock signal PCK and negative clock signal PCB in the third time period) can be a first constant level signal, and the frequency of the fifth sub-clock signal (i.e., the positive clock signal PCK and negative clock signal PCB in the second time period) can be one-tenth of M1 of the refresh frame stage, for example, 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, or 1 / 64, etc. M1 can be greater than M. For example, if the frequency of the second sub-clock signal is 1 / 8 of the refresh frame stage, the frequency of the fifth sub-clock signal can be reduced to 1 / 16 of the refresh frame stage. This effectively reduces the power consumption of the driver chip 300, the first gate drive circuit, and the second gate drive circuit, thereby reducing the power consumption of the display module.

[0117] When the display module includes the first gate driving circuit and the second gate driving circuit described above, in addition to inputting the first frame start signal to the first gate driving circuit, the driver chip 300 is also configured to input a second frame start signal to the signal input terminal of the second gate driving circuit. In some embodiments, based on the functional characteristics of the first reset circuit 117, the second reset circuit 118, and the third reset circuit 119, when the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the second frame start signal is less than the refresh frequency of the first frame start signal, which is beneficial for improving the VRR problem while further reducing the power consumption of the display module.

[0118] For example, the refresh rate of the second frame start signal can be reduced by 1 / 8, meaning the refresh rate of the second frame start signal can be lowered to 1 / 8 of the refresh rate of the light-emitting frame start signal, thus reducing the output signal of the second shift register by 1 / 8. Similarly, the refresh rate of the first frame start signal can be reduced by 1 / 4, meaning the refresh rate of the first frame start signal can be lowered to 1 / 4 of the refresh rate of the light-emitting frame start signal, thus reducing the output signal of the first shift register by 1 / 4. It should be noted that the frequency reduction method for the second frame start signal is similar to that for the first frame start signal; refer to the description of the frequency reduction for the first frame start signal above, which will not be elaborated upon here.

[0119] It should also be noted that in the holding frame refreshed by the second frame start signal, the frequency of the fourth clock signal is greater than zero. In some embodiments, in the holding frame where the second frame start signal is not refreshed, the fourth clock signal can be a first constant level signal. In the holding frame refreshed by the second frame start signal, the frequency of the fourth clock signal can be greater than zero and less than the frequency of the third clock signal to ensure the output of the second shift register, thereby realizing the refresh of the reset control terminal of the first reset sub-circuit 117.

[0120] In other embodiments, the second frame start signal is a second constant level signal during the hold frame phase. That is, the second frame start signal is not refreshed during the hold frame phase and remains at the second constant level, so that the output signal of the second shift register remains high during the hold frame phase, thereby keeping the first transistor T1 in the pixel circuit corresponding to FIG11 in the off state during the hold frame phase, so as to further reduce the power consumption of the display module.

[0121] In some embodiments, the second reset sub-circuit 118 and the third reset sub-circuit 119 may also be driven by different gate drive circuits. The first gate drive circuit described above is configured to drive the third reset sub-circuit 119, meaning the signal output terminal of the first shift register is electrically connected to the third reset control terminal Reset3 in FIG. 4. The multiple gate drive circuits 200 described above also include a second gate drive circuit for driving the first reset sub-circuit 117 and a third gate drive circuit for driving the second reset sub-circuit 118, both of which are electrically connected to the driver chip 300. The second gate drive circuit includes multiple cascaded second shift registers, the signal output terminal of which is electrically connected to the first reset control terminal Reset1 in FIG. 4. The third gate drive circuit includes multiple cascaded third shift registers, the signal output terminal of which is electrically connected to the second reset control terminal Reset2 in FIG. 4.

[0122] In some embodiments, the first shift register and the third shift register may employ the shift register circuit shown in FIG8, and the second shift register may employ the shift register circuit shown in FIG10.

[0123] Figure 16 shows a circuit diagram of a pixel circuit according to some embodiments of the present disclosure. The difference from the pixel circuit corresponding to Figure 11 is that the gate of the seventh transistor T7 in Figure 16 is connected to the reset control terminal Reset_H2, and the gate of the eighth transistor T8 is connected to the reset control terminal Reset_H1. These are different reset control terminals; Reset_H1 is driven by the first gate driving circuit, and Reset_H2 is driven by the third gate driving circuit. In this case, the display module has six groups of gate driving circuits. Figure 17 shows an exemplary timing diagram of the pixel circuit of Figure 16 during a refresh frame. As shown in Figure 17, since Reset_P, Reset_H1, and Reset_H2 are driven by different gate driving circuits, the driving waveforms can be different to more accurately drive the three different reset sub-circuits in the pixel circuit.

[0124] When there are six groups of gate driving circuits, in addition to inputting a clock signal to the first gate driving circuit, the driver chip 300 is also configured to: input a third clock signal to the clock signal terminal of the second gate driving circuit and a fifth clock signal to the clock signal terminal of the third gate driving circuit during the refresh frame phase; and input a fourth clock signal to the clock signal terminal of the second gate driving circuit and a sixth clock signal to the clock signal terminal of the third gate driving circuit during the hold frame phase. The frequency of the fourth clock signal is lower than the frequency of the third clock signal, the frequency of the sixth clock signal is lower than the frequency of the fifth clock signal, and the frequencies of the fourth and sixth clock signals are less than or equal to the frequency of the second clock signal. That is, during the hold frame phase, in addition to downclocking the clock signal of the first gate driving circuit, the clock signals of the second and third gate driving circuits are also downclocked, which helps to further reduce the power consumption of the display module. It should be noted that, similar to the first and second gate driving circuits, for ease of explanation, some embodiments of this disclosure refer to the clock signal received by the third gate driving circuit during the refresh frame phase of the same display cycle as the fifth clock signal, and the clock signal received during the hold frame phase as the sixth clock signal.

[0125] In some embodiments, the frequency of the sixth clock signal is one-N² times the frequency of the fifth clock signal, where N² is an even number. Figure 18 shows a timing diagram of a third gate driving circuit according to some embodiments of the present disclosure. Figure 18 uses an example where the clock signal of the third gate driving circuit includes a set of positive clock signals HCK' and negative clock signals HCB'. The fifth clock signal includes the positive clock signal HCK' and negative clock signal HCB' for the refresh frame phase, and the sixth clock signal includes the positive clock signal HCK' and negative clock signal HCB' for the hold frame phase. In Figure 18, HSTV' represents the third frame start signal of the third gate driving circuit, and HOUT' represents the output signal of the third gate driving circuit. As shown in Figure 18, after the refresh frame phase ends, the frequency of the positive clock signal HCK' of the third gate driving circuit can be adjusted to one-N² times the refresh frame phase frequency, and the frequency of the negative clock signal HCB' can also be adjusted to one-N² times the refresh frame phase frequency, maintaining the adjusted frequencies throughout the hold frame phase.

[0126] Considering the functional characteristics of the first reset circuit 117, the second reset circuit 118, and the third reset circuit 119, the display screen of the refresh frame phase is kept unchanged during the holding frame phase, and no new data is written. In some embodiments, the frequencies of the fourth clock signal and the sixth clock signal can be lower than the frequency of the second clock signal. That is, the clock frequencies of the second gate driving circuit and the third gate driving circuit during the holding frame phase are reduced to a lower level than those of the first gate driving circuit, which is beneficial to further reduce the power consumption of the display module.

[0127] In other embodiments, the frequency of the fourth clock signal may be less than that of the second clock signal, and the frequency of the sixth clock signal may be equal to that of the second clock signal. For example, during the refresh frame stage, the clock signals received by the first gate driving circuit, the second gate driving circuit, and the third gate driving circuit may also have the same frequency, that is, the frequencies of the first clock signal, the third clock signal, and the fifth clock signal are the same, denoted as f0. The frequencies of the second clock signal and the sixth clock signal may be 1 / 8 times f0, and the frequency of the fourth clock signal may be 1 / 16 times f0.

[0128] In some embodiments, the sixth clock signal can be dynamically frequency-adjusted during the hold frame phase. For example, the hold frame phase includes a first time period, a second time period, and a third time period set sequentially, and the sixth clock signal includes a seventh sub-clock signal, an eighth sub-clock signal, and a ninth sub-clock signal. The driver chip 300 is configured to input the seventh sub-clock signal to the clock signal terminal of the third gate driving circuit during the first time period, wherein the frequency of the seventh sub-clock signal is less than the frequency of the fifth clock signal; to input the eighth sub-clock signal to the clock signal terminal of the third gate driving circuit during the second time period, wherein the frequency of the eighth sub-clock signal is greater than the frequency of the seventh sub-clock signal and less than the frequency of the fifth clock signal; and to input the ninth sub-clock signal to the clock signal terminal of the third gate driving circuit during the third time period, wherein the frequency of the ninth sub-clock signal is less than the frequency of the eighth sub-clock signal. That is, the seventh sub-clock signal is the clock signal received by the third gate driving circuit during the first time period, the eighth sub-clock signal is the clock signal received by the third gate driving circuit during the second time period, and the ninth sub-clock signal is the clock signal received by the third gate driving circuit during the third time period.

[0129] Figure 19 shows a timing diagram of a third gate drive circuit according to some other embodiments of the present disclosure. Figure 19 also illustrates an example where the clock signal of the third gate drive circuit includes a set of positive clock signals HCK' and negative clock signals HCB'. As shown in Figure 19, when the first time period is the 1st to 20th holding frames, the second time period is the 21st to 39th holding frames, and the third time period is the 40th to 59th holding frames, the timing is similar to that of the first gate drive circuit shown in Figure 7 and the second gate drive circuit shown in Figure 18. The seventh sub-clock signal (i.e., the positive clock signal HCK' and the negative clock signal HCB' in the first time period) and the ninth sub-clock signal (i.e., the positive clock signal HCK' and the negative clock signal HCB' in the third time period) can be the first constant level signal. The frequency of the eighth sub-clock signal (i.e., the positive clock signal HCK' and the negative clock signal HCB' in the second time period) can be one-times of M2 in the refresh frame stage, for example, 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32, or 1 / 64, etc. M2 can be greater than or equal to M. For example, if the frequency of the second sub-clock signal is reduced to 1 / 8 of the refresh frame stage frequency, and the frequency of the fifth sub-clock signal is reduced to 1 / 16 of the refresh frame stage frequency, the frequency of the eighth sub-clock signal can be reduced to 1 / 8 of the refresh frame stage frequency, or even further, such as to 1 / 16 or 1 / 32 of the refresh frame stage frequency, depending on the needs of the actual application scenario. This effectively reduces the power consumption of the driver chip 300, the first gate driver circuit, the second gate driver circuit, and the third gate driver circuit, thereby reducing the power consumption of the display module.

[0130] When the display module includes the first gate driving circuit, the second gate driving circuit and the third gate driving circuit, the driver chip 300 is configured to input the first frame start signal to the first gate driving circuit and the second frame start signal to the second gate driving circuit, and is also configured to input the third frame start signal to the signal input terminal of the third gate driving circuit.

[0131] In some embodiments, considering the functional characteristics of the first reset circuit 117, the second reset circuit 118, and the third reset circuit 119, when the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequencies of the second frame start signal and the third frame start signal can be lower than the refresh frequency of the first frame start signal. This is beneficial for improving the VRR problem while further reducing the power consumption of the display module. The refresh frequencies of the second frame start signal and the third frame start signal can be the same or different, depending on the needs of the actual application scenario. For example, the first frame start signal can be down-clocked by 1 / 4, and the second and third frame start signals can be down-clocked by 1 / 8. It should be noted that the down-clocking method of the second and third frame start signals is similar to that of the first frame start signal, and can be referred to the relevant description of the down-clocking of the first frame start signal above, which will not be detailed here.

[0132] In other embodiments, the first frame start signal, the second frame start signal, and the third frame start signal are second constant level signals during the hold frame phase. That is, during the hold frame phase, the first frame start signal, the second frame start signal, and the third frame start signal are no longer refreshed and remain at the second constant level. The output signals of the first shift register, the second shift register, and the third shift register remain at a high level during the hold frame phase, thereby keeping the first transistor T1, the seventh transistor T7, and the eighth transistor T8 in the pixel circuit corresponding to Figure 15 in the off state during the hold frame phase, further reducing the power consumption of the display module.

[0133] In some embodiments, the display module further includes a fourth gate driving circuit, a fifth gate driving circuit, and a light-emitting driving circuit. The driving chip 300 is electrically connected to the fourth gate driving circuit, the fifth gate driving circuit, and the light-emitting driving circuit, respectively. The fourth gate driving circuit includes multiple cascaded fourth shift registers, the signal output terminals of which are electrically connected to the first scan control terminal. The fifth gate driving circuit includes multiple cascaded fifth shift registers, the signal output terminals of which are electrically connected to the second scan control terminal. The light-emitting driving circuit includes multiple cascaded sixth shift registers, the signal output terminals of which are electrically connected to the light-emitting control terminal. In some embodiments, the border region NA of the substrate 101 includes a first border region NA1 and a second border region NA2. The first border region NA1 is located on the first side of the display area, and the second border region NA2 is located on the second side of the display area, with the first side and the second side being opposite sides.

[0134] Figure 20 shows a schematic diagram of the arrangement of gate driving circuits according to some embodiments of the present disclosure. As shown in Figure 20, the fourth gate driving circuit 204 can be disposed in the first border area NA1 and the second border area NA2, i.e., bilateral driving is adopted. The first-level fourth shift register can drive one row of sub-pixels or multiple rows of sub-pixels, such as driving two rows of sub-pixels. The fifth gate driving circuit 205, the first gate driving circuit 201, and the third gate driving circuit 203 can be disposed in the first border area NA1, with the fifth gate driving circuit 205 located on the side of the fourth gate driving circuit 204 away from the display area AA, the third gate driving circuit 203 located on the side of the fifth gate driving circuit 205 away from the display area AA, and the first gate driving circuit 201 located on the side of the third gate driving circuit 203 away from the display area AA. The second gate driving circuit 202 and the light-emitting driving circuit 206 can be disposed in the second border area NA2, with the second gate driving circuit 202 located on the side of the fourth gate driving circuit 204 away from the display area AA, and the light-emitting driving circuit 206 located on the side of the second gate driving circuit 202 away from the display area AA.

[0135] Considering that the first shift register and the third shift register can use the same shift register circuit, and the clock signal can have the same down-frequency factor during the holding frame stage, the first gate drive circuit 201 and the third gate drive circuit 203 are arranged in the same side frame area and adjacent to each other, which helps to simplify the design and manufacturing difficulty.

[0136] In some embodiments, considering that the fourth shift registers of each stage of the fourth gate drive circuit 204 output a second constant level signal during the holding frame stage, the second constant level signal is a level signal that controls the data writing sub-circuit 111 to be in the off state. Taking the pixel circuit corresponding to FIG5 as an example, the second constant level signal can be a high level signal.

[0137] To further reduce the power consumption of the display module, in some embodiments, the clock signal of the fourth gate driving circuit 204 can be down-frequencyd during the hold frame phase, ensuring that the fourth gate driving circuit 204 outputs a second constant-level signal during the hold frame phase. For example, the driver chip 300 is also configured to input a seventh clock signal to the clock signal of the fourth gate driving circuit 204 during the refresh frame phase and an eighth clock signal to the clock signal of the fourth gate driving circuit 204 during the hold frame phase, wherein the frequency of the eighth clock signal is lower than the frequency of the seventh clock signal.

[0138] It should be noted that, similar to the first gate driving circuit 201, the second gate driving circuit 202, and the third gate driving circuit 203, for ease of explanation, some embodiments of this disclosure refer to the clock signal received by the fourth gate driving circuit 204 during the refresh frame phase of the same display cycle as the seventh clock signal, and the clock signal received during the hold frame phase as the eighth clock signal. The frequency reduction method for the clock signal of the fourth gate driving circuit 204 can refer to the aforementioned description of the frequency reduction of the clock signal of the first gate driving circuit 201, and will not be detailed here. Since the control terminal of the data writing sub-circuit 111 does not need to be refreshed during the hold frame phase, in some embodiments, the eighth clock signal can be a first constant level signal to further reduce power consumption.

[0139] In some embodiments, the driver chip 300 is further configured to input a fourth frame start signal to the signal input terminal of the fourth gate drive circuit 204 and a fifth frame start signal to the signal input terminal of the fifth gate drive circuit 205. In some embodiments, the pulse width of the fourth frame start signal may be less than the pulse width of the first frame start signal, the pulse width of the first frame start signal may be less than the pulse width of the fifth frame start signal, and the pulse width of the fifth frame start signal may be less than the pulse width of the light emission frame start signal. For example, when the operating level of the output signals of the light emission drive circuit 206, the first gate drive circuit 201, and the fourth gate drive circuit 204 is low, and the operating level of the output signal of the fifth gate drive circuit 205 is high, the pulse widths of the light emission frame start signal and the fifth frame start signal may be the width of a high-level pulse, and the pulse widths of the first frame start signal and the fourth frame start signal may be the width of a low-level pulse.

[0140] Figure 21 shows a timing diagram of frame start signals according to some embodiments of the present disclosure. Figure 21 uses a display module comprising four sets of gate driving circuits, namely a first gate driving circuit 201, a fourth gate driving circuit 204, a fifth gate driving circuit 205, and a light-emitting driving circuit 206, as an example to illustrate an exemplary timing diagram of the frame start signals of these four sets of gate driving circuits during the refresh frame stage and the hold frame stage. The hold frame stage only illustrates the timing of one hold frame. In Figure 21, ESTV represents the light-emitting frame start signal, NSTV represents the fifth frame start signal, HSTV represents the first frame start signal, and GSTV represents the fourth frame start signal. As shown in Figure 21, the pulse width of the light-emitting frame start signal can be 96H, the pulse width of the fifth frame start signal can be 56H, the pulse width of the first frame start signal can be 8H, and the pulse width of the fourth frame start signal can be 1H. 1H is the charging time of one row of pixels. Taking a display panel with a refresh rate of 60Hz and a total of 1125 pixel rows as an example, 1H is 1 / 60 / 1125 (seconds).

[0141] This disclosure provides a driver chip in some embodiments, including a memory and a processor. The memory stores a computer program that can run on the processor. The computer program is executed by the processor in the following steps: when the current display cycle includes a refresh frame phase and a hold frame phase, during the refresh frame phase, a first clock signal is input to the clock signal terminal of a first gate driving circuit; during the hold frame phase, a second clock signal is input to the clock signal terminal of the first gate driving circuit, the frequency of the second clock signal being less than the frequency of the first clock signal; wherein, the first gate driving circuit includes a plurality of cascaded first shift registers, and the signal output terminal of the first shift register is electrically connected to the reset control terminal of at least one reset sub-circuit in the pixel circuit of the display panel.

[0142] It should be noted that for a detailed description of the driver chip and its technical effects provided in the embodiments of this disclosure, please refer to the relevant description of the driver chip 300 in the above-described embodiments of the display module, which will not be repeated here.

[0143] Furthermore, those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0144] Although exemplary embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

Claims

1. A display module, comprising: The display panel includes a substrate and a plurality of sub-pixels arranged in an array on the substrate, each sub-pixel including a light-emitting device and a pixel circuit electrically connected to the light-emitting device; The first gate driving circuit includes a plurality of cascaded first shift registers, wherein the signal output terminal of the first shift register is electrically connected to the reset control terminal of at least one reset sub-circuit in the pixel circuit. as well as A driver chip is electrically connected to the first gate driving circuit. The driver chip is configured to: input a first clock signal to the clock signal terminal of the first gate driving circuit during the refresh frame phase when the current display cycle includes a refresh frame phase and a hold frame phase; and input a second clock signal to the clock signal terminal of the first gate driving circuit during the hold frame phase, wherein the frequency of the second clock signal is less than the frequency of the first clock signal.

2. The display module according to claim 1, wherein, The hold-frame phase includes a first time period, a second time period, and a third time period set sequentially. The second clock signal includes a first sub-clock signal, a second sub-clock signal, and a third sub-clock signal. The driver chip is configured as follows: During the first time period, a first sub-clock signal is input to the clock signal terminal of the first gate driving circuit, and the frequency of the first sub-clock signal is less than the frequency of the first clock signal. During the second time period, a second sub-clock signal is input to the clock signal terminal of the first gate driving circuit. The frequency of the second sub-clock signal is greater than the frequency of the first sub-clock signal and less than the frequency of the first clock signal. During the third time period, a third sub-clock signal is input to the clock signal terminal of the first gate driving circuit, and the frequency of the third sub-clock signal is less than the frequency of the second sub-clock signal.

3. The display module according to claim 2, wherein, The first sub-clock signal and the third sub-clock signal are first constant level signals, and the voltage value of the first constant level signal is approximately the same as the low level voltage value of the first clock signal. The frequency of the second sub-clock signal is one-M times the frequency of the first clock signal, where M is an even number.

4. The display module according to claim 1, wherein, The frequency of the second clock signal is one-N times the frequency of the first clock signal, where N is an even number.

5. The display module according to claim 1 further includes a light-emitting driving circuit, wherein the signal output terminal of the light-emitting driving circuit is electrically connected to the light-emitting control terminal in the pixel circuit; in, The driving chip is electrically connected to the light-emitting driving circuit and is configured to: input a first frame start signal to the signal input terminal of the first gate driving circuit and input a light-emitting frame start signal to the signal input terminal of the light-emitting driving circuit; In the case where the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the first frame start signal is greater than or equal to the current refresh frequency of the display panel and less than or equal to the refresh frequency of the light emission frame start signal; or, the first frame start signal is a second constant level signal in the hold frame phase, and the voltage of the second constant level signal is approximately the same as the high level voltage value of the first frame start signal.

6. The display module according to claim 5, wherein, The refresh frame stage includes a refresh frame, and the hold frame stage includes multiple hold frames. The first frame start signal starts from the refresh frame and is refreshed once every at least one hold frame, so that the refresh frequency of the first frame start signal is greater than the current refresh frequency of the display panel and less than the refresh frequency of the light emission frame start signal.

7. The display module according to any one of claims 1-6, wherein, The pixel circuit includes a driving sub-circuit, a compensation sub-circuit, a data writing sub-circuit, a storage sub-circuit, a first light emission control sub-circuit, a second light emission control sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a third reset sub-circuit. The control terminal of the driving sub-circuit is connected to the first node, the first connection terminal is connected to the second node, and the second connection terminal is connected to the third node; the control terminal of the compensation sub-circuit is connected to the second scan control terminal, the first connection terminal is connected to the first node, and the second connection terminal is connected to the third node; the first connection terminal of the storage sub-circuit is connected to the first power supply voltage terminal, and the second connection terminal is connected to the first node. The control terminal of the first reset sub-circuit is connected to the first reset control terminal, the first connection terminal is connected to the first initial voltage terminal, and the second connection terminal is connected to the third node; The control terminal of the second reset sub-circuit is connected to the second reset control terminal, the first connection terminal is connected to the second initial voltage terminal, and the second connection terminal is connected to the anode of the light-emitting device; The control terminal of the third reset sub-circuit is connected to the third reset control terminal, and the first connection terminal is connected to the third initial voltage terminal. The control terminal of the data writing sub-circuit is connected to the first scan control terminal, and the first connection terminal is connected to the data voltage terminal. The second connection terminal of the data writing sub-circuit and the third reset sub-circuit is connected to the second node. The control terminals of the first light-emitting control sub-circuit and the second light-emitting control sub-circuit are connected to the light-emitting control terminal. The first connection terminal of the first light-emitting control sub-circuit is connected to the first power supply voltage terminal, and the second connection terminal is connected to the second node. The first connection terminal of the second light-emitting control sub-circuit is connected to the third node, and the second connection terminal is connected to the anode of the light-emitting device. Among them, at least one of the first reset control terminal, the second reset control terminal and the third reset control terminal is electrically connected to the signal output terminal of the first shift register.

8. The display module according to claim 7, wherein, The signal output terminal of the first shift register is electrically connected to the first reset control terminal, the second reset control terminal, and the third reset control terminal, respectively.

9. The display module according to claim 7, wherein, The signal output terminal of the first shift register is electrically connected to the second reset control terminal and the third reset control terminal respectively. The display module also includes a second gate driving circuit, which includes multiple cascaded second shift registers. The signal output terminal of the second shift register is electrically connected to the first reset control terminal. The driver chip is electrically connected to the second gate driver circuit and is configured to: input a third clock signal to the clock signal terminal of the second gate driver circuit during the refresh frame phase; and input a fourth clock signal to the clock signal terminal of the second gate driver circuit during the hold frame phase, wherein the frequency of the fourth clock signal is less than the frequency of the third clock signal and the frequency of the second clock signal.

10. The display module according to claim 9, wherein, The driver chip is further configured to: input a first frame start signal to the signal input terminal of the first gate drive circuit, and input a second frame start signal to the signal input terminal of the second gate drive circuit; Wherein, in the current display cycle including a refresh frame phase and a hold frame phase, the refresh frequency of the second frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal and the second frame start signal are second constant level signals in the hold frame phase, and the voltage of the second constant level signal is approximately the same as the high level voltage value of the first frame start signal.

11. The display module according to claim 7, wherein, The signal output terminal of the first shift register is electrically connected to the third reset control terminal. The display module further includes: a second gate driving circuit and a third gate driving circuit; The second gate drive circuit includes multiple cascaded second shift registers, and the signal output terminal of the second shift register is electrically connected to the first reset control terminal; The third gate drive circuit includes multiple cascaded third shift registers, and the signal output terminal of the third shift register is electrically connected to the second reset control terminal. The driver chip is electrically connected to the second gate driver circuit and the third gate driver circuit respectively, and is configured to: input a third clock signal to the clock signal terminal of the second gate driver circuit and input a fifth clock signal to the clock signal terminal of the third gate driver circuit during the refresh frame phase; and input a fourth clock signal to the clock signal terminal of the second gate driver circuit and input a sixth clock signal to the clock signal terminal of the third gate driver circuit during the hold frame phase. Wherein, the frequency of the fourth clock signal is less than the frequency of the third clock signal, the frequency of the sixth clock signal is less than the frequency of the fifth clock signal, and the frequencies of the fourth clock signal and the sixth clock signal are less than or equal to the frequency of the second clock signal.

12. The display module according to claim 11, wherein, The driver chip is further configured to: input a first frame start signal to the signal input terminal of the first gate drive circuit, input a second frame start signal to the signal input terminal of the second gate drive circuit, and input a third frame start signal to the signal input terminal of the third gate drive circuit; Wherein, in the current display cycle including a refresh frame phase and a hold frame phase, the refresh frequency of the second frame start signal and the third frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal, the second frame start signal and the third frame start signal are second constant level signals in the hold frame phase, and the voltage of the second constant level signal is approximately the same as the high level voltage value of the first frame start signal.

13. The display module according to claim 11, further comprising: The fourth gate drive circuit includes multiple cascaded fourth shift registers, the signal output terminal of which is electrically connected to the first scan control terminal; The fifth gate drive circuit includes multiple cascaded fifth shift registers, the signal output terminal of which is electrically connected to the second scan control terminal; The light-emitting driving circuit includes multiple cascaded sixth shift registers, the signal output terminal of which is electrically connected to the light-emitting control terminal; The driving chip is electrically connected to the fourth gate driving circuit, the fifth gate driving circuit, and the light-emitting driving circuit, respectively.

14. The display module according to claim 13, wherein, The substrate includes a display area, a first border area, and a second border area. The first border area is located on a first side of the display area, and the second border area is located on a second side of the display area. The first side and the second side are opposite sides, and the plurality of sub-pixels are located in the display area. The fourth gate driving circuit is disposed in the first frame area and the second frame area; The fifth gate driving circuit, the first gate driving circuit, and the third gate driving circuit are disposed in the first frame area, and the fifth gate driving circuit is located on the side of the fourth gate driving circuit away from the display area, the third gate driving circuit is located on the side of the fifth gate driving circuit away from the display area, and the first gate driving circuit is located on the side of the third gate driving circuit away from the display area. The second gate driving circuit and the light-emitting driving circuit are disposed in the second frame area. The second gate driving circuit is located on the side of the fourth gate driving circuit away from the display area, and the light-emitting driving circuit is located on the side of the second gate driving circuit away from the display area.

15. A driver chip, comprising a memory and a processor, the memory storing a computer program executable on the processor, the computer program being executed by the processor of the following steps: In a current display cycle that includes a refresh frame phase and a hold frame phase, during the refresh frame phase, a first clock signal is input to the clock signal terminal of the first gate driving circuit; during the hold frame phase, a second clock signal is input to the clock signal terminal of the first gate driving circuit, the frequency of the second clock signal being less than the frequency of the first clock signal; wherein... The first gate driving circuit includes a plurality of cascaded first shift registers, and the signal output terminal of the first shift register is electrically connected to the reset control terminal of at least one reset sub-circuit in the pixel circuit of the display panel.

16. A display device comprising the display module according to any one of claims 1-14.

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