14results about "Switching accelaration modifications" patented technology

A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

The application provides a high-speed multi-voltage domain level conversion circuit with constant duty cycle, comprising: a level conversion module, the level conversion module comprising a pull-up tube circuit and a pull-down tube circuit; wherein the pull-up tube circuit is connected between a high power voltage domain and an output node, the pull-down tube circuit is coupled to the output node, and the output node is used to output an output signal with high and low levels; a first pull-down module connected between the pull-down tube circuit and a ground terminal, used to control the duty cycle of the output signal when the high power voltage domain is lower than a first preset value; a second pull-down module connected between the output node and the ground terminal, used to control the duty cycle of the output signal when the high power voltage domain is higher than a second preset value; wherein the second preset value is greater than the first preset value. Advantage: two pull-down modules are used to keep the high-speed signal output duty cycle constant at different voltages of the high power voltage domain.

A level shifter includes a cross-coupled circuit, a differential pair circuit, a NOT gate and a pulling device. The NOT gate receives an input signal and generates an inverted input signal. The cross-coupled circuit is connected to a first node and a second node. The cross-coupled circuit receives a first supply voltage. The voltage at the second node is used as an output signal. The differential pair circuit is connected to the first node and the second node. The differential pair circuit receives a ground voltage, the input signal and the inverted input signal. The pulling device is connected to the second node. The pulling device receives an enable signal. When the enable signal is not activated, the output signal is maintained at a specified logic level. When the enable signal is activated, the output signal changes with a change of the input signal.

An integrated circuit is provided. The integrated circuit includes a central processing unit built to process data and an output pin of the integrated circuit to provide processed data at the output pin to an external device connected to the output pin and a driver for the output pin with an output MOSFET of the driver connected to the output pin to provide the processed data with the power specified for the output pin. The driver includes a dynamic driver stage built to switch the output MOSFET between its conductive and non-conductive condition and a static driver stage built to maintain the condition of the output MOSFET until the dynamic driver stage switches the condition.

Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

An on-board device installed in a vehicle and is provided with an input circuit including an input end into which an input voltage is entered, and a drive power supply circuit that outputs a drive voltage to the input circuit. The input circuit includes a PNP bipolar transistor, a pull-up circuit, a second pull-up resistance, and a base resistance. The pull-up circuit includes a pull-up power supply, a first pull-up resistance, and a second diode with an anode facing the first pull-up resistance, which are connected in series and are provided between a base of the PNP bipolar transistor and the input end. The second pull-up resistance is provided between the base of the PNP bipolar transistor and the drive power supply circuit. The base resistance is provided between the base of the PNP bipolar transistor and the second pull-up resistance.

An integrated circuit is provided. The integrated circuit includes a central processing unit built to process data and an output pin of the integrated circuit to provide processed data at the output pin to an external device connected to the output pin and a driver for the output pin with an output MOSFET of the driver connected to the output pin to provide the processed data with the power specified for the output pin. The driver includes a dynamic driver stage built to switch the output MOSFET between its conductive and non-conductive condition and a static driver stage built to maintain the condition of the output MOSFET until the dynamic driver stage switches the condition.

An on-board device installed in a vehicle and is provided with an input circuit including an input end into which an input voltage is entered, and a drive power supply circuit that outputs a drive voltage to the input circuit. The input circuit includes a PNP bipolar transistor, a pull-up circuit, a second pull-up resistance, and a base resistance. The pull-up circuit includes a pull-up power supply, a first pull-up resistance, and a second diode with an anode facing the first pull-up resistance, which are connected in series and are provided between a base of the PNP bipolar transistor and the input end. The second pull-up resistance is provided between the base of the PNP bipolar transistor and the drive power supply circuit. The base resistance is provided between the base of the PNP bipolar transistor and the second pull-up resistance.

A bidirectional level shifter with fast rise and fall times and low current leakage is suitable for use with devices connected using an SPMI bus. The level shifter transfers signals between a first voltage domain and a second voltage domain operating at different voltage levels. The level shifter has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is between a first voltage source and the first terminal, and a second switch is between a second voltage source and the second terminal. The first switch and the second switch are operable to reduce current leakage of the level shifter.

Reduced delay and improved threshold tracking over PVT in a comparator input circuit and comparator are provided by circuits that include an inverter stage having a first complementary pair of transistors connected in a push-pull configuration. An input of the inverter stage is coupled to the gates of the first complementary pair of transistors, and an output of the inverter is coupled to the drains of the first complementary pair of transistors. The circuits also include one or more first degeneration transistors coupled between a source of one of the first complementary pair of transistors and a power supply rail of the circuit, and a reference circuit with an output coupled to one or more gates of the first degeneration transistors. The reference circuit controls the one or more first degeneration transistors to cause the inverter stage to have a threshold voltage equal to a threshold control voltage.

Integrated circuit (10) for data processing, the integrated circuit comprising: a central processing unit that is trained to process data; an output pin (2) of the integrated circuit (10) to supply processed data (D) at output pin (2) to an external device connected to output pin (2); a driver (7) for the output pin (2) with an output MOSFET (MPo) of the driver (7) connected to the output pin (2) to supply the processed data (D) with the power specified for the output pin (2), the driver (7) comprises: a dynamic driver stage (8) configured to switch the output MOSFET (MPo) between its conducting and non-conducting states, and a static driver stage (9) configured to maintain the state of the output MOSFET (MPo) until the dynamic driver stage (8) switches the state, wherein the dynamic driver stage (8) comprises a dynamic turn-on stage (11) with a first MOSFET (MP1) of the same technology as the output MOSFET (MPo) and a dynamic turn-off stage (12) and wherein the charge stored in the capacitance of the first MOSFET (MP1) at the turn-on time (T1) is used to charge the capacitance of the output MOSFET (MPo) at its gate contact in order to switch the output MOSFET (MPo) into its conducting state.

Disclosed herein are apparatus, system, method, and computer-readable medium aspects for interfacing a MIPI transmitter with a SERDES receiver. An example method aspect includes receiving first and second MIPI signals at respective inputs and level-shifting each signal using corresponding diodes. The level-shifted signals are applied to the base terminals of first and second transistors, whose emitters are coupled together. A control current is generated via a current mirror formed by a third and fourth transistor, with the current set by a control voltage. This control current is supplied to the coupled emitters, enabling the production of differential output signals at the collector terminals of the first and second transistors for input to a SERDES receiver.

A logic control circuit for a digital-to-analog converter, comprising: a first logic cell and a second logic cell each comprising: a first input terminal, a second input terminal and an output terminal; a first transistor and a second transistor both of a first carrier type, wherein the first transistor and the second transistor are connected in parallel; and a third transistor of a second carrier type opposite to the first carrier type; wherein the drain terminals of the first transistor, the second transistor, and the third transistor are connected to the output terminal; and a fourth transistor of the second carrier type connected in series with the third transistors of the first logic cell and the second logic cell such that the first logic cell and the fourth transistor form a first logic gate and the second logic cell and the fourth transistor form a second logic gate.

An analog circuit includes a logic output circuit and a standard cell. The logic output circuit outputs a first power supply voltage or a low-level signal to be an output signal. The standard cell includes at least two first-type transistors and at least two second-type transistors. The first-type transistors are connected in series. The first-type transistors receive a second power supply voltage, and output the second power supply voltage according to the output signal. A first voltage value of the first power supply voltage is less than a second voltage value of the second power supply voltage. The second-type transistors are connected in parallel, coupled to the first-type transistors at an output terminal, and output the low-level signal according to the output signal. First types of the first-type transistors are different from second types of the second-type transistors.