309results about "Reliability increase in field effect transistors" patented technology

A power switch includes a first transistor having a first current electrode corresponding to an output of the switch, a second transistor having a first current electrode coupled to a second current electrode of the first transistor, and a third transistor having a first current electrode coupled to a second current electrode of the second transistor and a second current electrode coupled to a first power supply voltage terminal which provides a first power supply voltage. The second current electrodes of each of the first, second, and third transistors are body-tied. An analog switch is either couples the second current electrode of the second transistor or a first reference voltage to a control electrode of the second transistor based on a control signal. A voltage selector circuit either couples the second current electrode of the first transistor or the first reference voltage to a control electrode of the first transistor.

In an example, a level shifter includes a low side having first and second inputs. The level shifter also includes a high side, where the high side has a latch having first and second terminals. The high side also includes a current comparator including first and second current mirrors. The high side includes isolation circuitry including first and second transistors, in which the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

The invention provides a bidirectional level converter and electronic equipment, and relates to the technical field of analog integrated circuits, the bidirectional level converter comprises a first port, a second port and a conversion circuit arranged between the first port and the second port; the first port comprises a first input / output port and a first reference level port; the second port comprises a second input / output port and a second reference level port; the conversion circuit comprises a first Schmidt comparator, a clamping circuit, a pull-up module, a pull-down module and a second Schmidt compartment.The bidirectional level converter and the electronic equipment have the advantages that under the condition that an input signal is converted from a high signal to a low signal, driving of an input stage does not need extremely high driving capacity, input and output are in an isolated state, and the conversion efficiency is improved; and the load size of the output stage has no influence on the driving capability of the input stage, so that the integrity of signals can be maintained, the system design is more flexible, and meanwhile, the circuit can adapt to more application scenes.

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

A level shifter includes an input circuit configured to invert an input voltage to output a first inverted voltage and a second inverted voltage, wherein the input voltage swings between a first ground voltage and a first power supply voltage, a protection circuit including at least one pair of transistors sharing a gate terminal to adjust, based on the first inverted voltage and the second inverted voltage, one of a first intermediate voltage and a second intermediate voltage of the protection circuit. a cross-coupling circuit configured to adjust the other of the first intermediate voltage and the second intermediate voltage, and an output circuit configured to invert the first intermediate voltage to output an output voltage that swings between a second ground voltage and a second power supply voltage.

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

The invention discloses an amplitude-adjustable attenuation circuit network for differential signal transmission. The amplitude-adjustable attenuation circuit network is composed of an attenuator I and an attenuator II. Wherein a common-mode feedback circuit is arranged between the attenuator I and the attenuator II. The attenuator I is introduced into an anti-ESD impact module which is composed of an input end back-to-back diode and used for resisting ESD impact. Differential signals at the input end of the attenuator I are subjected to voltage division through fixed resistors RS1 and RS1 < n > and binary weight adjustable resistors RS2 and RS2 < n >, the attenuator II is connected to a transmission channel in parallel, and the differential signals are subjected to further differential mode attenuation through binary weight adjustable capacitors CSp and CSn. The attenuation circuit network dynamically switches attenuation paths through an MOS tube switch matrix, respectively supports attenuation amounts from-1dB to-6dB and from-0.3 dB to-7dB, realizes high stepping precision, finally realizes synchronous attenuation for common-mode and differential-mode voltages, retains differential-mode attenuation of common-mode levels, and optimizes low-frequency amplitude attenuation and high-frequency signal integrity at the same time.

A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.

Electronic devices employing thin-gate insulator transistors coupled to varactors to reduce gate-to-source / drain voltage to avoid voltage breakdown, and related fabrication methods. The electronic device includes thin-gate insulator transistors coupled in series to provide a single output node, and with their gates controlled by a single, input node to provide an effective three (3) terminal, single transistor device. The electronic device includes varactors each coupled in series between a respective gate of a thin-gate insulator transistor and the input node to support a single input signal for the electronic device. Each series coupled varactor and thin-gate insulator transistor are coupled to the input node in parallel to each other. Each varactor creates a voltage division between the input signal voltage and its series connected gate of a respective thin-gate insulator transistor to prevent the respective gate-to-source / drain voltage of the thin-gate insulator transistor from exceeding its breakdown voltage.

The invention discloses a high-precision active isolation type 4-20 mA current loop circuit and an HART protocol transparent transmission method thereof, and relates to the technical field of industrial automation signal transmission, the high-precision active isolation type 4-20 mA current loop circuit comprises an input side, an output side and an isolation layer, the input end is connected with the transient protection circuit, the transient protection circuit is connected with the LC pi-type filter circuit, and the transient protection circuit and the LC pi-type filter circuit are respectively connected with the current reverse connection protection circuit. The influence of ground loop interference and common-mode voltage on the system is avoided, the safety of signal transmission is ensured, and the 3000Vrms withstand voltage requirement of an industrial scene is met. The interference of high-frequency noise on HART signals and 4-20mA analog signals is suppressed by optimizing the filter circuit and the EM I optimization layout.

A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge drive chip, relating to the technical field of power management in integrated circuits. By additionally providing a path from a floating power rail VDDH to the ground, the level shift circuit simulates the noise effect caused by a sudden change in the voltage of the floating power rail in the level shift circuit. The level shift circuit has a good noise immunity capability and a simple structure.

Chip package and method thereof. For example, a chip package of a charging controller chip for a USB charger includes: a high-side transistor including a first drain, a first gate and a first source; a low-side transistor including a second drain, a second gate and a second source, the low-side transistor being connected to the high-side transistor; one or more port transistors corresponding to one or more USB output ports respectively, each port transistor of the one or more port transistors including a third drain, a third gate and a third source; a controller coupled to the high-side transistor, the low-side transistor, and the one or more port transistors; a first chip base; a second chip base electrically insulated from the first chip base; and a third chip base electrically insulated from the first chip base and electrically insulated from the second chip base.

The embodiment of the disclosure provides an electronic device, which includes a functional circuit portion, an electrostatic protection circuit portion, and an external circuit portion. The electrostatic protection circuit portion is configured to electrically connect the functional circuit portion and the external circuit portion to transmit electrical signals, and provide electrostatic protection to the external circuit portion. The external circuit portion includes at least one external terminal and an external control circuit portion that is electrically connected to the external terminal, and the external control circuit portion is configured to control whether the electrical signal is transmitted to the external terminal. The electrostatic protection circuit portion is configured to use the external control circuit portion for electrostatic discharge.

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

The present disclosure provides a pulse trigger and a phase discriminator. The pulse trigger includes a logic module, a first input stage module, and a second input stage module; the circuit structures of the first input stage module and the second input stage module are the same; the logic module includes a first charging path corresponding to the positive terminal signal of the differential signal of the first clock signal, and a second charging path corresponding to the positive terminal signal of the differential signal of the second clock signal; the second clock signal and the first clock signal are clock signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal; the logic module is respectively connected to the first input stage module and the second input stage module. When the first clock signal is a rising edge signal, the logic module conducts based on the input signals of the first input stage module and the second input stage module, and the inverted output terminal of the pulse trigger outputs a high-level signal. By accelerating the charge and discharge stages of the pulse trigger, shortening the dead time, and improving the resolution of the pulse trigger, static errors are eliminated.

A memory controller may include an interface, and an input / output driving circuit. The interface may be configured to transfer data between a host and a memory device. The input / output driving circuit may include a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal. The pull-down driver includes a plurality of NMOS transistors and the gate control logic includes a plurality of PMOS transistors.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

The invention discloses a differential signal output circuit and an interface circuit. The differential signal output circuit comprises a first switch tube, a second switch tube and a first switch circuit. A third switch tube, a fourth switch tube and a second switch circuit; a first control signal is accessed to the control end of the first switch tube, a second control signal is accessed to the control end of the second switch tube, a third control signal is accessed to the control end of the third switch tube, and a fourth control signal is accessed to the control end of the fourth switch tube; the first switch circuit and the second switch circuit are suitable for controlling the states of the P-path differential output signals and the N-path differential output signals under the control of the first control signal, the second control signal and the fourth control signal so as to control the states of the P-path differential output signals and the N-path differential output signals after the first control signal and the fourth control signal are turned over or after the second control signal and the third control signal are turned over. And the P-path differential output signal and the N-path differential output signal are controlled to be overturned. By adopting the scheme, the cross point offset of the differential output signals can be reduced.

A circuit is disclosed. The circuit comprises a first switch with a first source terminal and a first drain terminal, and a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal. In one aspect, the second switch is configured to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal. In another aspect, a detection circuit is configured to receive the first signal and determine the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal, the detection circuit further being configured to transmit a second signal based on the first signal.

Various embodiments describe an integrated circuit. The integrated circuit includes at least seven planar field effect transistors provided in a common substrate next to one another with a maximum feature size in accordance with a technology node of a maximum of 65 nm. Each field effect transistor of the at least seven planar field effect transistors includes a first source / drain diffusion region, a second source / drain diffusion region, a channel region between the drain diffusion region and the source diffusion region, and a gate terminal. Each field effect transistor of the at least seven planar field effect transistors includes at least one common source / drain diffusion region with another field effect transistor of the at least seven planar field effect transistors. The common source / drain diffusion regions are free of vertical terminal contact material.

The invention provides a bias drive circuit suitable for a bipolar process, a control method and a digital-to-analog converter, the bias drive circuit comprises a bias generation module and a compensation module, the bias generation module generates a bias voltage, when a to-be-driven load changes, a corresponding initial compensation current is generated, and when the to-be-driven load changes, the to-be-driven load changes, the to-be-driven load changes; and mirroring the initial compensation current and adjusting the current to obtain a target compensation current so as to stabilize the bias voltage through the target compensation current. According to the bias driving circuit suitable for the bipolar process, when the driving load is increased, the target compensation current needed for increasing the load is generated through the compensation module, the influence on the bias voltage is reduced, the driving capacity of the bias driving circuit is improved, the bias driving circuit can be applied to a high-resolution current-steering DAC, a stable bias is provided for the DAC, and the reliability of the DAC is improved. And the stability of the DAC is improved.

The present application relates to the technical field of integrated circuits, and discloses a false trigger prevention circuit, method, system, power amplifier circuit and device, which comprises an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are both connected with the input end of the logic circuit, so that the false trigger problem of the existing N-type power tube caused by glitches is solved.

A level shifter includes an input circuit (110) configured to invert an input voltage (VIN) to output a first inverted voltage (VI1) and a second inverted voltage (VI2), wherein the input voltage (VIN) swings between a first ground voltage (VSS1) and a first power supply voltage (VDD1), a protection circuit (120) including at least one pair of transistors (PT1 to PT6) sharing a gate terminal to adjust, based on the first inverted voltage (VI1) and the second inverted voltage (VI2), one of a first intermediate voltage (VM1) and a second intermediate voltage (VM2) of the protection circuit (120), a cross-coupling circuit (130) configured to adjust the other of the first intermediate voltage (VM1) and the second intermediate voltage (VM2), and an output circuit (140) configured to invert the first intermediate voltage (VM1) to output an output voltage that swings between a second ground voltage (VSS2) and a second power supply voltage (VDD2).

A semiconductor device is disclosed. The semiconductor device includes: a semiconductor body (100) with a first surface (101); a first transistor device (1) arranged in the semiconductor body; and a second transistor device (2) arranged in the semiconductor body (100). The second transistor device (2) is arranged in a semiconductor region (130) that is dielectrically insulated from a remainder of the semiconductor body (100) and includes a plurality of transistor cells (20). Each of the plurality of transistor cells (20) includes: a source region (23) of a first doping type; a body region (22) of a second doping type; a drift region (21) of the first doping type; a drain region (24) of the first doping type, the drain region (24) being separated from the body region (22) by the drift region (21), and the source region (23) being spaced apart from the drain region (24) in a vertical direction of the semiconductor body (100); a gate electrode (25) dielectrically insulated from the body region (22); a source electrode (263) and a drain electrode (267) formed above the first surface (101) of the semiconductor body (100); and a doped connection region (29) extending from the first surface (101) of the semiconductor body (100) to the drain region (24) of the semiconductor body (100), wherein the doped region (29) is connected to the drain electrode (267) formed on the first surface (101) of the semiconductor body (100).

According to an embodiment, a high-voltage tolerant level shifter circuit (400, 500) includes input terminals for receiving complementary PWM input signals (CMDP, CMDN), output terminals for providing complementary output signals (OUTP, OUTN), and a latch circuit for translating the input signals to the output signals. The circuit has terminals for receiving floating ground (VFG) and supply (VFS) voltages, and a control circuit (802) to ensure operation within a known state. The latch circuit includes cross-coupled PMOS and NMOS transistors. NMOS input transistors are coupled to the latch circuit through cascode NMOS transistors. The floating voltages are generated based on a pre-regulated supply voltage (103), tracking ground (GND) over a first voltage range and controlled by ratio relationships over a second range. A monitoring circuit (600) generates control signals based on the pre-regulated supply voltage. The level shifter enables efficient voltage domain transfers at higher operating supplies using low-voltage devices, avoiding additional mask layers and reducing manufacturing costs and complexity.

An output driver and an output buffer circuit including the same, the output driver including: a driving circuit electrically connected to a pad and including at least two transistors connected in series with each other; and an anti-leakage circuit, wherein the anti-leakage circuit is configured to block the leakage current of the driving circuit. The gates of the at least two transistors are electrically connected to each other, and the leakage prevention circuit is configured to control a voltage level of an intermediate node between the at least two transistors based on a signal level of the pad.