209results about "Reliability increase in field effect transistors" patented technology

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

The invention discloses an amplitude-adjustable attenuation circuit network for differential signal transmission. The amplitude-adjustable attenuation circuit network is composed of an attenuator I and an attenuator II. Wherein a common-mode feedback circuit is arranged between the attenuator I and the attenuator II. The attenuator I is introduced into an anti-ESD impact module which is composed of an input end back-to-back diode and used for resisting ESD impact. Differential signals at the input end of the attenuator I are subjected to voltage division through fixed resistors RS1 and RS1 < n > and binary weight adjustable resistors RS2 and RS2 < n >, the attenuator II is connected to a transmission channel in parallel, and the differential signals are subjected to further differential mode attenuation through binary weight adjustable capacitors CSp and CSn. The attenuation circuit network dynamically switches attenuation paths through an MOS tube switch matrix, respectively supports attenuation amounts from-1dB to-6dB and from-0.3 dB to-7dB, realizes high stepping precision, finally realizes synchronous attenuation for common-mode and differential-mode voltages, retains differential-mode attenuation of common-mode levels, and optimizes low-frequency amplitude attenuation and high-frequency signal integrity at the same time.

A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.

The invention discloses a high-precision active isolation type 4-20 mA current loop circuit and an HART protocol transparent transmission method thereof, and relates to the technical field of industrial automation signal transmission, the high-precision active isolation type 4-20 mA current loop circuit comprises an input side, an output side and an isolation layer, the input end is connected with the transient protection circuit, the transient protection circuit is connected with the LC pi-type filter circuit, and the transient protection circuit and the LC pi-type filter circuit are respectively connected with the current reverse connection protection circuit. The influence of ground loop interference and common-mode voltage on the system is avoided, the safety of signal transmission is ensured, and the 3000Vrms withstand voltage requirement of an industrial scene is met. The interference of high-frequency noise on HART signals and 4-20mA analog signals is suppressed by optimizing the filter circuit and the EM I optimization layout.

A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge drive chip, relating to the technical field of power management in integrated circuits. By additionally providing a path from a floating power rail VDDH to the ground, the level shift circuit simulates the noise effect caused by a sudden change in the voltage of the floating power rail in the level shift circuit. The level shift circuit has a good noise immunity capability and a simple structure.

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

A memory controller may include an interface, and an input / output driving circuit. The interface may be configured to transfer data between a host and a memory device. The input / output driving circuit may include a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal. The pull-down driver includes a plurality of NMOS transistors and the gate control logic includes a plurality of PMOS transistors.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.

The invention discloses a differential signal output circuit and an interface circuit. The differential signal output circuit comprises a first switch tube, a second switch tube and a first switch circuit. A third switch tube, a fourth switch tube and a second switch circuit; a first control signal is accessed to the control end of the first switch tube, a second control signal is accessed to the control end of the second switch tube, a third control signal is accessed to the control end of the third switch tube, and a fourth control signal is accessed to the control end of the fourth switch tube; the first switch circuit and the second switch circuit are suitable for controlling the states of the P-path differential output signals and the N-path differential output signals under the control of the first control signal, the second control signal and the fourth control signal so as to control the states of the P-path differential output signals and the N-path differential output signals after the first control signal and the fourth control signal are turned over or after the second control signal and the third control signal are turned over. And the P-path differential output signal and the N-path differential output signal are controlled to be overturned. By adopting the scheme, the cross point offset of the differential output signals can be reduced.

A circuit is disclosed. The circuit comprises a first switch with a first source terminal and a first drain terminal, and a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal. In one aspect, the second switch is configured to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal. In another aspect, a detection circuit is configured to receive the first signal and determine the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal, the detection circuit further being configured to transmit a second signal based on the first signal.

Various embodiments describe an integrated circuit. The integrated circuit includes at least seven planar field effect transistors provided in a common substrate next to one another with a maximum feature size in accordance with a technology node of a maximum of 65 nm. Each field effect transistor of the at least seven planar field effect transistors includes a first source / drain diffusion region, a second source / drain diffusion region, a channel region between the drain diffusion region and the source diffusion region, and a gate terminal. Each field effect transistor of the at least seven planar field effect transistors includes at least one common source / drain diffusion region with another field effect transistor of the at least seven planar field effect transistors. The common source / drain diffusion regions are free of vertical terminal contact material.

The present application relates to the technical field of integrated circuits, and discloses a false trigger prevention circuit, method, system, power amplifier circuit and device, which comprises an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are both connected with the input end of the logic circuit, so that the false trigger problem of the existing N-type power tube caused by glitches is solved.

According to an embodiment, a high-voltage tolerant level shifter circuit (400, 500) includes input terminals for receiving complementary PWM input signals (CMDP, CMDN), output terminals for providing complementary output signals (OUTP, OUTN), and a latch circuit for translating the input signals to the output signals. The circuit has terminals for receiving floating ground (VFG) and supply (VFS) voltages, and a control circuit (802) to ensure operation within a known state. The latch circuit includes cross-coupled PMOS and NMOS transistors. NMOS input transistors are coupled to the latch circuit through cascode NMOS transistors. The floating voltages are generated based on a pre-regulated supply voltage (103), tracking ground (GND) over a first voltage range and controlled by ratio relationships over a second range. A monitoring circuit (600) generates control signals based on the pre-regulated supply voltage. The level shifter enables efficient voltage domain transfers at higher operating supplies using low-voltage devices, avoiding additional mask layers and reducing manufacturing costs and complexity.

A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

The invention provides an overvoltage protection circuit, which belongs to the technical field of integrated circuits, and comprises a main circuit comprising a first transistor and a second transistor, the grid electrode of the first transistor and the grid electrode of the second transistor are connected with a first control signal, and the source electrode and the substrate of the first transistor are in short circuit with the source electrode and the substrate of the second transistor; the drain of the first transistor is connected with a first signal; the drain of the second transistor is connected with a second signal; wherein the first control signal is a signal selected from the transistor substrate voltage signal and the third signal based on the switching control signal, and the difference between the voltage maximum value of the first signal and the second signal and the voltage of the third signal does not exceed the power supply voltage. The overvoltage protection circuit has the beneficial effects that the difference between the maximum voltage value in the first signal and the second signal and the voltage of the third signal does not exceed the power supply voltage, so that the gate-source voltage, the gate-drain voltage and the drain-source voltage of each transistor in the circuit do not exceed the power supply voltage, and overvoltage protection of the transistors is realized.

The invention relates to the technical field of PSI5 interfaces, and discloses a PSI5 interface circuit, which comprises a current-to-voltage unit, a switch unit, a threshold voltage generation unit, a comparator COMP and a logic control unit, during normal use, the current-to-voltage conversion unit, the threshold voltage generation unit, the comparator COMP and the logic control unit correctly convert sensor Manchester encoding current data conforming to a PSI5 protocol range, namely current flowing through the switch unit, into digital signals, and the digital signals are output signals of the comparator COMP; on the basis, after an open circuit or short circuit fault is removed, the output end of the comparator COMP may output a high-level signal for a long time, and at the moment, the logic control unit controls the threshold voltage output by the threshold voltage generation unit, so that the output end of the comparator COMP outputs a low-level signal; normal tracking of current and self-recovery of data are realized.

A complementary metal oxide semiconductor (CMOS) circuit includes a logical operation circuit formed on a substrate of a first conductivity type and including at least a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type, a third transistor of the first conductivity type having a gate terminal connected to the second well, and a fourth transistor of the second conductivity type having a gate terminal connected to the first well.

Provided are a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. The differential latch circuit includes: a first-stage differential latch circuit (I), a second-stage differential inverter circuit (II), and a low-level shift circuit, a pull-up terminal of a differential positive terminal of the second-stage differential inverter circuit (II) includes a first P-Channel Metal-Oxide-Semiconductor (PMOS) transistor (M9) and a second PMOS transistor (M10), a pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit (II) includes a third PMOS transistor (M15) and a first N-Channel Metal-Oxide-Semiconductor (NMOS) transistor (M11), and a circuit structure of a differential negative terminal of the first-stage differential latch circuit (I) is symmetrical to a circuit structure of a differential positive terminal of the first-stage differential latch circuit (I).

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The application provides a high-isolation T-type analog switch and a control circuit thereof, wherein: the input end of a first-stage delay module is coupled with a control signal of a system, the output end of the first-stage delay module is coupled with the input end of a second-stage delay module and the input end of a third set of inverting circuits, the output end of the third set of inverting circuits is coupled with the first input end of a circuit or the output end of the circuit outputs a first control signal, and the first control signal is output as a second control signal after passing through a first set of inverting circuits; the output end of the second-stage delay module is respectively coupled with the input end of a third-stage delay module and the input end of a fourth set of inverting circuits; the output end of the third-stage delay module is coupled with the input end of a second set of inverting circuits, the output end of the third-stage delay module outputs a third control signal, and the second set of inverting circuits is coupled with the second input end of the circuit; and the output end of the fourth set of inverting circuits outputs a fourth control signal. The control circuit of the application can avoid the occurrence of leakage during the switching process of the T-type analog switch circuit.

The invention discloses a switching circuit. The switching circuit comprises a first charge pump unit, a bootstrap unit and a switching unit, the bootstrap unit comprises a first switch tube, a bootstrap capacitor, a second switch tube, a first CMOS transmission gate module and a second CMOS transmission gate module, the second end of the first switch tube is connected with a first voltage, the first end of the first switch tube is connected with the first end of the bootstrap capacitor, the second end of the bootstrap capacitor is connected with the second end of the second switch tube, and the second end of the second switch tube is connected with a second voltage. The first end of the second switch tube is connected with a second voltage, the first end of the first CMOS transmission gate module is connected with the first end of the bootstrap capacitor, and the first end of the second CMOS transmission gate module is connected with the second end of the bootstrap capacitor; the switch unit comprises an output tube, and the control end of the output tube is connected with the second end of the first CMOS transmission gate module. According to the switching circuit provided by the invention, the turn-off stage of the output tube is eliminated through the configuration of the bootstrap unit, so that the output tube is always conducted, the function of continuously transmitting signals is realized, and the switching linearity is higher.

The present application provides an electronic device, which comprises a level conversion circuit including a first voltage domain circuit and a second voltage domain circuit. The second voltage domain circuit converts an input signal of the first voltage domain circuit into an output signal of the second voltage domain. The input signal switches between a first high level potential and a first low level potential, and the output signal switches between a second high level potential and a second low level potential. The second voltage domain circuit comprises a plurality of transistors, which form an input unit, a control unit and an output unit. The control unit clamps the voltage domains of the input unit and the output unit in a preset range according to a first control voltage and a second control voltage, so as to avoid the same type of transistors in the second voltage domain circuit from being broken down. The present application also provides an electronic device.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.

The described embodiments include a protection circuit comprising a voltage attenuation circuit with an input coupled to a switch terminal. A filter circuit has a filter input coupled to the output of the attenuation element. A first transistor has a first current terminal coupled to a power supply terminal and a first control terminal coupled to the filter output. A second transistor, matched to the first transistor, has a third current terminal coupled to the first current terminal, a second control terminal coupled to the first control terminal, and a fourth current terminal coupled to a first voltage sensing terminal. A buffer circuit has a buffer input coupled to the attenuation output.A S / H circuit has a sampling input coupled to the buffer output and a sampling output that provides a minimum ringing voltage of a signal from the switch terminal.

The embodiments of the present invention provide a turnout position detection device and system, which relate to the railway field. The turnout position detection device includes a DC power supply group, a drive circuit connected to the DC power supply group, and a position detection circuit connected to the drive circuit. Therefore, compared with the prior art method of detecting turnout position using a polarity-biased relay that relies on an AC power supply, the technical solution provided by the embodiments of the present invention uses a DC power supply group to provide a more reliable signal and higher security. This can improve the problems of low safety factors and low reliability in the prior art, thereby improving reliability and safety. In addition, the turnout position detection device uses an electronic circuit to implement the functions performed by the polarity-biased relay in a switch machine, and has the following advantages: the electronic components take up less space; they can be plugged and unplugged under power, making replacement easy.

The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven.The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

An input circuit receives an input voltage and generates a digital output. A first signal splitter generates a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level and provides a first control signal based on the upper signal. A second signal splitter generates an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and provides at least one control signal based on the upper signal. The third voltage level is greater than the second voltage level which is greater than the first voltage level. A level shifter receives the at least one control signal from the second signal splitter and provides a third control signal, and a combiner circuit generates the digital output as a logical combination of the first and third controls signals.