403results about "Reliability increase in field effect transistors" patented technology

A power switch includes a first transistor having a first current electrode corresponding to an output of the switch, a second transistor having a first current electrode coupled to a second current electrode of the first transistor, and a third transistor having a first current electrode coupled to a second current electrode of the second transistor and a second current electrode coupled to a first power supply voltage terminal which provides a first power supply voltage. The second current electrodes of each of the first, second, and third transistors are body-tied. An analog switch is either couples the second current electrode of the second transistor or a first reference voltage to a control electrode of the second transistor based on a control signal. A voltage selector circuit either couples the second current electrode of the first transistor or the first reference voltage to a control electrode of the first transistor.

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

In an example, a level shifter includes a low side having first and second inputs. The level shifter also includes a high side, where the high side has a latch having first and second terminals. The high side also includes a current comparator including first and second current mirrors. The high side includes isolation circuitry including first and second transistors, in which the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

The invention provides a bidirectional level converter and electronic equipment, and relates to the technical field of analog integrated circuits, the bidirectional level converter comprises a first port, a second port and a conversion circuit arranged between the first port and the second port; the first port comprises a first input / output port and a first reference level port; the second port comprises a second input / output port and a second reference level port; the conversion circuit comprises a first Schmidt comparator, a clamping circuit, a pull-up module, a pull-down module and a second Schmidt compartment.The bidirectional level converter and the electronic equipment have the advantages that under the condition that an input signal is converted from a high signal to a low signal, driving of an input stage does not need extremely high driving capacity, input and output are in an isolated state, and the conversion efficiency is improved; and the load size of the output stage has no influence on the driving capability of the input stage, so that the integrity of signals can be maintained, the system design is more flexible, and meanwhile, the circuit can adapt to more application scenes.

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

The present application discloses a high-speed transmitter and a serial data transmitter circuit, which relates to the technical field of signal transmission circuit design, wherein the high-speed transmitter includes a signal transmission unit, and the signal transmission unit includes: a signal transceiver module, which is used to transmit an input target signal; a first power tube, whose input end is used to receive an input target voltage, and whose output end is connected to the power supply end of the signal transceiver module. The technical solution of the present application is to set a first power tube in the signal transmission unit, and control the first power tube to power the signal transceiver module according to the target voltage input at the input end of the first power tube, and at the same time, combined with the characteristic of the power tube having a lower on-resistance, so that the setting of the first power tube can reduce the voltage drop at the power supply end of the signal transceiver module, thereby being able to meet the normal supply voltage requirements during high-speed serial link transmission.

Embodiments of the disclosure provide a level shift circuit, a chip and a display device. By setting first and second voltage clamping modules, and by adjusting first clamping voltage by controlling bias voltage input to the first voltage clamping module and adjusting second clamping voltage by controlling bias voltage and second bias voltage input to the second voltage clamping module, respective operating and output voltages of the first and the second voltage clamping modules and the shift module are within small range. Therefore, even the level shift circuit is designed by using devices with breakdown voltage lower than the difference between the first and second power supply voltages, the devices in the level shift circuit may be avoid being breakdown. Accordingly, some process platforms that cannot produce high-breakdown voltage devices may produce chips including the level shift circuit in the embodiment, and the restrictions on the process platform are reduced.

The invention discloses a wide-level-range high-speed level conversion circuit, and relates to the technical field of electronic circuits. A level conversion module in the level conversion circuit comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a second PMOS tube; a first NMOS tube and a second NMOS tube in the input module are NMOS devices with the voltage grade lower than the device grade corresponding to the main power supply voltage of the chip; the bias voltage generation module is connected with a power supply voltage and is used for generating a bias voltage; the bias voltage is dynamically adjusted along with the change of the power supply voltage; and a signal access selection unit in the input module is respectively connected with the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube, and is used for controlling the grid electrode to be connected with a bias voltage or a ground potential. The pull-down capability of the level conversion circuit can be adaptively adjusted along with the change of the pull-up capability caused by the change of the main power supply voltage, so that the level conversion circuit can realize high-speed level conversion in a wide level range.

A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

An electrostatic discharge protection circuit protects a first transistor. The circuit includes N diodes in series between conduction terminals of the first transistor. A second transistor and third transistor are connected in series between the conduction terminals of the first transistor. A control terminal of the third transistor is coupled to an anode of the N diodes. A first inverter couples the control terminals of the first and second transistors. A fourth transistor is connected in parallel with the first transistor. A control terminal of the fourth transistor is coupled to the junction point of the second and third transistors. A capacitor is arranged between the control terminal of the fourth transistor and a conduction terminal of the first transistor.

The embodiment of the invention discloses a level shift circuit and a high-voltage half-bridge driving chip. The level shift circuit comprises a first high-voltage switch tube, a second high-voltage switch tube, a cross coupling module and a conversion module; the controlled end of the first high-voltage switch tube is connected with a setting signal; a reset signal is accessed to the controlled end of the second high-voltage switch tube; the cross coupling module comprises a first current mirror and a second current mirror, first current is connected to the first end of the first current mirror, second current is connected to the first end of the second current mirror, and the first current is larger than or equal to N times of the second current; the first and second of the conversion module are respectively connected with the first and second current mirrors through the first and second nodes, and output signals are output. The level shift circuit can filter common-mode noise so as to ensure the stability of an output signal, a large resistor or capacitor does not need to be arranged, delay is reduced, and the signal transmission speed is increased.

A level shifter includes an input circuit configured to invert an input voltage to output a first inverted voltage and a second inverted voltage, wherein the input voltage swings between a first ground voltage and a first power supply voltage, a protection circuit including at least one pair of transistors sharing a gate terminal to adjust, based on the first inverted voltage and the second inverted voltage, one of a first intermediate voltage and a second intermediate voltage of the protection circuit. a cross-coupling circuit configured to adjust the other of the first intermediate voltage and the second intermediate voltage, and an output circuit configured to invert the first intermediate voltage to output an output voltage that swings between a second ground voltage and a second power supply voltage.

A laser detecting circuit is provided. The laser detecting circuit includes a latch circuit with a first inverter configured to invert a first output signal at a first node to generate a second output signal at a second node, and a second inverter configured to generate the first output signal based on the second output signal. The second inverter includes a plurality of PMOS transistors connected in series between a first source voltage and the first node, and a plurality of NMOS transistors. A gate of each of the plurality of PMOS transistors is connected to the second node, and a drain of each of the plurality of NMOS transistors is connected to the first node. The plurality of NMOS transistors includes dummy NMOS transistors and normal NMOS transistors.

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.

The invention discloses an amplitude-adjustable attenuation circuit network for differential signal transmission. The amplitude-adjustable attenuation circuit network is composed of an attenuator I and an attenuator II. Wherein a common-mode feedback circuit is arranged between the attenuator I and the attenuator II. The attenuator I is introduced into an anti-ESD impact module which is composed of an input end back-to-back diode and used for resisting ESD impact. Differential signals at the input end of the attenuator I are subjected to voltage division through fixed resistors RS1 and RS1 < n > and binary weight adjustable resistors RS2 and RS2 < n >, the attenuator II is connected to a transmission channel in parallel, and the differential signals are subjected to further differential mode attenuation through binary weight adjustable capacitors CSp and CSn. The attenuation circuit network dynamically switches attenuation paths through an MOS tube switch matrix, respectively supports attenuation amounts from-1dB to-6dB and from-0.3 dB to-7dB, realizes high stepping precision, finally realizes synchronous attenuation for common-mode and differential-mode voltages, retains differential-mode attenuation of common-mode levels, and optimizes low-frequency amplitude attenuation and high-frequency signal integrity at the same time.

The invention discloses a driving circuit for optimizing switching characteristics of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and belongs to the technical field of power electronics. After an input voltage VCC is isolated and converted by the isolation power supply unit, the input voltage VCC is input to the driving power supply unit for level conversion, and then a driving positive voltage and a driving negative voltage required by the work of the silicon carbide MOSFET are output. An input voltage VIN signal, a pulse signal VPWM, a driving positive voltage and a driving negative voltage pass through the driving signal unit to output a driving signal of the silicon carbide MOSFET; the outputs of the driving signal unit and the driving power supply unit are jointly input into the crosstalk suppression unit for crosstalk suppression, and a switching signal is output to the silicon carbide MOSFET. According to the invention, stable driving positive voltage and driving negative voltage required for switching on and switching off the silicon carbide MOSFETs can be output without being influenced by fluctuation of power supply voltage output by the isolation power supply unit, meanwhile, the rising or falling speed of driving voltage spikes generated when the silicon carbide MOSFETs work in series can be effectively inhibited, and the response speed is higher.

A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.

Electronic devices employing thin-gate insulator transistors coupled to varactors to reduce gate-to-source / drain voltage to avoid voltage breakdown, and related fabrication methods. The electronic device includes thin-gate insulator transistors coupled in series to provide a single output node, and with their gates controlled by a single, input node to provide an effective three (3) terminal, single transistor device. The electronic device includes varactors each coupled in series between a respective gate of a thin-gate insulator transistor and the input node to support a single input signal for the electronic device. Each series coupled varactor and thin-gate insulator transistor are coupled to the input node in parallel to each other. Each varactor creates a voltage division between the input signal voltage and its series connected gate of a respective thin-gate insulator transistor to prevent the respective gate-to-source / drain voltage of the thin-gate insulator transistor from exceeding its breakdown voltage.

The invention discloses a high-precision active isolation type 4-20 mA current loop circuit and an HART protocol transparent transmission method thereof, and relates to the technical field of industrial automation signal transmission, the high-precision active isolation type 4-20 mA current loop circuit comprises an input side, an output side and an isolation layer, the input end is connected with the transient protection circuit, the transient protection circuit is connected with the LC pi-type filter circuit, and the transient protection circuit and the LC pi-type filter circuit are respectively connected with the current reverse connection protection circuit. The influence of ground loop interference and common-mode voltage on the system is avoided, the safety of signal transmission is ensured, and the 3000Vrms withstand voltage requirement of an industrial scene is met. The interference of high-frequency noise on HART signals and 4-20mA analog signals is suppressed by optimizing the filter circuit and the EM I optimization layout.

A high-noise-immunity and low-delay level shift circuit for a GaN half-bridge drive chip, relating to the technical field of power management in integrated circuits. By additionally providing a path from a floating power rail VDDH to the ground, the level shift circuit simulates the noise effect caused by a sudden change in the voltage of the floating power rail in the level shift circuit. The level shift circuit has a good noise immunity capability and a simple structure.

Chip package and method thereof. For example, a chip package of a charging controller chip for a USB charger includes: a high-side transistor including a first drain, a first gate and a first source; a low-side transistor including a second drain, a second gate and a second source, the low-side transistor being connected to the high-side transistor; one or more port transistors corresponding to one or more USB output ports respectively, each port transistor of the one or more port transistors including a third drain, a third gate and a third source; a controller coupled to the high-side transistor, the low-side transistor, and the one or more port transistors; a first chip base; a second chip base electrically insulated from the first chip base; and a third chip base electrically insulated from the first chip base and electrically insulated from the second chip base.

The embodiment of the disclosure provides an electronic device, which includes a functional circuit portion, an electrostatic protection circuit portion, and an external circuit portion. The electrostatic protection circuit portion is configured to electrically connect the functional circuit portion and the external circuit portion to transmit electrical signals, and provide electrostatic protection to the external circuit portion. The external circuit portion includes at least one external terminal and an external control circuit portion that is electrically connected to the external terminal, and the external control circuit portion is configured to control whether the electrical signal is transmitted to the external terminal. The electrostatic protection circuit portion is configured to use the external control circuit portion for electrostatic discharge.

The embodiment of the invention provides a digital isolator based on charge detection and an implementation method of the digital isolator based on charge detection, high-voltage capacitors with two channels independent of each other are adopted for isolation, rising edge oscillation signals and falling edge oscillation signals are transmitted respectively, and no matching requirement exists relative to a differential channel; the signal encoding side and the signal decoding side are both matched with mutually independent dual-channel charge detection circuits, the encoding side charge detection unit is used for controlling the voltage-controlled oscillation unit to work through charge detection, detecting continuous first preset number of pulses to turn over high level and terminating the work of the voltage-controlled oscillation unit, otherwise, the pulse is low level; and the decoding side charge detection unit is used for detecting continuous pulses with a second preset number and generating a setting / resetting signal for the RS trigger to recover the original signal. According to the mode, the influence of interference signals on the oscillation signal frequency is avoided, and the correctness and reliability of signal demodulation are greatly improved.

A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of the conversion circuit comprises a first phase inverter, a first-stage amplifier and a second-stage amplifier. The input terminal of the first inverter is short-circuited to the output terminal of the first inverter. The second stage amplifier of the replica feedback loop circuit is a replica of the CML to half of the differential amplifier of the CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage for biasing a differential amplifier of the CML-to-CMOS converter such that a common mode (CM) voltage output by the differential amplifier is the same as a switching threshold voltage of a second inverter of the CML-to-CMOS converter.

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

The present disclosure provides a pulse trigger and a phase discriminator. The pulse trigger includes a logic module, a first input stage module, and a second input stage module; the circuit structures of the first input stage module and the second input stage module are the same; the logic module includes a first charging path corresponding to the positive terminal signal of the differential signal of the first clock signal, and a second charging path corresponding to the positive terminal signal of the differential signal of the second clock signal; the second clock signal and the first clock signal are clock signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal; the logic module is respectively connected to the first input stage module and the second input stage module. When the first clock signal is a rising edge signal, the logic module conducts based on the input signals of the first input stage module and the second input stage module, and the inverted output terminal of the pulse trigger outputs a high-level signal. By accelerating the charge and discharge stages of the pulse trigger, shortening the dead time, and improving the resolution of the pulse trigger, static errors are eliminated.

A memory controller may include an interface, and an input / output driving circuit. The interface may be configured to transfer data between a host and a memory device. The input / output driving circuit may include a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal. The pull-down driver includes a plurality of NMOS transistors and the gate control logic includes a plurality of PMOS transistors.

The application relates to a line driver impedance calibration overvoltage protection circuit and method, which is applied to an Ethernet and comprises a first impedance calibration circuit and an overvoltage protection circuit. The first impedance calibration circuit comprises a plurality of first transmission gates, two ends of each first transmission gate are connected with a first resistor and a second resistor respectively, and the first transmission gate can be controlled to be turned on or turned off to adjust the impedance between the line driver and the first connection end to a preset value. The overvoltage protection circuit is used for detecting the amplitude of the opposite end signal received by the hybrid circuit, comparing the amplitude of the opposite end signal with a predetermined threshold value, outputting a comparison signal, and controlling the amplitude of the local end signal sent by the line driver according to the comparison signal. The application can realize impedance calibration, the transmission gate works at the intermediate voltage, the voltage interval range is smaller, the overvoltage of the transmission gate is protected, the tolerance of the reliability of the Ethernet is better, the amplitude of the local end is limited, and then the overvoltage protection of the impedance calibration is realized.