114results about "Reliability increase in field effect transistors" patented technology

An asynchronous finite state machine (FSM) circuit comprises an arc cell configured to receive an analog input signal candidate for propagation over the FSM circuit as an output signal from the arc cell. In response to glitch affecting the analog input signal to the arc cell propagation over the FSM circuit of the analog input signal affected by glitch is conditioned upon either one of: i) the glitch being suppressed at the output of the arc cell, or ii) the glitch being latched within the arc cell. Propagation over the FSM circuit of the analog input signal affected by glitch takes place in response to the glitch being suppressed at the output of the arc cell irrespective of the glitch being latched within the arc cell.

A circuit is disclosed. The circuit comprises a first switch with a first source terminal and a first drain terminal, and a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal. In one aspect, the second switch is configured to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal. In another aspect, a detection circuit is configured to receive the first signal and determine the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal, the detection circuit further being configured to transmit a second signal based on the first signal.

The present application relates to the technical field of integrated circuits, and discloses a false trigger prevention circuit, method, system, power amplifier circuit and device, which comprises an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are both connected with the input end of the logic circuit, so that the false trigger problem of the existing N-type power tube caused by glitches is solved.

According to an embodiment, a high-voltage tolerant level shifter circuit (400, 500) includes input terminals for receiving complementary PWM input signals (CMDP, CMDN), output terminals for providing complementary output signals (OUTP, OUTN), and a latch circuit for translating the input signals to the output signals. The circuit has terminals for receiving floating ground (VFG) and supply (VFS) voltages, and a control circuit (802) to ensure operation within a known state. The latch circuit includes cross-coupled PMOS and NMOS transistors. NMOS input transistors are coupled to the latch circuit through cascode NMOS transistors. The floating voltages are generated based on a pre-regulated supply voltage (103), tracking ground (GND) over a first voltage range and controlled by ratio relationships over a second range. A monitoring circuit (600) generates control signals based on the pre-regulated supply voltage. The level shifter enables efficient voltage domain transfers at higher operating supplies using low-voltage devices, avoiding additional mask layers and reducing manufacturing costs and complexity.

A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

The invention provides an overvoltage protection circuit, which belongs to the technical field of integrated circuits, and comprises a main circuit comprising a first transistor and a second transistor, the grid electrode of the first transistor and the grid electrode of the second transistor are connected with a first control signal, and the source electrode and the substrate of the first transistor are in short circuit with the source electrode and the substrate of the second transistor; the drain of the first transistor is connected with a first signal; the drain of the second transistor is connected with a second signal; wherein the first control signal is a signal selected from the transistor substrate voltage signal and the third signal based on the switching control signal, and the difference between the voltage maximum value of the first signal and the second signal and the voltage of the third signal does not exceed the power supply voltage. The overvoltage protection circuit has the beneficial effects that the difference between the maximum voltage value in the first signal and the second signal and the voltage of the third signal does not exceed the power supply voltage, so that the gate-source voltage, the gate-drain voltage and the drain-source voltage of each transistor in the circuit do not exceed the power supply voltage, and overvoltage protection of the transistors is realized.

The invention relates to the technical field of PSI5 interfaces, and discloses a PSI5 interface circuit, which comprises a current-to-voltage unit, a switch unit, a threshold voltage generation unit, a comparator COMP and a logic control unit, during normal use, the current-to-voltage conversion unit, the threshold voltage generation unit, the comparator COMP and the logic control unit correctly convert sensor Manchester encoding current data conforming to a PSI5 protocol range, namely current flowing through the switch unit, into digital signals, and the digital signals are output signals of the comparator COMP; on the basis, after an open circuit or short circuit fault is removed, the output end of the comparator COMP may output a high-level signal for a long time, and at the moment, the logic control unit controls the threshold voltage output by the threshold voltage generation unit, so that the output end of the comparator COMP outputs a low-level signal; normal tracking of current and self-recovery of data are realized.

A complementary metal oxide semiconductor (CMOS) circuit includes a logical operation circuit formed on a substrate of a first conductivity type and including at least a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type, a third transistor of the first conductivity type having a gate terminal connected to the second well, and a fourth transistor of the second conductivity type having a gate terminal connected to the first well.

Provided are a differential latch circuit, a switch driver, and a digital-to-analog conversion circuit. The differential latch circuit includes: a first-stage differential latch circuit (I), a second-stage differential inverter circuit (II), and a low-level shift circuit, a pull-up terminal of a differential positive terminal of the second-stage differential inverter circuit (II) includes a first P-Channel Metal-Oxide-Semiconductor (PMOS) transistor (M9) and a second PMOS transistor (M10), a pull-down terminal of the differential positive terminal of the second-stage differential inverter circuit (II) includes a third PMOS transistor (M15) and a first N-Channel Metal-Oxide-Semiconductor (NMOS) transistor (M11), and a circuit structure of a differential negative terminal of the first-stage differential latch circuit (I) is symmetrical to a circuit structure of a differential positive terminal of the first-stage differential latch circuit (I).

This invention discloses circuits and methods for active power supply decoupling in synchronous digital systems. An active decoupling unit, incorporating switched capacitors, addresses voltage dips caused by simultaneous switching events. During peak demand, the unit quickly discharges capacitors to stabilize the supply voltage, while recharging occurs during low-demand intervals. This approach significantly reduces the required capacitor size and enhances charge delivery efficiency. Additionally, complementary clock signals can synchronize decoupling units, allowing partial or full compensation during both rising and falling edges of the clock. The invention provides enhanced area efficiency and reliability in synchronous digital logic environments.

The application provides a high-isolation T-type analog switch and a control circuit thereof, wherein: the input end of a first-stage delay module is coupled with a control signal of a system, the output end of the first-stage delay module is coupled with the input end of a second-stage delay module and the input end of a third set of inverting circuits, the output end of the third set of inverting circuits is coupled with the first input end of a circuit or the output end of the circuit outputs a first control signal, and the first control signal is output as a second control signal after passing through a first set of inverting circuits; the output end of the second-stage delay module is respectively coupled with the input end of a third-stage delay module and the input end of a fourth set of inverting circuits; the output end of the third-stage delay module is coupled with the input end of a second set of inverting circuits, the output end of the third-stage delay module outputs a third control signal, and the second set of inverting circuits is coupled with the second input end of the circuit; and the output end of the fourth set of inverting circuits outputs a fourth control signal. The control circuit of the application can avoid the occurrence of leakage during the switching process of the T-type analog switch circuit.

The present application provides an electronic device, which comprises a level conversion circuit including a first voltage domain circuit and a second voltage domain circuit. The second voltage domain circuit converts an input signal of the first voltage domain circuit into an output signal of the second voltage domain. The input signal switches between a first high level potential and a first low level potential, and the output signal switches between a second high level potential and a second low level potential. The second voltage domain circuit comprises a plurality of transistors, which form an input unit, a control unit and an output unit. The control unit clamps the voltage domains of the input unit and the output unit in a preset range according to a first control voltage and a second control voltage, so as to avoid the same type of transistors in the second voltage domain circuit from being broken down. The present application also provides an electronic device.

A circuit includes a first transistor having a control terminal and includes a predriver having an input and an output. The output is coupled to the control terminal of the first transistor. A second transistor of a first polarity has a control terminal coupled to the output of the predriver. A third transistor of a second polarity has first and second terminals. The first terminal of the third transistor is coupled to the control terminal of the second transistor. A fourth transistor having the second polarity has first and second terminals. The first terminal of the fourth transistor is coupled to the second terminal of the third transistor. The second terminal of the fourth transistor is coupled to a supply terminal.

The described embodiments include a protection circuit comprising a voltage attenuation circuit with an input coupled to a switch terminal. A filter circuit has a filter input coupled to the output of the attenuation element. A first transistor has a first current terminal coupled to a power supply terminal and a first control terminal coupled to the filter output. A second transistor, matched to the first transistor, has a third current terminal coupled to the first current terminal, a second control terminal coupled to the first control terminal, and a fourth current terminal coupled to a first voltage sensing terminal. A buffer circuit has a buffer input coupled to the attenuation output.A S / H circuit has a sampling input coupled to the buffer output and a sampling output that provides a minimum ringing voltage of a signal from the switch terminal.

An active gate driver provided to drive a power transistor includes a two-level Miller plateau detector, a cycle shifter, a flexible split-path feedback circuit, a PMOS switch picker, a NMOS switch picker, a PMOS buffer array and a NMOS buffer array. The active gate driver turns off some PMOS transistors of the PMOS buffer array and some NMOS transistors of the NMOS buffer array to lower power consumption when the power transistor in the Miller plateau. And the active gate driver also turns off some PMOS transistors of the PMOS buffer array if a gate-source voltage is greater than a high-potential reference voltage, thereby further reducing power consumption.

According to an embodiment, a transistor driver circuit includes a driving force limitation circuit and a delay-time adjustment circuit. The driving force limitation circuit operates to maintain a gate potential of a transistor to be driven at a driving force limitation potential when the transistor to be driven is driven. The driving force limitation potential corresponds to a threshold voltage of the transistor to be driven.The delay-time adjustment circuit operates to cause the gate potential to transition to the driving force limitation potential when the driving force limitation circuit is in operation.

An input circuit receives an input voltage and generates a digital output. A first signal splitter generates a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level and provides a first control signal based on the upper signal. A second signal splitter generates an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and provides at least one control signal based on the upper signal. The third voltage level is greater than the second voltage level which is greater than the first voltage level. A level shifter receives the at least one control signal from the second signal splitter and provides a third control signal, and a combiner circuit generates the digital output as a logical combination of the first and third controls signals.

The invention relates to a fail-safe input-output circuit. A circuit includes an input-output, a power supply terminal (113), a reference terminal (117), transistors (122) and (123), a driver circuit (120), and a bias generation circuit (125). The driver circuit (120) includes: a first inverter having an output; a second inverter having an input, an output, and a first power supply input and a second power supply input; and a transfer gate having an input, an output, and an enable input. The input of the second inverter is coupled to the output of the first inverter. The first enable input is coupled to the output of the first inverter, the second enable input is coupled to the output of the second inverter, the output of the transfer gate is coupled to an output of a driver circuit (120), the first supply input of the second inverter is coupled to the output of the transfer gate, and the second supply input of the second inverter is coupled to the output of the driver circuit (120). And the second supply input of the second inverter is coupled to a reference terminal (117).

The present invention provides a common-mode transient suppression protection circuit for a digital isolator, including a modulation circuit, a demodulation circuit and an isolation capacitor connected between the modulation circuit and the demodulation circuit. The modulation circuit includes a modulation circuit front-end and a drive circuit, which are connected in sequence, and a clamping module is arranged in the drive circuit. The protection circuit further includes a linear voltage regulator structure connected with the drive circuit, and a power supply clamp is arranged in the linear voltage regulator structure. By providing the linear voltage regulator structure having the power supply clamp and the drive circuit having the clamping module in the protection circuit, low-voltage devices in the drive circuit can be protected from being damaged by high-voltage signals generated by common-mode transient interference.

The present invention provides a semiconductor device that can reliably obtain a correct voltage detection signal when the power supply voltage is 0V or higher. [Solution] The semiconductor device 1 comprises power terminals VDD and GND, a voltage detection circuit 11, transistors 12, 13, and 14, a depletion transistor 15, a control circuit 16, input terminals 12a and 14a connected to output terminal 11b, input terminals 11a and 16b connected to power terminal VDD, source terminal 12b, input terminals 11c and 16c connected to power terminal GND, source terminals 14c and 15c, gate terminal 15a, source terminal 13b connected to drain terminal 12c, gate terminal 13a connected to drain terminal 13c, drain terminals 14b and 15b, and input terminal 16a. The control circuit 16 is configured such that even if the power supply voltage input to the voltage detection circuit 11 is less than or equal to the minimum operating voltage of the voltage detection circuit 11, the signal input to input terminal 16a of the control circuit 16 matches the potential of input terminal GND.

A circuit. The circuit includes a switch having a gate terminal, a source terminal and a drain terminal, a switch driver circuit connected to the gate terminal and arranged to control an on-state and an off-state of the switch, the switch drive circuit including: a signal conversion circuit arranged to receive a control signal and in response generate a high-side signal; a signal buffer circuit coupled to the signal conversion circuit and arranged to receive the high-side signal and in response generate a buffered signal; and a drive circuit coupled to the signal buffer circuit and arranged to receive the buffered signal and in response generate a gate drive signal that causes the switch to transition between the on-state and the off-state. In one aspect, the switch is an NMOS transistor having a gate, a source and a drain, where the source and drain are at substantially high voltage.

A high-noise-resistance and low-delay level shifting circuit for a GaN half-bridge driving chip is provided, relating to the technical field of power management in integrated circuits. A path from a floating power rail VDDH to the ground is arranged to simulate the noise generated when the voltage of the floating power rail in the level shifting circuit suddenly changes. Theoretically, a noise resistance performance can be achieved according to the present disclosure. In addition, only six PMOS transistors, one NLDMOS transistor and one inverter are added, having a simple structure.

A differential signal input buffer (200) is disclosed. The differential signal input buffer (200) may receive a differential signal that includes a first signal and a second signal and may be divided into a first section (260) and a second section (261). The first section (260) may buffer and / or amplify the first signal based on a first level-shifted second signal. The second section (261) may buffer and / or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section (260) may buffer and / or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section (261) may buffer and / or amplify the second signal based on a second level-shifted first signal.

An output buffer includes a first transistor, a second transistor, and a pad tracking circuit. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad tracking circuit is coupled to the first transistor and is configured to generate a gate control signal to a gate of the first transistor. The output buffer is selectively operable in an input mode and a failsafe mode, and the pad tracking circuit generates the gate control signal to the gate of the first transistor based on a voltage of the pad when the voltage of the pad is a high voltage level.

To suppress hot carrier deterioration without reducing an operation speed, in a semiconductor device that generates an output voltage having a voltage amplitude higher than a withstanding voltage of a transistor.SOLUTION: A P-type transistor MP0 and a P-type transistor MP2 are connected in series between a power supply terminal 11 and an output terminal 13. An N-type transistor MN0 and an N-type transistor MN2 are connected between a ground terminal 12 and a power supply terminal 13. The N-type transistor MN2 and the P-type transistor MP2 are on / off-controlled in a complementary manner in response to an input signal VIN. A gate voltage control circuit 110 changes at least one of gate voltages of the P-type transistor MP0 and the N-type transistor MN0 whose drains are electrically connected with the output terminal 13 so as to follow an output voltage VOUT at the output terminal 13 while maintaining an ON state of the P-type transistor MP0 or the N-type transistor MN0.SELECTED DRAWING: Figure 5

To suppress malfunction of a logic circuit by reducing a leakage current of a transistor.SOLUTION: A transistor including an oxide semiconductor layer functioning as a channel formation layer and having an off-state current per micrometer of channel width of less than or equal to 1*10-13A, a first signal, a second signal, and a third signal which is a clock signal are input as input signals, and a fourth signal and a fifth signal whose voltage states are set in accordance with the input first signal to third signal are output as output signals.SELECTED DRAWING: Figure 1

The application provides a floating N-well anti-inversion interface circuit, which comprises a power supply module, a gate tracking module, a floating N-well module, a floating N-well stabilizing module, an output driving stage module and a transistor. When a chip enters a low-power consumption state, the floating N-well module delivers a first high potential to the gate tracking module, and the gate tracking module outputs a second high potential to the control end of the transistor after receiving the first high potential, so as to disconnect the electrical connection between the power supply module and the output driving stage module. Anti-inversion is realized, and the chip is prevented from being mistakenly awakened. The cooperation of the gate tracking module, the floating N-well module, the floating N-well stabilizing module and the transistor realizes anti-inversion, and the anti-inversion of the voltage or current of the chip is more stable and reliable. The floating N-well module stabilizes the potential of the floating N-well module, so that the floating N-well module provides a stable first high potential, and the anti-inversion stability is further improved, thereby solving the problems in the prior art.

The disclosure includes a p-channel output transistor MP1, of which the drain is connected to the output end; a gate drive circuit A1, which drives the gate voltage of the output transistor; and an n-channel pull-up transistor NAT, which is connected to the gate of the output transistor MP1, and is turned on when the output transistor is OFF to pull up the gate voltage. The output transistor MP1 is of an enhanced type with a relatively high threshold voltage for being turned on, and the pull-up transistor NAT is of a native type with a relatively low threshold voltage for being turned on.

According to an embodiment, a high-voltage tolerant level shifter circuit includes input terminals for receiving complementary PWM input signals, output terminals for providing complementary output signals, and a latch circuit for translating the input signals to the output signals. The circuit has terminals for receiving floating ground and supply voltages, and a control circuit to ensure operation within a known state. The latch circuit includes cross-coupled PMOS and NMOS transistors. NMOS input transistors are coupled to the latch circuit through cascode NMOS transistors. The floating voltages are generated based on a pre-regulated supply voltage, tracking ground over a first voltage range and controlled by ratio relationships over a second range. A monitoring circuit generates control signals based on the pre-regulated supply voltage. The level shifter enables efficient voltage domain transfers at higher operating supplies using low-voltage devices, avoiding additional mask layers and reducing manufacturing costs and complexity.

A high-speed circuit with a high-voltage (HV) driver circuit. The high-speed circuit has a driver circuit and a level shifter. The driver circuit includes HV components which are operated in an HV domain. The level shifter includes low-voltage (LV) components which are operated in an LV domain. The level shifter translates signals from the LV domain to the HV domain to generate control signals for the driver circuit. The high-speed circuit may include a protection voltage generator converting a power supply voltage and a power ground voltage to generate a first direct-current bias voltage (VBP) and a second direct-current bias voltage (VBN) to bias the LV components of the level shifter. The LV components of the level shifter include input transistors and protection transistors. Gate voltages of the protection transistors may be tied to VBP or VBN.