12results about "Computing operation arrangements" patented technology

Systems, methods, and devices for predictive maintenance of machinery are provided. An exemplary apparatus includes a vibration sensor configured to sense vibrations of a vibration source and an analog circuit. The analog circuit includes a plurality of operational amplifiers and a plurality of resistors. The analog circuit is coupled to the vibration sensor and configured to receive an analog signal from the vibration sensor and to calculate an output based on the analog signal by executing a portion of a trained neural network.

The present invention relates to the field of artificial intelligence technology, and discloses an analog computer chip; the analog computer chip includes an input layer, N addition layers and an output layer; each addition layer includes multiple adders; each input interface in the input layer is connected to each adder in the first addition layer through different operation units; in the N addition layers, each adder in the upper addition layer is connected to each adder in the lower addition layer through different operation units; each operation unit has a transfer function corresponding to its node parameter; and multiple adders in the Nth adder layer are connected one-to-one with multiple output interfaces in the output layer; the operation units and adders are both composed of analog devices. In the above scheme, using the analog computer chip as an artificial intelligence chip can reduce the size of the artificial intelligence chip, increase the speed of the artificial intelligence chip, and reduce the power consumption of the artificial intelligence chip.

The present invention discloses an unsupervised learning circuit of Hall bar synapse based on pulse amplitude, including an STDP algorithm circuit, a front amplitude control circuit, a rear amplitude control circuit and a weight adjustment circuit. The STDP algorithm circuit is used to generate an enhancement signal or an inhibition signal according to the arrival order of the pre-synaptic and post-synaptic neuron pulses, and control the direction of the pulses applied to the two ends of the Hall bar in the weight adjustment circuit. The amplitude control circuit generates a pulse signal of corresponding duration according to the action time of the synaptic neuron pulse, and adjusts the abnormal Hall resistance value. The weight adjustment circuit receives the enhancement signal or inhibition signal output by the STDP algorithm circuit, determines the direction of applying the pulse signal to the Hall bar, and realizes the increase or decrease of the abnormal Hall resistance value of the Hall bar. The present invention can be used to store the energy of the time difference between the front and rear neuron pulses and to adjust the abnormal Hall resistance value, and has the advantages of high adjustment accuracy and simple circuit structure.

Systems, methods, and apparatus are provided for predictive maintenance of a machine. An example apparatus includes a vibration sensor configured to sense vibration of a vibration source and an analog circuit. The analog circuit includes a plurality of operational amplifiers and a plurality of resistors. The analog circuit is coupled to the vibration sensor and is configured to: receive an analog signal from the vibration sensor; and calculating an output based on the analog signal by executing a portion of the trained neural network.

Systems, methods, and devices are provided for predictive maintenance of machines. An example apparatus includes a vibration sensor configured to sense vibrations of a vibration source and an analog circuit. The analog circuit comprises a plurality of operational amplifiers and a plurality of resistors. The analog circuit is coupled to the vibration sensor and configured to: receive an analog signal from the vibration sensor; and compute an output based on the analog signal, by performing a portion of a trained neural network.

The utility model provides the differential sampling calculation circuit formed by the operational amplifier, the divider resistor of the differential sampling calculation circuit adopts a common high-precision resistor to replace an ultra-high-precision divider resistor, and the divided output voltage is not directly connected with the sampling signal error amplifier, so that more stable and efficient output voltage sampling can be realized. The circuit comprises a sampling signal error amplifier IC1, and a differential sampling circuit is arranged between the sampling signal error amplifier IC1 and a positive end VO + and a negative end VO-of output voltage, so that the output voltage is prevented from being directly connected with the sampling signal error amplifier in a partial voltage manner, efficient output voltage sampling can be realized, and the safety of the whole circuit is guaranteed.

The present invention relates to the field of artificial intelligence technology, and discloses an analog computer chip with an on-chip training system. In the computing structure of the analog computer chip, the input end of the analog computer chip is connected to the output end of the analog computer chip through n-layer memories and n-layer operators, and two adjacent layers of operators are connected through a layer of memory; the on-chip training system includes an error threshold comparator, an n-layer trainer, and an n-layer updater; the output end of the analog computer chip is also connected to the error threshold comparator; the error threshold comparator is used to control the working state of the on-chip training system according to the difference between the actual output value and the expected output value of the output end of the analog computer chip. The on-chip training system is set in the analog computer chip of the present application, and the computing model is generated autonomously, and self-learning updates are performed, thereby improving the accuracy of the artificial intelligence chip and expanding the application scope of the artificial intelligence chip.

A method and an apparatus for processing an analog input signal and generating a corresponding analog output signal are disclosed. The input signal is supplied to an analog delay line comprising analog memory cells. A propagation signal causes the input signal to propagate through the sequence of memory cells in discrete time steps. Each memory cell is buffered and weighted by the stored analog parameters, and the sum of weighted memory cell values is accumulated as an analog signal. The result of accumulation is passed through an activation function. Multiple such blocks provide a convolutional neural network that works at extremely low power in comparison with its digital equivalent.

The present application provides a true random number generator and a random number generation method based on a magnetic tunnel junction device. The true random number generator provided by the present application includes a control circuit, a magnetic tunnel junction device, and a random number generator; the control circuit is used to provide multiple continuous voltage pulse signals to the magnetic tunnel junction device, causing the resistance of the magnetic tunnel junction device to oscillate; the multiple voltage pulse signals correspond to different flipping probabilities of the magnetic tunnel junction device, and after the multiple continuous voltage pulse signals act synergistically on the magnetic tunnel junction device, the magnetic tunnel junction device accumulates the flipping probabilities based on in-memory calculations so that the final flipping probability after accumulation tends to be half-and-half probability; the random number generator is used to generate random numbers based on the resistance state of the magnetic tunnel junction device after the multiple continuous voltage pulse signals are applied. The true random number generator and random number generation method based on the magnetic tunnel junction device provided by the present application can generate random numbers with high randomness and uniform distribution.

There is provided a circuit comprising a mirrored enhanced Howland current source, the mirrored enhanced Howland current source comprising an input and an output; and a feedback loop, the feedback loop comprising: an instrumentation amplifier arranged to measure a current at the output of the mirrored enhanced Howland current source; a comparator arranged to compare an output of the instrumentation amplifier to a reference voltage source; an integrator electrically coupled to the output of the comparator; a multiplier arranged to multiply the output of the integrator with the reference voltage, wherein the output of the multiplier is electrically coupled to the input of the mirrored enhanced Howland current source.

A method and an apparatus for processing an analog input signal using an analog neural network and generating a corresponding analog output signal are disclosed. An analog input interface is configured to supply a task input signal and a compensation input signal. One or more analog neuron circuits are connected to the analog input interface. An analog parameter storage array modifies task input signals and supplies these to an analog computation circuit that generates an output signal based on a combination of contributions from the modified task input signals and the compensation input signal.