44 results about "Analogue filter" patented technology

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

A system includes a processing chamber configured to perform a plasma process with respect to one or more substrates. The system further includes an electrostatic chuck disposed within the processing chamber. The electrostatic chuck includes one or more electrodes. The system further includes an analog filter electrically coupled to at least one electrode of the one or more electrodes. The analog filter includes an air-core coil including a first coil and a second coil disposed within the first coil. The first coil and the second coil together form an inductor.

A nested Δ-Σ analog-to-digital conversion system and method, compromising: an analog filter, an analog comparator, a first feedback digital-to-analog converter (DAC), a second feedback DAC placed in front of the first feedback DAC, and a digital filter and an MSB quantizer placed at the output of the analog comparator; wherein the input of the first feedback DAC is connected to the output of the analog comparator; the analog filter, the analog comparator, and the first feedback DAC form an internal analog Δ-Σ loop; the input of the second feedback DAC is connected to the output of the MSB quantizer; the output of the second feedback DAC is connected to the output of the first feedback DAC and to the input of the analog filter; and the second feedback DAC, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop.

The invention discloses a stop-band residual compensation method and device of a digital filter, a storage medium and a computer program product, and relates to the technical field of audio signal processing, and the method comprises the steps: collecting an original audio signal and a digital filtering signal; the digital filtering signal and the original audio signal are synchronously input into a pre-constructed stop-band residual noise dynamic compensation model to be processed, a smooth transition signal is obtained, and the stop-band residual noise dynamic compensation model takes a hardware filtering signal output by a hardware simulation filter as a target label; and superposing the smooth transition signal and the digital filtering signal according to a preset superposition proportion to obtain a calibration signal. The stop-band residual noise dynamic compensation model learns smooth transition characteristics when the hardware simulation filter reproduces parameter adjustment, and the flexibility of the digital filter is considered, so that the response speed when the digital filter adjusts the cut-off frequency in real time at high frequency is improved, and the stop-band residual energy at the moment of cut-off frequency adjustment is inhibited.

The invention discloses a zero-sequence current acquisition and analysis device and method for a power secondary circuit, and belongs to the field of power systems. The device comprises a current transformer, a temperature sensor, a front-end analog filter, an ADC, a rear-end digital filter, a self-adaptive wave trap, a processor and an alarm. Wherein the output end of the current transformer is connected to the processor through the front-end analog filter, the ADC and the rear-end digital filter in sequence; and the processor is also respectively connected with the temperature sensor and the alarm. According to the invention, real-time acquisition and early warning of the zero-sequence current are realized, and high precision and stability of an acquisition result in a full temperature range are ensured at the same time.

The invention relates to the technical field of broadband signal synthesis and high-speed digital-to-analog conversion, in particular to an oversampling-based real-time frequency interleaving digital-to-analog conversion system aliasing suppression method and system, and aims to solve the problem of spectrum aliasing caused by non-ideal characteristics of a digital sub-band decomposition filter and an analog filter under a real-time architecture of the system. In the invention, the sub-band decomposition is completed by adopting the linear phase complementary filter bank, so that distortion introduced by a transition band of a digital filter is avoided; by restraining system parameters such as passband and stopband frequencies and local oscillation frequency of a sub-band decomposition filter, a protection band is set by an oversampling mechanism, a frequency margin is reserved for a transition band of the filter, and aliasing components are suppressed. According to the method, extraction aliasing of a digital domain and mirror image aliasing of an analog domain are avoided at the same time from the system architecture, the frequency spectrum purity of output signals is improved, the method is suitable for a real-time system for processing continuous data streams, and technical support is provided for achieving a high-performance broadband signal source.

A continuous-time analog-to-digital converter circuit includes an input configured to receive an analog input signal; a delay element with a specified time delay, the delay element functionally connected between the input and a first summation node; a ADC-DAC path with a sub ADC and a sub DAC connected between the input and the first summation node. The ADC-DAC path is configured to digitize the analog input signal and to reconvert the digitized signal to analog domain and to subtract it at the first summation node. An output of the first summation node is filtered by means of a continuous-time filter and an output of the continuous-time filter is clocked by a specified sampling rate. A backend ADC is configured to digitize the clocked output of the analog filter and to connect the clocked output to a second summation node. An output is obtained by a summation of the output of the backend ADC and an output of a digital filter is connected to the sub ADC. The digital filter is configured to represent a replica of a transfer function of the sampled output of the continuous-time filter in the digital domain.

The invention discloses a bearing fault classification method based on a decision tree algorithm full-analog circuit, and the method comprises the steps: enabling various bearing fault signals to pass through two layers of analog filters in sequence, and enabling the difference between the root mean square values of a low-pass output signal and a high-pass output signal of each layer of analog filter to serve as a decision condition, classifying and coding various bearing fault signals to obtain simulation signal codes; the currently collected bearing fault signal is successively introduced into two layers of programmable control filters with the same parameters as the two layers of analog filters, the difference between root mean square values of a low-pass output signal and a high-pass output signal of each layer of programmable control filter is used as a decision condition, and the current bearing fault signal is coded to obtain a current signal code; and comparing the current signal code with the simulation signal code to determine the current bearing fault signal type. According to the invention, the original continuous vibration signals collected on the motor can be directly classified, and the advantages of more convenient operation, faster classification speed, lower energy consumption and the like can be realized.

The invention discloses a 12-lead electrocardiosignal acquisition universal module, which relates to the technical field of electrocardiograph detection and comprises a signal conditioning acquisition module, an analog filter module, a main controller module, a power management module, a 12-lead electrocardiosignal pin, an inter-board communication pin and a power pin. A human body electrocardiosignal is transmitted to the analog filter module through the 12-lead electrocardiosignal pin; the filtered signals are transmitted to the signal conditioning and collecting module and are converted into digital signals which are transmitted to the main controller module; the main controller module transmits data to external equipment through an inter-board communication pin, and configures parameters of the signal conditioning acquisition module and the analog filter module based on an instruction issued by the external equipment; the power supply pin is connected with electric energy, and the power supply management module supplies power to each module. The module has the characteristics of high integration, adjustable parameters and interference resistance, and is directly welded to a user development board through a stamp hole pin process, so that standardized rapid integration is realized, and the development cycle of 12-lead electrocardiosignal acquisition equipment in different scenes is shortened.

A data acquisition circuit includes a plurality of signal processors including a first analog chopper circuit, an amplifier, a second analog chopper circuit, and an analog filter that are coupled in series, respectively. The data acquisition circuit during a first mode converts analog signals from analog filters into a serial signal and converts the serial signal into a digital signal, and filters the digital signal after converting the digital signal into parallel signals. The data acquisition circuit during a second mode converts the analog signals from the amplifiers into the serial signal and converts the serial signal into the digital signal, outputs the digital signal to the digital chopper circuit, and filters the digital signal after converting the digital signal from the digital chopper circuit into parallel signals. Thus, biological information in the plurality of frequency bands can be appropriately acquired.

An analog filter circuit includes an active filter configured to filter a transmission signal, the active filter including an active element to which a power supply voltage is applied, and a passive filter connected to an output terminal of the active filter, the passive filter including a passive element having a dynamically variable impedance.

The utility model discloses an analog-digital hybrid filter for electrocardiosignal noise reduction processing, and relates to the field of signal noise reduction. The analog filter is a band-pass filter and comprises a low-pass filter and a high-pass filter which are connected in sequence, and the low-pass filter comprises a series inductor and a parallel capacitor; the high-pass filter comprises a parallel inductor, a series capacitor and a radio frequency port connected with the low-pass filter, and the series capacitor in the high-pass filter and the series inductor in the low-pass filter are connected in series to form radio frequency signal output; the output of the radio frequency signal is connected with the signal amplifier, the output port of the amplifier is connected with the analog signal input end of the ADC converter, and the digital signal output port of the ADC converter is divided into a plurality of paths which are respectively connected to the digital filter. By combining analog filtering and digital signal processing technologies, the quality of electrocardiosignals can be effectively improved, the real-time performance of signal processing is improved, and the design flexibility is enhanced.

The utility model discloses a blasting data acquisition circuit based on an FPGA, and belongs to the technical field of blasting data acquisition. Comprising a field programmable gate array (FPGA) which is connected with an analog-to-digital converter (ADC) and an advanced RISC machine (ARM) processor. The input end of the analog-to-digital converter ADC is connected with three four-order analog filters, and the three four-order analog filters are respectively used for filtering X-direction, Y-direction and Z-direction signals; and the ARM processor is connected with a nonvolatile storage device FLASH, an SDRAM (Synchronous Dynamic Random Access Memory) and an external device. According to the utility model, through combination of the FPGA, the ADC and the ARM, the precision, real-time performance and flexibility of data acquisition can be improved, the overall power consumption is reduced, and the overall performance is improved. The FPGA is used for processing high-speed data, and the ARM is used for subsequent processing, so that the system delay can be reduced, and the throughput can be improved. And the FPGA is used for processing real-time tasks, and the ARM enters a low-power-consumption mode when being idle, so that the overall power consumption can be reduced.

Embodiments of the present disclosure relate to systems, methods, apparatuses, and computer program products that align filter configurations between a device and a network. A method can include transmitting capability information to a network element. The method can also include receiving a radio resource configuration from the network element, the radio resource configuration including parameters for support of frequency arrangement and dynamic analog filter bandwidth switching determined from a local oscillator, and at least one parameter range. The method can further include maintaining a current local oscillator arrangement and analog filter configuration, or switching to a new local oscillator arrangement and analog filter bandwidth configuration, based on the radio resource configuration.

An FMCW-radar based distance measuring device is characterized in that, in addition to analogue high-pass and low-pass filtering, the evaluation signal typical for FMCW additionally undergoes subsequent digital filtering. In this case, the analogue / digital conversion takes place by oversampling. As a result, according to the invention, all those frequencies in the evaluation signal that are above or below the frequency corresponding to the distance of the object are effectively suppressed. At the same time, the analogue filters can be constructed with a very low level of complexity. The space requirement and the costs of the analogue components is reduced thereby. In addition, the dependence on temperature of the distance measuring device is reduced thereby. The potentially high distance resolution is also maintained.

The present invention discloses a low-noise dual-output synchronous demodulation circuit and method. The synchronous demodulation circuit includes a signal source to be measured, a reference signal source, a pulse generator, a voltage comparator, a logic operator, a reversible counter, a digital-to-analog converter, a digital filter, and an analog filter. A sinusoidal reference signal is generated by the pulse generator as a digital pulse signal. A sinusoidal voltage signal is generated by the voltage comparator and the logic operator as a synchronized pulse count signal. The reversible counter and the digital-to-analog converter are used to obtain a digital voltage signal and an analog voltage signal. Real-time looping is used to maintain the consistency of the voltage value of the sinusoidal voltage signal when the analog voltage signal is synchronized with the digital pulse signal. This synchronous demodulation method can effectively reduce high-frequency components and improve the signal-to-noise ratio of the demodulated signal. The synchronous demodulation circuit can directly provide dual outputs of a digital demodulation signal and an analog demodulation signal.

Variable Gauge Analog Filter The present invention relates to a variable gauge analog filter (10) comprising, between an input (18) for a frequency signal (22) to be filtered and an output (20) for a filtered signal (24). The filter comprises a set of filtering impedances (26) with at least one variable capacitor (28, 32) disposed between a high point and a low point, and comprising a control input (21) for a control voltage (of the capacitor's capacitance). The variable capacitor (28) is a main transistor (28) whose source and drain form the high and low points respectively, the control input (21) being connected to the drain, the source and gate being connected to electrical potentials for operation of the main transistor (28) in a cutoff state. Figure for the abstract: Figure 1

The optical fiber sensor adaptive filter of the present invention includes a front-end digital filter and a back-end analog filter. The front-end digital filter adopts filtering using an FIR filter adaptive filtering coefficient, estimates the FIR length N through frequency deviation, obtains the correlation coefficient n, and sets N and corresponding weights according to the correlation coefficient and frequency accuracy, that is, the resolution requirement. The weight value is improved by an additional momentum method, which can avoid overfitting or underfitting and ensure filtering performance. The back-end analog filter adopts attenuation + variable impedance acquisition + transformer primary frequency selection and transformer secondary induction tuning, and finally filters through an adjustable harmonic filter and an LC frequency selection network, which can effectively filter noise interference and improve measurement accuracy.

Linear time-invariant (LTI) filters are a staple of modern signal processing. LTI filters perform many operations including signal estimation, bandpass / stopband selection, encoding / decoding, modulation / demodulation, etc. Most modem LTI filters operate in the digital domain due to the flexibility of programming digital processors. However, this means that the incoming signal must be digitized. This introduces the signals to the bottlenecks and latency of digital computing, where digital electronics cannot process the increasing high data-rate and high-bandwidth data in dense spectral environments in real-time. The programmable analog LTI (PA-LTI) architecture is a hardware accelerator that performs real-time LTI operations in the analog domain and is fully programmable, enabling unprecedented acceleration of front-end PHY layer communications processing. Conventional analog LTI processors, such as RLC circuits or amplifiers, can perform only one LTI function. A PA-LTI processor can be digitally programmed to implement any arbitrary finite impulse response (FIR) LTI operation in the analog domain.

A nested Δ-Σ analog-to-digital conversion system and method, comprising: an analog filter, an analog comparator, and a first feedback digital-to-analog converter connected in sequence; a second feedback digital-to-analog converter disposed before the first feedback digital-to-analog converter; and a digital filter and an MSB quantizer disposed at the output end of the analog comparator. The input end of the first feedback digital-to-analog converter is connected to the output end of the analog comparator. The analog filter, the analog comparator, and the first feedback digital-to-analog converter form an internal analog Δ-Σ loop. The input end of the second feedback digital-to-analog converter is connected to the output end of the MSB quantizer. The output end of the second feedback digital-to-analog converter is connected to the output end of the first feedback digital-to-analog converter and the input end of the analog filter. The second feedback digital-to-analog converter, the internal analog Δ-Σ loop, the digital filter, and the MSB quantizer form an external hybrid Δ-Σ loop. By means of the nested external digital-to-analog external hybrid Δ-Σ loop, the present invention dynamically adjusts the signal swing of the internal analog Δ-Σ loop, thereby reducing the design difficulty of the internal analog Δ-Σ loop and significantly improving the energy efficiency and accuracy.

The present invention relates to a distance measuring device (1) based on an FMCW radar that is particularly advantageous for measuring a filling level, and a method for operating the distance measuring device (1). The distance measuring device (1) is characterized in that, in addition to analog high-pass filtering and analog low-pass filtering, an evaluation signal (IF) that is typical for FMCW also undergoes subsequent digital filtering. In this case, the analog / digital conversion takes place by means of oversampling. As a result, according to the invention, all those frequencies (f IF ) above or below the frequency corresponding to the distance (d) of the object (2) in the evaluation signal (IF) are effectively suppressed. At the same time, the analog filters (131, 132, 133) can be constructed with a very low level of complexity. Thereby, the space requirements and costs of the analog components (131, 132, 133) are reduced. Additionally, the temperature dependence of the distance measuring device (1) is reduced thereby. A potentially high distance resolution is also maintained.

The application discloses a stopband residual compensation method and device of a digital filter, a storage medium and a computer program product, relates to the technical field of audio signal processing, and the method comprises the steps of collecting an original audio signal and a digital filtering signal; inputting the digital filtering signal and the original audio signal into a pre-constructed stopband residual noise dynamic compensation model synchronously for processing to obtain a smooth transition signal, wherein the stopband residual noise dynamic compensation model takes a hardware filtering signal output by a hardware analog filter as a target label; and superimposing the smooth transition signal and the digital filtering signal at a preset superimposition ratio to obtain a calibration signal. The stopband residual noise dynamic compensation model learns the smooth transition characteristics when the hardware analog filter reproduces parameter adjustment, takes into account the flexibility of the digital filter, thereby improving the response speed when the digital filter adjusts the cutoff frequency in real time at a high frequency, and suppressing the stopband residual energy at the moment of cutoff frequency adjustment.

The utility model belongs to the technical field of filter debugging, and particularly relates to a press-down tester for a filter with a shielding case, which comprises a debugging bracket; the debugging assemblies are arranged on the two opposite sides of the edge part of the debugging table; and the downward pressing assembly comprises a floating pressing head and a first driving mechanism for driving the floating pressing head to perform downward pressing action, and the floating pressing head and the first driving mechanism are connected through a connecting rod. The pressing cylinder drives the floating pressure head at the end part to press the dielectric filter, and the floating mechanism arranged in the floating pressure head can perform buffering, so that the dielectric filter cannot be damaged due to rigid impact during pressing; meanwhile, a floating ball and a floating groove are arranged, so that the pressure head body is always in press fit with the surface of the to-be-tested filter, and damage caused by uneven stress of the dielectric filter due to imbalance of a machine is prevented; the guide assembly assists the floating pressing head in pressing down, and it is guaranteed that the direction is stable and uniform in the pressing down process; a shielding case is arranged to simulate the actual use scene of the filter.

The present invention provides a method and apparatus for generating RF signals. [Solution] A method and apparatus for generating an RF signal uses digital signal components to generate a composite RF signal having multiple frequency components. An analog filter is used to filter the composite RF signal. The analog filter is an adjustable active feedback circuit having one or more variable resonators and a variable gain block connected to a signal loop defined by a passband. The analog filter is adjusted so that the passband of the analog filter overlaps with one or more desired frequency components of the multiple frequency components of the composite RF signal, and the passband has a relative bandwidth of about 1% or less.

The embodiment of the present application discloses a kind of wideband amplifier and analog filter, wherein, wideband amplifier, it is arranged in analog filter, analog filter includes multiple bandwidth modes, wideband amplifier includes: gain circuit;Gain circuit includes: first amplification subcircuit and second amplification subcircuit;First amplification subcircuit is used to amplify the input signal and process;Second amplification subcircuit is used to reconfigure according to the bandwidth mode of analog filter, also for amplifying the input signal after amplification processing.The technical scheme provided by the embodiment of the present application can configure amplifier when filter is in different bandwidth mode, while guaranteeing the performance of filter, also realizes power consumption optimization.

The invention relates to a multi-tone signal separation system and method, and the system comprises a signal source, an adder circuit, a multi-path pre-filtering circuit, a clock source circuit, a level adjustment circuit, a low-pass filter, a single-chip microcomputer and a phase-locked loop circuit, and the multi-path pre-filtering circuit controls the cut-off frequency of the multi-path pre-filtering circuit through a received clock signal. Carrying out pre-filtering on the mixed multi-tone signal; the phase-locked loop circuit is used for locking multi-tone mixed signals containing a plurality of similar frequencies, extracting single-tone signal components, forming square wave signals and outputting the square wave signals; the low-pass filter is used for carrying out low-pass filtering on the square wave signal extracted and output by the phase-locked loop and restoring each single-tone signal; and the single-chip microcomputer controls the cut-off frequency of the multi-path pre-filter circuit. The beneficial effects are that the separation system and method are suitable for multi-tone mixed signal separation scenes with similar amplitudes and similar frequencies, the separation effect is far higher than that of a traditional method using a high-order analog filter, and the system and method have the advantages of simple structure, low cost, automatic measurement and strong expansibility.

The invention provides an analog filter unevenness compensation method and system, and the method comprises the steps: carrying out the full-load scheduling of a known modulation symbol on a channel bandwidth, forming first frequency domain data used for generating calibration data, converting the first frequency domain data to a time domain for timing deviation compensation, and obtaining the calibration data on the frequency domain of an analog filter, and compensating the service data in the frequency domain according to the calibration data. Known modulation symbols are dispatched on channel bandwidth in a full-load mode, calibration data on a frequency domain are obtained after timing deviation estimation, and then the calibration data can be used for directly conducting unevenness compensation on the frequency domain according to subcarriers. The method can well reflect the passband amplitude and phase unevenness characteristics of the analog filter in the frequency domain, and reduces the operation complexity at the same time.

The invention relates to the technical field of wireless communication, in particular to a broadband IQ imbalance and group delay joint calibration implementation method and device and a storage medium, and the method comprises the following steps: arranging a correction filter between the input end of an I channel baseband signal and the input end of a Q channel baseband signal of a radio frequency transmission link; the correction filter is arranged behind the input end of the Q-channel baseband signal of the radio frequency transmitting link; converting the IQ two paths of baseband signals into analog signals through a DAC, processing the analog signals through an analog filter BBF, sending the processed analog signals into a frequency mixer, and outputting radio frequency signals; configuring an observation channel for the radio frequency signal; inputting the radio frequency signal, the I-channel baseband signal and the Q-channel baseband signal into a preset QEC calibration module to perform IQ calibration on a radio frequency transmitting link; the IQ calibration comprises initial calibration and real-time tracking calibration. According to the invention, IQ calibration and group delay calibration in a coverage full power range can be realized, temperature drift is suppressed, and performance and resource consumption are considered.

The present invention discloses an improved intercom, which mainly improves the intermediate frequency demodulation circuit and audio processing circuit of the receiving circuit. In the intermediate frequency demodulation circuit, a DSP demodulator module is used to replace the intermediate frequency amplifier, intermediate frequency demodulator IC, two-way ceramic filters and ceramic discriminator in the prior art; in the audio processing circuit, an audio processing module is used to replace the audio buffer amplifier circuit, audio high-pass filter circuit and audio low-pass filter circuit in the prior art. A digital filter as a second intermediate frequency filter is integrated inside the DSP demodulator module, and no additional ceramic filter is required. Not only are there fewer discrete components and a small size, but the digital filter also has a strong out-of-band suppression capability. A digital filter is integrated in the audio processing module, and the digital filter can filter the sub-audio signals below 300Hz more thoroughly and cleanly than the analog filter, avoiding the crosstalk of the sub-audio, and has a higher signal-to-noise ratio than the analog filter.