6 results about "Offset cancellation" patented technology

This disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an interlayer insulating film disposed on a substrate and having a recessed portion of the substrate exposed; a bottom electrode contact embedded in at least a portion of the recessed portion; a magnetic tunnel junction (MTJ) layer disposed on the interlayer insulating film and the bottom electrode contact; and a offset cancellation layer with a magnetization direction parallel to the antiparallel side of a fixed layer, wherein the offset cancellation layer may include a Co alloy, Fe alloy, Ni alloy, or Mn alloy comprising at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals, or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy comprising one selected from the group consisting of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B.

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to an amplification circuit, a control method and a memory, comprising: a sensing amplification circuit comprising a readout node, a complementary readout node, a first node and a second node; an isolation circuit is configured to, in a sensing amplification phase, couple the readout node to a bit line and couple the complementary readout node to a complementary bit line; an offset cancellation circuit is configured to, in an offset cancellation phase, couple the bit line to the complementary readout node and couple the complementary bit line to the readout node; a first power supply circuit is coupled to the first node and comprises a first power supply and a second power supply, the power supply voltage of the first power supply being higher than that of the second power supply; the first power supply circuit is configured to, in the offset cancellation phase, couple the first power supply to the first node, and in the sensing amplification phase, couple the second power supply to the first node, so as to shorten the processing time of the offset cancellation phase, thereby optimizing the performance of the memory.

This application is directed to a data interface having an input interface for receiving a differential input signal and a reference interface for providing a predefined reference voltage. A high pass filter is coupled to the input interface, and configured to filter the differential input signal and generate a filtered differential input signal. A differential integrator is coupled to the high pass filter and reference interface, and configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal. Each of the first and second output signals has a common mode output voltage substantially equal to the predefined reference voltage. In some embodiments, the data interface includes a connector including a plurality of data lanes and a pair of command pins that are distinct from the data lanes and coupled to the input interface.

The application discloses a CTLE (Continuous Time Linear Equalizer) based on a single amplifier and having a DC offset and common-mode voltage modulation function, and mainly solves the technical problem that the DC working point of the existing CTLE is easily affected by process deviation, input signal common-mode voltage and current mismatch, and an additional DC offset elimination loop is needed, thereby increasing the design and area complexity. The CTLE comprises a first-stage equalization unit EQ1, a second-stage equalization unit EQ2, a low-pass filter LPF, a frequency compensation unit and an offset and common-mode multiplexing amplifier OCMA. The CTLE adopts a single offset and common-mode multiplexing amplifier OCMA, simultaneously completes DC offset elimination and DC output control, and can reduce the design and area complexity.

This invention relates to the field of quantum communication technology and discloses an anti-interference quantum key distribution protocol optimization method, comprising: acquiring the single-photon counter count statistics output by the measurement end during the key screening stage, including signal state, decoy state, and vacuum state count values; calculating the instantaneous variance of the vacuum state count value and determining a counting correction parameter based on the ratio of the variance to the signal state count value; using the parameter to correct the gain deviation of the single-photon counter count statistics; extracting the polarization deviation feature vector from the corrected statistics and determining the bit offset parameter; and performing bit-level logic remapping on the key screening sequence based on the bit offset parameter to compensate for channel disturbances when the polarization control voltage at the measurement end is constant. This invention converts the basis vector deflection into an address offset through protocol layer logic mapping, eliminates the occupation of the link by hardware calibration, ensures the continuity of key generation under environmental disturbances, avoids background noise introduced by strong light pilots, and improves quantum key distribution efficiency.

This invention relates to the field of wireless sensing, and in particular to a baseband amplifier, elimination circuit, and chip for temperature compensation and DC offset cancellation. The baseband amplifier includes a fully inverting amplifier, a power supply circuit, and multiple DC offset cancellation circuits. The power supply circuit includes an LDO circuit, a gain temperature compensation circuit, and a resistor divider network. The gain temperature compensation circuit provides the LDO with a temperature reference voltage that compensates for the amplifier's gain temperature degradation characteristics and a zero-temperature drift reference current. The output of the LDO, after being divided by the resistor divider network, serves as a reference voltage V. CM The DC offset cancellation circuits are connected across each transimpedance amplifier, and are configured according to V. CM This invention generates a control current in real time to counteract the unbalanced DC current injected by the pre-amplifier mixer. It solves the problems of gain instability, multi-source offset, and difficulty in balancing circuit overhead and accuracy in existing fully inverter-type amplifiers.