37 results about "Offset cancellation" patented technology

In a microelectromechanical system (MEMS) sensor, movement of a component such as a proof mass due to a force of interest is sensed capacitively. A capacitance-to-voltage (C2V) converter receives a capacitance signal from the sensor and outputs a signal that includes an offset in addition to a signal of interest. The output signal is analyzed to identify the offset portion of the output signal and to modify values one or more variable capacitors coupled to the C2V input reduce the offset portion of the output signal.

The invention discloses a low-kick-back low-detuning dynamic comparator with cross coupling pair transistors and an operation method, and belongs to the technical field of analog integrated circuits. The comparator comprises a pre-amplification stage and a regeneration stage, the pre-amplification stage is composed of a reset module I, an offset elimination module, a cross coupling module and a pre-amplification module, and the regeneration stage is composed of a reset module II, an enabling module and a latch comparison module. According to the operation method, a complete period is divided into four stages of resetting, offset elimination, sampling and comparison, wherein key nodes are initialized in the resetting stage; in the offset elimination stage, offset voltage of the input geminate transistors is stored through a capacitor. In the sampling stage, an input signal is coupled with a stored offset voltage, and introduction of additional offset is avoided; in the comparison stage, a cross coupling module is used for regulating and controlling the discharge rate, kickback noise is restrained, the comparison precision is improved, and finally signal latching is completed through a regenerative-stage positive feedback mechanism.

The invention provides a frequency deviation estimation method and device, electronic equipment and a storage medium, and relates to the technical field of communication. Wherein the frequency modulation signal comprises a frequency linear increase signal and a frequency linear decrease signal; demodulating with the frequency linear increase signal and the frequency linear decrease signal based on the received signal to obtain a target increase signal and a target decrease signal; determining a target receiving signal according to the target increasing signal and the target decreasing signal; the target received signal is a signal obtained after offset elimination is carried out on the received signal; and performing offset estimation according to the target received signal and the pilot signal to obtain a target frequency offset result. According to the technical scheme, on the basis of combination of the frequency modulation signal and the pilot signal, offset elimination is carried out on the receiving signal through the frequency modulation signal to obtain the target receiving signal, accurate offset estimation is carried out on the target receiving signal through the pilot signal to obtain the target frequency offset result, and the accuracy of offset estimation is improved.

A method for obtaining neural signals from a neural signal sensor includes extracting sensor offset from a neural input signal. Sensor offset is removed from N-channels that share a single amplifier. The neural input signal is acquired from the analog domain by neural electrodes with varying DC-offset and the method includes multiplexing the N-channels via a time divisional multiple access procedure into a single neural amplifier An integrated digitally assisted neural recording system includes an analog multiplexer structured to receive N-channels and to multiplex the N-Channels into a single neural amplifier. A feedback loop is configured to cancel electrode offset voltage in the digital domain by generating electrode offset voltage samples and adding delay to align each electrode offset voltage sample to be subtracted at the neural amplifier in the analog domain.

A sense amplifier includes a first isolation transistor connected to a first memory cell through a first bit line, a second isolation transistor connected to a second memory cell through a second bit line, and sense amplifying circuitry connected to the first memory cell through the first isolation transistor, connected to the second memory cell through the second isolation transistor, and latch, to a pair of sense bit lines, data corresponding to a cell voltage stored in the first memory cell or the second memory cell, wherein the sense amplifying circuitry is configured to perform an offset cancellation operation while a charge sharing operation is performed between the first memory cell and the first bit line or between the second memory cell and the second bit line.

A comparator circuit for detecting an amount of variation in an input signal (Vlog) is provided, comprising a comparator having a non-inverting input (Vref_pos, Vref_neg) and an inverting input (Vcp, Vcn); a capacitor (Cp, Cn) connected between the inverting input and a terminal for applying the input signal as a voltage (Vlog); a reset switch (SWrp, SWrn) connected between the inverting input and an output (EPOS, ENEG) of the comparator; and a calibration switch (SWcp, SWcn) connected to select for the non-inverting input a voltage among a threshold voltage (Vth_pos, Vth_neg) and a calibration voltage (Vcal_pos, Vcal_neg).

To provide a semiconductor storage device capable of improving a sense margin of a sense amplifier, even if an offset cancellation operation sequence is executed for each of a plurality of sense amplifiers of a plurality of pages, and a control method thereof.SOLUTION: A semiconductor storage device includes a control unit that executes an offset cancellation operation sequence including at least one predetermined operation of supplying a power supply voltage common to all pages to the sense amplifier, for each sense amplifier on each page. The control unit is configured to control timing of executing the offset cancellation operation sequence in each page without executing the predetermined operation on the other page other than any other page, while executing the predetermined operation on any other page of the plurality of pages, when executing the offset cancellation operation sequence on each page of the plurality of pages.SELECTED DRAWING: Figure 6

This disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an interlayer insulating film disposed on a substrate and having a recessed portion of the substrate exposed; a bottom electrode contact embedded in at least a portion of the recessed portion; a magnetic tunnel junction (MTJ) layer disposed on the interlayer insulating film and the bottom electrode contact; and a offset cancellation layer with a magnetization direction parallel to the antiparallel side of a fixed layer, wherein the offset cancellation layer may include a Co alloy, Fe alloy, Ni alloy, or Mn alloy comprising at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals, or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy comprising one selected from the group consisting of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B.

A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.

The invention provides a semiconductor memory device and a control method thereof, which can improve sensing margins of sense amplifiers even when a plurality of sense amplifiers for each of a plurality of pages execute an offset cancellation operation sequence. The semiconductor memory device includes a control section configured to execute an offset cancellation operation sequence including at least a specified operation for supplying a power supply voltage common to each page to the sense amplifiers for each of the page. The control unit is configured so as to control, when the offset cancellation operation sequence is executed in each of the plurality of pages, a point in time at which the offset cancellation operation sequence is executed in each of the plurality of pages in a control manner in which a specified operation is not performed on other pages other than any one of the plurality of pages during a period in which the specified operation is performed on the any one of the plurality of pages.

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to an amplification circuit, a control method and a memory, comprising: a sensing amplification circuit comprising a readout node, a complementary readout node, a first node and a second node; an isolation circuit is configured to, in a sensing amplification phase, couple the readout node to a bit line and couple the complementary readout node to a complementary bit line; an offset cancellation circuit is configured to, in an offset cancellation phase, couple the bit line to the complementary readout node and couple the complementary bit line to the readout node; a first power supply circuit is coupled to the first node and comprises a first power supply and a second power supply, the power supply voltage of the first power supply being higher than that of the second power supply; the first power supply circuit is configured to, in the offset cancellation phase, couple the first power supply to the first node, and in the sensing amplification phase, couple the second power supply to the first node, so as to shorten the processing time of the offset cancellation phase, thereby optimizing the performance of the memory.

Semiconductor devices for synchronizing networks are described. The semiconductor device includes a timing circuit having a sub-sampling phase lock loop. The sub-sampling phase lock loop includes a radio frequency sampler circuit that is configured to generate at least one error signal corresponding to a phase difference between an output signal of a voltage-controlled oscillator and a reference signal and a transconductor circuit that is configured to generate a tuning signal based on the at least one error signal. The tuning signal is configured to tune the voltage-controlled oscillator. The sub-sampling phase lock loop further includes an adaptive bias circuit that is configured to generate a nulling signal based on an offset in the tuning signal created by the transconductor circuit and provide the nulling signal to the transconductor circuit. The transconductor circuit is configured to adjust the tuning signal based on the nulling signal.

The invention relates to a comparator, an analog-to-digital converter and an offset elimination method thereof. The comparator includes a comparator circuit, an offset calculation circuit, a hybrid offset voltage generation circuit, and an offset cancellation circuit. The comparator circuit is used for generating a decision signal according to an input signal. An offset calculation circuit is configured to calculate an offset of the comparator circuit according to the decision signal to generate a plurality of control signals. The hybrid offset voltage generation circuit is configured to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to the plurality of control signals, and perform a charge transfer operation using the first reference voltage and the second reference voltage to generate a plurality of correction voltages. The offset cancellation circuit is configured to cancel the offset according to the plurality of correction voltages.

The invention discloses a single amplifier-based CTLE with direct current offset and common mode voltage modulation functions, and mainly solves the technical problems that the direct current working point of the existing CTLE is easily influenced by process deviation, input signal common mode voltage and current mismatch, an additional direct current offset elimination loop is needed, and the design and area complexity is increased. The CTLE comprises a first-stage equalization unit EQ1, a second-stage equalization unit EQ2, a low-pass filter LPF, a frequency compensation unit and an offset and common-mode multiplexing amplifier OCMA. The CTLE adopts a single offset and common-mode multiplexing amplifier OCMA to complete direct current offset elimination and direct current output control at the same time, so that the design and area complexity can be reduced.

This estimation device comprises: an input unit that inputs channel state information (CSI) acquired by using a plurality of reception antennas and a plurality of transmission antennas; a first offset removal unit that divides the CSI among the reception antennas and that generates a first signal; a second offset removal unit that divides the CSI among the transmission antennas and that generates a second signal; a first phase difference correction unit that corrects the phase of a dynamic component extracted from the first signal by using a static component extracted from the second signal and that generates a third signal; a second phase difference correction unit that corrects the phase of a dynamic component extracted from the second signal by using a static component extracted from the first signal and that generates a fourth signal; an AoD estimation unit that estimates the AoD, which is the transmission direction of the radio wave, by using the third signal; and an AoA estimation unit that estimates the AoA, which is the arrival direction of the radio wave, by using the fourth signal.

The invention relates to the technical field of analog integrated circuits, in particular to a high-speed comparator circuit with a self-return-to-zero preamplifier. Aiming at the problems that the precision of a traditional comparator is reduced due to offset voltage of a pre-amplifier and the response speed of a latch stage is limited, the invention provides an optimized structure integrating a self-return-to-zero technology and a dynamic latch. The circuit comprises a self-return-to-zero preamplifier which stores offset voltage in a reset stage through a switched capacitor network and realizes offset cancellation in a working stage; and the dynamic latch stage adopts a positive feedback cross coupling structure and is matched with a differential signal output by the preamplifier to realize rapid level judgment. The input offset voltage is reduced to the microvolt level through the self-return-to-zero technology, meanwhile, the delay time of the dynamic latch is shortened by more than 30% compared with that of a traditional structure, and the dynamic latch is suitable for the scene that a high-precision ADC has strict requirements for speed and precision.

A slicer of a decision feedback equalizer (DFE) comprises an integrator circuit, a regenerator circuit coupled to the integrator circuit, and a temperature offset cancelation circuit coupled to the regenerator circuit. The integrator circuit comprises a first transistor associated with a first temperature-dependent beta value. The temperature offset cancelation circuit comprises a second transistor associated with a second temperature dependent beta value, a pair of first and second resistors, and a third transistor coupled to the pair of first and second resistors. The first resistor is coupled to the second transistor. The pair of first and second resistors is to modify the second temperature-dependent beta value to correspond to the first temperature-dependent beta value of the first transistor. The third transistor is to provide a bias current for biasing the first transistor.

The invention discloses a current multiplexing feedback type direct current offset elimination circuit and method, and belongs to the field of direct current offset elimination. The feedback type direct current offset cancellation circuit comprises a fully differential amplifier and a DCOC feedback circuit, the fully differential amplifier is used as an input stage of the three-stage amplifier, is mainly used for amplifying a feedforward signal, and consists of R2, R3, M1, M2 and M3; and the R1, the C1, the M5 and the M6 form a DCOC feedback circuit. According to the direct-current offset elimination circuit, the problem that the direct-current offset of the circuit is too large is solved through fewer components; the feedback circuit and the feed-forward circuit share one path of current, so that extra power consumption cannot be introduced into the direct-current offset elimination circuit. According to the invention, feedback type DC offset elimination of current multiplexing can be realized, the problem of overlarge DC offset of the circuit caused by mismatching of CMOS process devices, temperature drift, process deviation and the like can be solved, and the problems of complex design, extra area introduction and power consumption of a traditional DC negative feedback type DCOC can also be solved.

This application is directed to a data interface having an input interface for receiving a differential input signal and a reference interface for providing a predefined reference voltage. A high pass filter is coupled to the input interface, and configured to filter the differential input signal and generate a filtered differential input signal. A differential integrator is coupled to the high pass filter and reference interface, and configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal. Each of the first and second output signals has a common mode output voltage substantially equal to the predefined reference voltage. In some embodiments, the data interface includes a connector including a plurality of data lanes and a pair of command pins that are distinct from the data lanes and coupled to the input interface.

The application discloses a CTLE (Continuous Time Linear Equalizer) based on a single amplifier and having a DC offset and common-mode voltage modulation function, and mainly solves the technical problem that the DC working point of the existing CTLE is easily affected by process deviation, input signal common-mode voltage and current mismatch, and an additional DC offset elimination loop is needed, thereby increasing the design and area complexity. The CTLE comprises a first-stage equalization unit EQ1, a second-stage equalization unit EQ2, a low-pass filter LPF, a frequency compensation unit and an offset and common-mode multiplexing amplifier OCMA. The CTLE adopts a single offset and common-mode multiplexing amplifier OCMA, simultaneously completes DC offset elimination and DC output control, and can reduce the design and area complexity.

The invention relates to the field of wireless sensing, in particular to a baseband amplifier for temperature compensation and direct current offset elimination, an elimination circuit and a chip. The baseband amplifier comprises a full inverter type amplifier, a power supply circuit and a plurality of direct current offset cancellation circuits. Wherein the power supply circuit comprises an LDO circuit, a gain temperature compensation circuit and a resistance potential-divider network; the gain temperature compensation circuit is used for providing a temperature reference voltage capable of compensating the gain temperature degradation characteristic of the amplifier and a reference current with zero temperature excursion for the LDO; and the output of the LDO is subjected to voltage division by the resistance voltage division network and then is used as a reference voltage VCM. The direct current offset elimination circuit is connected to the two ends of each trans-impedance amplifier and generates regulation and control current capable of offsetting unbalanced direct current injected by the preceding-stage frequency mixer in real time according to the VCM. According to the full-inverter amplifier, the problems of gain instability, multi-source imbalance and difficulty in balancing circuit overhead and precision of the existing full-inverter amplifier are solved.

A display driver circuit for controlling a display panel includes a first operational amplifier, a second operational amplifier and a first output switching circuit. The first output switching circuit is coupled to the first operational amplifier and the second operational amplifier. The first output switching circuit couples the first operational amplifier to a first data line of the display panel in a first scan period, to control the first operational amplifier to drive a first subpixel having a first color through the first data line. The first output switching circuit couples the first operational amplifier to a second data line of the display panel in a second scan period, to control the first operational amplifier to drive a second subpixel having the first color through the second data line.

The invention relates to a broadband amplitude detector circuit of a CMOS process, and the circuit comprises a logarithmic amplifier circuit which is used for carrying out the multi-stage amplitude limiting amplification of an original radio frequency signal; the DC offset offset module comprises a DC compensation module and an offset offset circuit, and the DC compensation module is used for filtering an input signal in the amplified radio frequency signal and retaining the amplified offset voltage; the offset counteracting circuit is used for carrying out subtraction operation on the amplified offset voltage and an input signal in the original radio frequency signal; and the peak detection circuit is used for extracting the amplitude of the signal after the subtraction operation. Compared with the prior art, the broadband amplitude detector has the advantages that the problem that bandwidth, sensitivity and temperature stability in a traditional amplitude detector are mutually restricted is solved, detection performance with wider working frequency band, higher temperature stability and better dynamic range is achieved on the standard CMOS technology, meanwhile, the structure is simple, power consumption is low, and integration convenience and application prospects in a monolithic system are greatly improved.

A DC offset cancellation circuit and method are disclosed, comprising an offset cancellation module, an amplifier group, and an inverter structure. Several inverter structures are connected between two amplifier groups, with one end of each amplifier group connected to the signal input and the other end connected to the signal output. An offset cancellation module is provided between the input and output terminals of each amplifier group. This invention differs from existing offset cancellation circuit structures, as it can correct both common-mode voltage and differential-mode offset, improving the reliability of the circuit operation. The use of single-ended bias stabilizes the output DC point at the optimal bias point, ensuring optimal linearity for the inverter-structured amplifier and thus meeting the overall circuit linearity requirements. The Class AB output stage significantly reduces static power consumption, avoids wasted current in the transconductor, and has a much stronger driving capability than a standalone transconductor.

A sense amplifier which includes a sense amplifier circuit that includes a first NMOS transistor and a second NMOS transistor, the first NMOS transistor being connected to a first bit line and the second NMOS transistor being connected to a second bit line complementary to the first bit line, a first isolation / offset cancellation circuit that includes a first isolation switch connecting the first bit line and a first sensing bit line and a first offset cancellation switch connecting the first bit line and a second sensing bit line complementary to the first sensing bit line, and a second isolation / offset cancellation circuit that includes a second isolation switch connecting the second bit line and the second sensing bit line and a second offset cancellation switch connecting the second bit line and the first sensing bit line.

A semiconductor memory device is provided and includes at least one sense amplifier and a control unit. The at least one sense amplifier includes a pair of first transistors and a pair of second transistors. The control unit provides voltages that are adjusted based on characteristics of the pair of first transistors and the pair of second transistors of each sense amplifier of the at least one sense amplifier to the pair of first transistors and the pair of the second transistors of each sense amplifier of the at least one sense amplifier so that voltages of a pair of bit lines connected to each sense amplifier of the at least one sense amplifier are close to a specific target voltage during an offset elimination operation.

The application discloses a linear laser radar-based analog front-end receiving device, which comprises a transimpedance amplifier with an input end of a current signal, an output end of the transimpedance amplifier being connected to an input end of a single-ended-to-differential circuit; an output end of the single-ended-to-differential circuit being connected to an input end of an equalizer in sequence after passing through a first DC offset canceller, a post-amplifier and a second DC offset canceller; and an output end of the equalizer being connected to an input end of an output buffer, wherein the equalizer is a two-stage source-degeneration-type equalizer and is configured as a differential pair structure of source-degeneration parallel resistance and capacitance, the transimpedance amplifier is configured as a resistance parallel type structure, and the transimpedance amplifier comprises a common-source feed-forward resistance, a local negative feedback resistance RF1 and a resistance RF2. According to the front-end receiving device, the detection capability of a laser radar for a long-distance weak signal can be improved, gain switching can be supported to adapt to different ranging scenes, the front-end receiving device has the advantages of high bandwidth, low noise, large ranging range, short recovery time and high reliability.

This invention relates to the field of quantum communication technology and discloses an anti-interference quantum key distribution protocol optimization method, comprising: acquiring the single-photon counter count statistics output by the measurement end during the key screening stage, including signal state, decoy state, and vacuum state count values; calculating the instantaneous variance of the vacuum state count value and determining a counting correction parameter based on the ratio of the variance to the signal state count value; using the parameter to correct the gain deviation of the single-photon counter count statistics; extracting the polarization deviation feature vector from the corrected statistics and determining the bit offset parameter; and performing bit-level logic remapping on the key screening sequence based on the bit offset parameter to compensate for channel disturbances when the polarization control voltage at the measurement end is constant. This invention converts the basis vector deflection into an address offset through protocol layer logic mapping, eliminates the occupation of the link by hardware calibration, ensures the continuity of key generation under environmental disturbances, avoids background noise introduced by strong light pilots, and improves quantum key distribution efficiency.

This invention provides a linear transimpedance amplifier with multi-inductor peaking and a wide gain range, belonging to the field of high-speed optical communication analog front-end integrated circuits. It includes: an inductor peaking module, a gain amplification module, a linear amplification module, a drive module, a gain control module, a first DC offset cancellation module, and a second DC offset cancellation module. The input terminal of the inductor peaking module is connected to the anode of a photodiode. The inductor peaking module, gain amplification module, linear amplification module, and drive module are connected in series. The first terminal of the gain control module is connected to the control terminal of the gain amplification module, and the first terminal of the gain control module is connected to the output terminal of the linear amplification module. The first terminal of the first DC offset cancellation module is connected to the first node in the inductor peaking module, and the second terminal of the first DC offset cancellation module is connected to the output terminal of the inductor peaking module. The second DC offset cancellation module is connected in parallel with the linear amplification module.

This invention discloses a self-alignment control circuit for an offset cancellation calibration circuit of an input buffer. By generating multiple timing control signals based on a start signal through a delay chain and outputting them to the offset cancellation calibration circuit, self-alignment of the timing control signals can be achieved without using a clock to synchronize the signals. This saves the area of ​​the clock circuit and avoids increased power consumption due to clock switching. Furthermore, self-alignment ensures that there are no timing margin issues.