97 results about "Offset cancellation" patented technology

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sensitive amplifier, a reading circuit and a module based on capacitance and flip point compensation. The invention discloses a sensitive amplifier based on capacitors and flip point compensation. The sensitive amplifier comprises nine NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M9, two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2 and two capacitors C1-C2. According to the invention, the CSCSA is designed, and corresponding control logic is matched, so that a pre-charging stage, an offset elimination stage, a charge sharing stage, a pre-sensing stage and an induction amplification stage are designed when the DRAM storage unit is read, the potential of a bit line BL or BLB can be correctly changed, and the reading amplification function of the CSCSA is ensured. Compared with the traditional DRAM sensitive amplifier, the CSCSA provided by the invention has the advantages that the offset voltage index is greatly reduced and the sensing yield is improved under the condition that the quantity of elements is not greatly increased.

The present application relates to the field of semiconductor circuit design, and relates to a sense amplifier circuit and a data readout method, comprising: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; a first control MOS transistor for providing a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor for providing a bias voltage to the second PMOS transistor according to a control signal; a first offset cancellation MOS transistor for electrically connecting an initial bit line to a first complementary readout bit line according to the offset cancellation signal; and a second offset cancellation MOS transistor for electrically connecting the initial complementary bit line to the first readout bit line according to the offset cancellation signal. Stable gate voltages are provided to the first and second PMOS transistors respectively via the first and second control MOS transistors, thereby stably eliminating offset noise in the sense amplifier circuit and avoiding voltage fluctuations on the bit lines and complementary bit lines.

The invention discloses an offset cancellation circuit, which comprises a signal conditioning unit used for processing an input signal and outputting a first current signal, an offset cancellation unit used for removing offset current in the first current signal and outputting a second current signal, and a signal processing unit used for processing the second current signal and eliminating offset voltage, the detuning elimination unit specifically comprises a chopper, a digital analog converter, a successive approximation register logic module and a comparator which are connected in sequence, and through multi-level detuning elimination, the precision of the whole circuit is improved, the processing capacity for weak signals is enhanced, the anti-interference capacity is improved, and noise is reduced; the method ensures the stability of long-time operation, and has a wide application prospect in the field of high-precision signal processing.

The invention relates to the technical field of DRAM (Dynamic Random Access Memory) circuit design, in particular to a sense amplifier based on flip point and current mirror compensation, a reading circuit and a chip. The invention designs a sensitive amplifier based on flip point and current mirror compensation. The sensitive amplifier comprises 11 NMOS (N-channel Metal Oxide Semiconductor) tubes M1-M11 and two PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P2. Corresponding control logic is provided in cooperation with the provided sensitive amplifier, so that a pre-charging stage, an offset elimination stage, an offset compensation stage, a charge sharing and reference voltage amplification stage and an induction amplification stage are designed when the sensitive amplifier reads the DRAM storage unit. The sensitive amplifier provided by the invention has the advantages that the number of elements is small, the circuit area is not greatly increased, the high sensing yield is ensured, the offset voltage index is greatly reduced, and the reading speed is increased.

In a microelectromechanical system (MEMS) sensor, movement of a component such as a proof mass due to a force of interest is sensed capacitively. A capacitance-to-voltage (C2V) converter receives a capacitance signal from the sensor and outputs a signal that includes an offset in addition to a signal of interest. The output signal is analyzed to identify the offset portion of the output signal and to modify values one or more variable capacitors coupled to the C2V input reduce the offset portion of the output signal.

The invention provides a control method of a sensitive amplifier and a memory. The sensitive amplifier comprises a pre-charging stage, an offset elimination stage, a charge sharing stage and a sensing amplification stage. In the offset elimination stage, the first power end is controlled to be connected with power voltage, the second power end is controlled to be connected with grounding voltage, and the sensitive amplifier is controlled to form compensation voltage on the bit line and the complementary bit line; wherein the duration of the offset elimination stage is the optimal offset elimination duration, and the sensing margin of the sensitive amplifier is the maximum value under the optimal offset elimination duration. In the sensing amplification stage, the first power end is controlled to be connected with the power voltage, the second power end is controlled to be connected with the grounding voltage, the time when the first power end is connected with the power voltage is later than the time when the second power end is connected with the grounding voltage, and the sensitive amplifier is controlled to amplify the voltage difference on the bit line and the complementary bit line.

In a microelectromechanical system (MEMS) sensor, movement of a component such as a proof mass due to a force of interest is sensed capacitively. A capacitance-to-voltage (C2V) converter receives a capacitance signal from the sensor and outputs a signal that includes an offset in addition to a signal of interest. The output signal is analyzed to identify the offset portion of the output signal and to modify values one or more variable capacitors coupled to the C2V input reduce the offset portion of the output signal.

The present disclosure provides a control method of a sense amplifier and a memory. The sense amplifier includes a pre-charge phase, an offset cancellation phase, a charge sharing phase and a sense amplification phase. In the offset cancellation phase, a first power terminal is controlled to be connected to a power voltage, a second power terminal is controlled to be connected to a ground voltage, and the sense amplifier is controlled to form a compensation voltage on a bit line and a complementary bit line; a duration of the offset cancellation phase is an optimal offset cancellation duration, and a sensing margin of the sense amplifier is a maximum value at the optimal offset cancellation duration. In the sense amplification phase, the first power terminal is controlled to be connected to the power voltage, the second power terminal is controlled to be connected to the ground voltage, and a time when the first power terminal is connected to the power voltage is later than a time when the second power terminal is connected to the ground voltage, and the sense amplifier is controlled to amplify a voltage difference on the bit line and the complementary bit line.

The invention discloses a low-kick-back low-detuning dynamic comparator with cross coupling pair transistors and an operation method, and belongs to the technical field of analog integrated circuits. The comparator comprises a pre-amplification stage and a regeneration stage, the pre-amplification stage is composed of a reset module I, an offset elimination module, a cross coupling module and a pre-amplification module, and the regeneration stage is composed of a reset module II, an enabling module and a latch comparison module. According to the operation method, a complete period is divided into four stages of resetting, offset elimination, sampling and comparison, wherein key nodes are initialized in the resetting stage; in the offset elimination stage, offset voltage of the input geminate transistors is stored through a capacitor. In the sampling stage, an input signal is coupled with a stored offset voltage, and introduction of additional offset is avoided; in the comparison stage, a cross coupling module is used for regulating and controlling the discharge rate, kickback noise is restrained, the comparison precision is improved, and finally signal latching is completed through a regenerative-stage positive feedback mechanism.

The invention relates to offset cancellation. A memory device may determine that a channel is in a state that interrupts active termination of the channel and enable calibration of a reference voltage (e.g., by the memory device). For example, a channel for data transfer for a second device (e.g., a controller) may initially be in an actively terminated state. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting a calibration signal on the channel and detecting an offset associated with the reference voltage. The memory device may identify a signal transmitted to the memory device on the channel using the detected offset and the reference voltage.

The present invention discloses a two-dimensional AMR sensor switch chip signal architecture and detection method. In the signal circuit architecture, the clock signal output terminal of the fast clock circuit is connected to the clock signal input terminal of the first combinational logic operation module and the clock signal input terminal of the second combinational logic operation module, and the clock signal output terminal of the slow clock circuit is connected to the clock signal input terminal of the first combinational logic operation module; the first combinational logic operation module outputs an X-direction sampling signal, a Y-direction sampling signal, and a detection enable signal, and the second combinational logic operation module outputs a comparator enable signal, a chopping signal, and an XY-direction switching signal. Chopping offset cancellation technology is used to improve detection accuracy, and time-division multiplexing technology is used to share a processing signal chain, achieving low-power two-dimensional signal acquisition and detection in the X and Y directions, and flexible switching of directions according to actual needs.

The invention provides a frequency deviation estimation method and device, electronic equipment and a storage medium, and relates to the technical field of communication. Wherein the frequency modulation signal comprises a frequency linear increase signal and a frequency linear decrease signal; demodulating with the frequency linear increase signal and the frequency linear decrease signal based on the received signal to obtain a target increase signal and a target decrease signal; determining a target receiving signal according to the target increasing signal and the target decreasing signal; the target received signal is a signal obtained after offset elimination is carried out on the received signal; and performing offset estimation according to the target received signal and the pilot signal to obtain a target frequency offset result. According to the technical scheme, on the basis of combination of the frequency modulation signal and the pilot signal, offset elimination is carried out on the receiving signal through the frequency modulation signal to obtain the target receiving signal, accurate offset estimation is carried out on the target receiving signal through the pilot signal to obtain the target frequency offset result, and the accuracy of offset estimation is improved.

A method for obtaining neural signals from a neural signal sensor includes extracting sensor offset from a neural input signal. Sensor offset is removed from N-channels that share a single amplifier. The neural input signal is acquired from the analog domain by neural electrodes with varying DC-offset and the method includes multiplexing the N-channels via a time divisional multiple access procedure into a single neural amplifier An integrated digitally assisted neural recording system includes an analog multiplexer structured to receive N-channels and to multiplex the N-Channels into a single neural amplifier. A feedback loop is configured to cancel electrode offset voltage in the digital domain by generating electrode offset voltage samples and adding delay to align each electrode offset voltage sample to be subtracted at the neural amplifier in the analog domain.

A method for obtaining neural signals from a neural signal sensor includes extracting sensor offset from a neural input signal. Sensor offset is removed from N-channels that share a single amplifier. The neural input signal is acquired from the analog domain by neural electrodes with varying DC-offset and the method includes multiplexing the N-channels via a time divisional multiple access procedure into a single neural amplifier An integrated digitally assisted neural recording system includes an analog multiplexer structured to receive N-channels and to multiplex the N-Channels into a single neural amplifier. A feedback loop is configured to cancel electrode offset voltage in the digital domain by generating electrode offset voltage samples and adding delay to align each electrode offset voltage sample to be subtracted at the neural amplifier in the analog domain.

A sense amplifier includes a first isolation transistor connected to a first memory cell through a first bit line, a second isolation transistor connected to a second memory cell through a second bit line, and sense amplifying circuitry connected to the first memory cell through the first isolation transistor, connected to the second memory cell through the second isolation transistor, and latch, to a pair of sense bit lines, data corresponding to a cell voltage stored in the first memory cell or the second memory cell, wherein the sense amplifying circuitry is configured to perform an offset cancellation operation while a charge sharing operation is performed between the first memory cell and the first bit line or between the second memory cell and the second bit line.

The invention provides a high-precision band-gap reference circuit with an offset elimination function. The high-precision band-gap reference circuit comprises a band-gap reference amplifier A1; the band-gap reference amplifier A1 comprises a square wave generator circuit, a clock circuit and an offset elimination circuit; the square wave generator circuit, the clock circuit and the offset cancellation circuit are connected in sequence; the square wave generator circuit generates a clock signal and transmits the clock signal to the clock circuit; the clock circuit comprises a first NOR gate and a second NOR gate, and capacitors are additionally arranged at the output ends of the first NOR gate and the second NOR gate respectively; and a capacitor is additionally arranged in a feedback path of the offset elimination circuit and is used for storing the offset quantity. When a square wave generator and a two-phase non-overlapping clock control single-end input in the circuit are zero, offset is measured, and the offset amount is stored on a capacitor at an output end, so that the influence of input offset is counteracted at the output end.

A comparator circuit for detecting an amount of variation in an input signal (Vlog) is provided, comprising a comparator having a non-inverting input (Vref_pos, Vref_neg) and an inverting input (Vcp, Vcn); a capacitor (Cp, Cn) connected between the inverting input and a terminal for applying the input signal as a voltage (Vlog); a reset switch (SWrp, SWrn) connected between the inverting input and an output (EPOS, ENEG) of the comparator; and a calibration switch (SWcp, SWcn) connected to select for the non-inverting input a voltage among a threshold voltage (Vth_pos, Vth_neg) and a calibration voltage (Vcal_pos, Vcal_neg).

To provide an offset cancel amplifier, a display driver, and a display device capable of generating a highly accurate output voltage corresponding to an input voltage.SOLUTION: An offset cancellation amplifier according to the present invention includes: a first differential pair that receives an input voltage at one end, receives an input voltage or an output voltage at the other end, and outputs a first current pair corresponding to a difference between voltages at both ends; first and second capacitive elements; a switch circuit that supplies a reference voltage or the input voltage to one end of the first capacitive element and supplies the output voltage to one end of the second capacitive element in an on state; a second differential pair having one end of the first capacitive element connected to one end thereof and one end of the second capacitive element connected to the other end thereof and outputting a second current pair corresponding to the difference between voltages at both ends thereof; an output amplification stage for generating the output voltage by sending a current corresponding to a magnitude of a current obtained by current-coupling the first and second current pairs to an output node; and a third capacitive element having one end and the other end thereof connected to one end of each of the first and second capacitive elements.SELECTED DRAWING: Figure 2

To provide a semiconductor storage device capable of improving a sense margin of a sense amplifier, even if an offset cancellation operation sequence is executed for each of a plurality of sense amplifiers of a plurality of pages, and a control method thereof.SOLUTION: A semiconductor storage device includes a control unit that executes an offset cancellation operation sequence including at least one predetermined operation of supplying a power supply voltage common to all pages to the sense amplifier, for each sense amplifier on each page. The control unit is configured to control timing of executing the offset cancellation operation sequence in each page without executing the predetermined operation on the other page other than any other page, while executing the predetermined operation on any other page of the plurality of pages, when executing the offset cancellation operation sequence on each page of the plurality of pages.SELECTED DRAWING: Figure 6

This disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an interlayer insulating film disposed on a substrate and having a recessed portion of the substrate exposed; a bottom electrode contact embedded in at least a portion of the recessed portion; a magnetic tunnel junction (MTJ) layer disposed on the interlayer insulating film and the bottom electrode contact; and a offset cancellation layer with a magnetization direction parallel to the antiparallel side of a fixed layer, wherein the offset cancellation layer may include a Co alloy, Fe alloy, Ni alloy, or Mn alloy comprising at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals, or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy comprising one selected from the group consisting of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B.

A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.

The invention provides a semiconductor memory device and a control method thereof, which can improve sensing margins of sense amplifiers even when a plurality of sense amplifiers for each of a plurality of pages execute an offset cancellation operation sequence. The semiconductor memory device includes a control section configured to execute an offset cancellation operation sequence including at least a specified operation for supplying a power supply voltage common to each page to the sense amplifiers for each of the page. The control unit is configured so as to control, when the offset cancellation operation sequence is executed in each of the plurality of pages, a point in time at which the offset cancellation operation sequence is executed in each of the plurality of pages in a control manner in which a specified operation is not performed on other pages other than any one of the plurality of pages during a period in which the specified operation is performed on the any one of the plurality of pages.

The present disclosure relates to the field of semiconductor circuit design, and particularly relates to an amplification circuit, a control method and a memory, comprising: a sensing amplification circuit comprising a readout node, a complementary readout node, a first node and a second node; an isolation circuit is configured to, in a sensing amplification phase, couple the readout node to a bit line and couple the complementary readout node to a complementary bit line; an offset cancellation circuit is configured to, in an offset cancellation phase, couple the bit line to the complementary readout node and couple the complementary bit line to the readout node; a first power supply circuit is coupled to the first node and comprises a first power supply and a second power supply, the power supply voltage of the first power supply being higher than that of the second power supply; the first power supply circuit is configured to, in the offset cancellation phase, couple the first power supply to the first node, and in the sensing amplification phase, couple the second power supply to the first node, so as to shorten the processing time of the offset cancellation phase, thereby optimizing the performance of the memory.

Semiconductor devices for synchronizing networks are described. The semiconductor device includes a timing circuit having a sub-sampling phase lock loop. The sub-sampling phase lock loop includes a radio frequency sampler circuit that is configured to generate at least one error signal corresponding to a phase difference between an output signal of a voltage-controlled oscillator and a reference signal and a transconductor circuit that is configured to generate a tuning signal based on the at least one error signal. The tuning signal is configured to tune the voltage-controlled oscillator. The sub-sampling phase lock loop further includes an adaptive bias circuit that is configured to generate a nulling signal based on an offset in the tuning signal created by the transconductor circuit and provide the nulling signal to the transconductor circuit. The transconductor circuit is configured to adjust the tuning signal based on the nulling signal.

The invention relates to a comparator, an analog-to-digital converter and an offset elimination method thereof. The comparator includes a comparator circuit, an offset calculation circuit, a hybrid offset voltage generation circuit, and an offset cancellation circuit. The comparator circuit is used for generating a decision signal according to an input signal. An offset calculation circuit is configured to calculate an offset of the comparator circuit according to the decision signal to generate a plurality of control signals. The hybrid offset voltage generation circuit is configured to select a first reference voltage and a second reference voltage from a plurality of reference voltages according to the plurality of control signals, and perform a charge transfer operation using the first reference voltage and the second reference voltage to generate a plurality of correction voltages. The offset cancellation circuit is configured to cancel the offset according to the plurality of correction voltages.

The invention discloses a single amplifier-based CTLE with direct current offset and common mode voltage modulation functions, and mainly solves the technical problems that the direct current working point of the existing CTLE is easily influenced by process deviation, input signal common mode voltage and current mismatch, an additional direct current offset elimination loop is needed, and the design and area complexity is increased. The CTLE comprises a first-stage equalization unit EQ1, a second-stage equalization unit EQ2, a low-pass filter LPF, a frequency compensation unit and an offset and common-mode multiplexing amplifier OCMA. The CTLE adopts a single offset and common-mode multiplexing amplifier OCMA to complete direct current offset elimination and direct current output control at the same time, so that the design and area complexity can be reduced.

This estimation device comprises: an input unit that inputs channel state information (CSI) acquired by using a plurality of reception antennas and a plurality of transmission antennas; a first offset removal unit that divides the CSI among the reception antennas and that generates a first signal; a second offset removal unit that divides the CSI among the transmission antennas and that generates a second signal; a first phase difference correction unit that corrects the phase of a dynamic component extracted from the first signal by using a static component extracted from the second signal and that generates a third signal; a second phase difference correction unit that corrects the phase of a dynamic component extracted from the second signal by using a static component extracted from the first signal and that generates a fourth signal; an AoD estimation unit that estimates the AoD, which is the transmission direction of the radio wave, by using the third signal; and an AoA estimation unit that estimates the AoA, which is the arrival direction of the radio wave, by using the fourth signal.

Implementations of a resolver sensor system may include a signal amplifier portion configured to be coupled to a magnetoresistive sensor coupled with a movable element where the signal amplifier portion configured to receive a sine signal and a cosine signal from the magnetoresistive sensor; and a sensor offset canceling portion coupled with a signal amplifier portion. The sensor offset canceling portion may be configured to generate a direct current offset correction signal to the signal amplifier portion which uses two or more amplifiers included in the signal amplifier portion to receive the sine signal and the cosine signal and to generate corresponding adjusted digital sine and cosine signals. The signal amplifier portion may be configured to provide the adjusted digital sine signal and the adjusted digital cosine signal to one of the servo signal processor or the system controller for use in determining a position of the movable element.

The present disclosure relates to a sense amplifier, a memory device including the sense amplifier, and an electronic device including the memory device. The sense amplifier includes: a first isolation unit; a second isolation unit; a first offset cancellation unit; a second offset cancellation unit; and a sense amplifier unit including a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. The sense amplifier further includes at least one of a first equalization unit and a second equalization unit, wherein the first equalization unit is configured to selectively apply a precharge voltage to a bit line, and the second equalization unit is configured to selectively apply a precharge voltage to a complementary bit line. This improves the equalization performance of the bit lines during a precharge operation, thereby increasing the sensing efficiency of the sense amplifier.

The embodiment of the present application relates to the field of semiconductor circuit design, and particularly relates to a readout circuit and a data readout method, which comprises: a first isolation unit is configured to connect a bit line to a readout bit line based on an isolation signal; a second isolation unit is configured to connect a complementary bit line to a complementary readout bit line based on the isolation signal; a first PMOS tube is connected between a first signal end and the readout bit line, and has a control terminal connected to the complementary readout bit line; a second PMOS tube is connected between the first signal end and the complementary readout bit line, and has a control terminal connected to the readout bit line; a first NMOS tube is connected between a second signal end and the bit line, and has a control terminal connected to the complementary readout bit line; and a second NMOS tube is connected between the second signal end and the complementary bit line, and has a control terminal connected to the readout bit line, so that the offset noise in the readout circuit is eliminated without introducing more offset cancellation MOS tubes, and the DRAM integration is improved.