14 results about "Duty cycle corrector" patented technology

A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

A duty cycle corrector (DCC) includes a first duty cycle correction circuit, a second duty cycle correction circuit, and overshoot prevention circuit connected between the first duty cycle correction circuit and the second duty cycle correction circuit. Each of the duty cycle correction circuits include a capacitor, two inverters, a resister, and two switches.

This application relates to duty cycle corrector circuits and related devices and methods. One device includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to provide an integrator signal that substantially indicates the integration of a corrected clock signal. The amplifier circuit is configured to deactivate in response to detecting that an input clock signal has been deactivated. The amplifier circuit includes a first amplifier input terminal and a second amplifier input terminal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal in response to detecting that the input clock signal has been deactivated. A method for correcting the duty cycle of an input clock signal includes adjusting the corrected duty cycle of the corrected clock signal in response to a first error signal and a second error signal from the amplifier circuit.

Proposed are an LSK demodulator that can implement accurate recovery of a received signal, noise removal, clock synchronization by operating two signal processing means, each of which includes an integrator and a comparator, with a phase difference and a wireless power transmission / sensor information processing device including the LSK demodulator. The LSK demodulator includes an integrating receiver, a quadrature phase clock generator, a finite state machine, a phase interpolator, a duty cycle corrector, and a control circuit.

A duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. A duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. The DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).

A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.

A charge pump includes a first transistor, a first switch coupled between the first transistor and an output of the charge pump, a second transistor, and a second switch coupled between the output of the charge pump and the second transistor. The charge pump also includes a third transistor, wherein a gate of the third transistor is coupled to a gate of the first transistor, a fourth transistor, wherein a drain of the fourth transistor is coupled to a drain of the third transistor, and a bias circuit configured to bias a gate of the fourth transistor and a gate of the second transistor. The charge pump also includes an amplifier having a first input coupled to the output of the charge pump, a second input coupled to the drain of the third transistor, and the output coupled to the gate of the third transistor.

A device includes a receiving circuit, a processing circuit, and a transmitting circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each of which receives a data input signal and generates a first data output signal. Each receiver includes a delay line that is devoid of a duty cycle corrector (DCC), that has a predetermined number of delay elements, and that introduces a propagation delay to the data input signal by a fixed amount that substantially matches a propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. The transmitting circuit transmits the second data output signal to a data signal-receiving device.

A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.

A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

An apparatus for synchronizing a data input signal and a clock input signal is provided. The device comprises a receiving circuit, a processing circuit and a transmission circuit. The receiving circuit generates a clock input signal and includes a plurality of receivers, each receiving a data input signal and generating a first data output signal. Each receiver includes a delay line that does not include a duty cycle corrector (DCC), has a predetermined number of delay elements, and introduces a propagation delay to the data input signal by a fixed amount that substantially matches the propagation delay of the clock input signal. The processing circuit processes the first data output signal and generates a second data output signal. And the transmission circuit sends the second data output signal to a data signal receiving device.

A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).