A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.