Integrated circuit devices having improved duty cycle correction and methods of operating the same

Abstract

Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and / or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

Description

[0001] This application relates to and claims priority from Korean Patent Application No. 2003-19653 filed on March 28, 2003, the entire contents of which are incorporated by reference if necessary. technical field [0002] The present invention relates to an integrated circuit device and its operating method, more specifically, to an integrated circuit device with a duty cycle correction circuit and its operating method. Background technique [0003] Recently, the speed of integrated circuit memory devices, such as dynamic random access memories (DRAMs), has been increased to improve the performance of existing systems. However, growing demands for improved systems may require DRAM to be able to handle even more data at higher speeds. Accordingly, a synchronous dynamic random access memory (SDRAM) operating in synchronization with a system clock has been developed for high-speed operation, thereby significantly increasing the data transfer speed. [0004] There is a limit ...

AI Technical Summary

Problems solved by technology

A digital duty cycle correction circuit 600 that includes a DLL circuit may be smaller than a digital duty cycle correction circuit that includes an analog duty cycle correction circuit, but typically includes a DLL circuit because it uses the delay line of the DLL circuit

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