255 results about "Comparators circuits" patented technology

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

In disclosed embodiments, a voltage sensor of a computing device is configured to determine a voltage level of a supply voltage provided by a power supply to processor circuitry. Comparator circuitry may perform a comparison operation that compares the determined voltage level to a threshold. A temperature sensor may determine a temperature of at least a portion of processor circuitry. Power control circuitry may initiate a power management operation to adjust voltage margin based on a result of the comparison operation. Additionally, the power management circuitry may control the comparator circuitry to impose an offset on the comparison operation. The power control circuitry may determine a magnitude of the offset based on a pre-determined effect of the determined temperature on voltage margin parameters for at least a portion of the processor circuitry.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention provides a wide dynamic range methane detection system based on synchronous accumulation and system reconstruction. The device is characterized by comprising a modulated laser (1), a gas absorption cell (2), a photoelectric detector (APD) (3), a variable gain trans-impedance amplifier (TIA) (4) based on a digital potentiometer, a dual-threshold voltage comparator circuit (5) and a microcontroller processing unit (6). The device can be used for large-dynamic-range real-time monitoring of the methane gas concentration, and the problem that a traditional TDLAS system is prone to saturation or limited in detection limit when the concentration span is large is effectively solved. The method can be widely applied to the fields of gas concentration detection, industrial safety control and the like.

A continuity detector for determining the continuity of a Unit Under Test (UUT). The detector comprises a housing defining an interior volume, an electronics package disposed within the interior volume defined by the housing assembly, a first test contact and a second test contact to interface with the electrical wire or harness assembly, a precision resistance standard disposed within the housing and electrically coupled to the electronics package, and a power source disposed within the housing assembly. The first test contact and the second test contact are external to the interior volume. The first test contact and the second test contact are electrically coupled to the electronics package. The electronics package comprising a resistance measurement device and a comparator circuit. The comparator circuit is configured to determine if the resistance of the UUT is greater than, less than, or equal to the resistance of the resistance standard.

A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. The circuit includes a first-stage positive feedback module, a second-stage triggering and clocking module, a second-stage positive feedback amplification module, and a third-stage positive feedback latching module. By employing a three-stage positive feedback structure, this invention places the corresponding differential signal nodes in the same feedback loop at each stage, significantly enhancing the comparator's amplification rate and metastability suppression capability. Furthermore, by introducing a fast timing control mechanism, the second-stage amplification, clock reset generation, and third-stage latching operations can be executed in parallel, effectively shortening the critical path delay and significantly improving the overall comparison speed. The electronic device includes the aforementioned comparator circuit. This invention effectively solves the bottlenecks of traditional comparators in terms of speed and reliability and is suitable for high-speed, high-precision data conversion systems.

The invention discloses a motor forward and reverse rotation driving circuit and system, and the circuit comprises a reference voltage supply circuit which is provided with a reference voltage output end; the first reference voltage providing circuit is provided with a first reference voltage output end; the reference voltage output end and the first reference voltage output end are respectively connected with the first comparator circuit; wherein the reference voltage is gradually changed from the first reference voltage to the second reference voltage, the first reference voltage is located between the first reference voltage and the second reference voltage, so that the reference voltage is smaller than the first reference voltage in a first time period and larger than the first reference voltage in a second time period, and the first time period and the second time period are not overlapped; and the first comparator circuit is connected with the motor driving circuit. When the motor rotates positively and negatively, a single chip microcomputer is not needed, the cost is reduced, software burning is not needed, and the process is simple during mass production.

Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and a number of content-addressable control cells. Each control cell controls a respective display pixel of the pixel active array. Each control cell includes a comparator to generate a control signal to control the respective display pixel of the pixel active array based on a comparison between pixel data for the respective display pixel and one or more counters corresponding to a gray level.

The utility model relates to a PD detection alarm protection circuit of a laser. The PD detection alarm protection circuit comprises a PD sensor, a resistance voltage division circuit, an in-phase proportion amplification circuit, a comparator circuit and a voltage reference circuit, the PD sensor collects a PD photocurrent signal of the laser and then sends the PD photocurrent signal to the resistance voltage division circuit; the resistance voltage division circuit converts the PD photocurrent signal into a PD voltage signal and then sends the PD voltage signal to the in-phase proportion amplification circuit; the in-phase proportional amplification circuit amplifies the PD voltage signal and then transmits the PD voltage signal to one input end of the comparator circuit, the other input end of the comparator circuit is connected with the voltage reference circuit, and the output end of the comparator circuit outputs a processed PD signal; by optimizing a pre-stage amplification framework and a post-stage reference design, the detection reliability is remarkably improved while the cost is reduced, and the detection response speed is very high. And real-time monitoring can be realized through an upper computer. The system is especially suitable for a safety protection system of industrial laser equipment.

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit with a wide common-mode input range. The LVDS receiving circuit comprises a common-mode conversion circuit, a main comparator circuit, a secondary comparison circuit and a logical judgment circuit, the common-mode conversion circuit is used for converting an external wide common-mode input differential signal into a signal with constant common-mode voltage and no attenuation of the differential signal; the main comparator circuit identifies the converted differential signal to complete differential-to-single-ended data conversion; the secondary comparator circuit is composed of two low-speed comparators; and the logic judgment circuit judges the output of the main comparator and the window comparator to ensure that the output of the input end of the circuit group is a constant level under the short circuit and disconnection conditions, so that the function of dynamic failure protection of the circuit is realized. The wide common-mode input circuit can realize discrimination of wide common-mode input signals ranging from-4V to 5V, and has a dynamic failure protection function.

A delta-sigma modulator includes a comparator circuit having an output that provides a digital signal indicative of a voltage of a signal received at an input of the comparator circuit. The modulator includes a continuous-time path from a modular input to an input of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path and providing a first feedback current controlled by the comparator circuit output and a second second feedback loop providing a second feedback current controlled by the comparator circuit output to a second integrating node of the path, the second integrating node connected to the input of the comparator and to a capacitor.

The application provides a reverse voltage protection circuit and a bus transceiver, and the reverse voltage protection circuit comprises a comparator, the input port and the output port of the circuit are connected with the input end of the comparator, the comparator is used for comparing the voltage of the input port and the output port, and outputs a comparison signal; a trigger circuit receives the comparison signal, turns on / off a MOS tube connected between the input port and the output port according to the comparison signal; and the MOS tube is used for preventing abnormal voltage of the output port from flowing back to the input port. By using the above circuit, the trigger circuit can be turned on or turned off by comparing the voltage of the input port and the output port, the MOS tube is controlled in the off state by the trigger circuit, the abnormal voltage is prevented from flowing back to the input port, the function of the high-voltage diode is replaced by the reverse voltage protection circuit, the use of the high-voltage diode is reduced, and the manufacturing difficulty and the manufacturing cost of the chip are reduced.

Memory circuit with a memory array comprising first memory cells and second memory cells, each of the first memory cells being configured to store a data bit, and each subset of the second memory cells being configured to store repair bits, the repair bits indicating a location of a corresponding first memory cell and a random bit; register circuits, the register circuits being configured to transmit or lock the multiple repair bits; a comparator circuit coupled to the register circuits being configured to provide a match signal in response to the finding that an address signal matches the location of the corresponding first memory cell indicated by the repair bits;and a multiplexer coupled to the comparator circuit, configured to output the random bit instead of the data bit stored by the corresponding first memory cell based on the matching signal.

An example apparatus includes: alternating current (AC) source circuitry having an input and an output; comparator circuitry having an input and an output, the output of the comparator circuitry coupled to the input of the AC source circuitry; integrator circuitry having an output of the integrator circuitry coupled to the input of the comparator circuitry; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the output of the AC source circuitry, the second terminal of the capacitor coupled to the integrator circuitry.

This disclosure provides an external constant current circuit based on a DC-DC converter. The external constant current circuit includes a signal conversion operational amplifier circuit, a comparator circuit, a current regulation circuit, and a buffer. Specifically, the signal conversion operational amplifier circuit acquires the output current of the DC-DC converter, converts and amplifies the output current into a first voltage signal. The comparator circuit then compares the first voltage signal with an external reference voltage signal to output a second voltage signal. When the output current exceeds the constant current threshold, the current regulation circuit adjusts the current injected into the voltage feedback pin using the second voltage signal, thereby regulating the output current and maintaining it constant at the constant current threshold. This solves the problem of how to more efficiently implement constant current functionality in chips based on existing DC-DC converters.

This invention relates to a frequency identification circuit for motor driver control, belonging to the field of motor drive control technology. The frequency identification circuit compares frequency signals with corresponding duty cycles of 1% and 99% using two comparators. The first comparator circuit amplifies the output signal of the frequency identification module and inputs it to the non-inverting terminal of the comparator. The second comparator circuit directly inputs the output signal of the frequency identification module to the inverting terminal of the comparator. When the duty cycle is less than 1% or greater than 99%, the corresponding comparator outputs a low level. The signal processing circuit uses the unidirectional conductivity of a diode to perform an OR operation on the two comparison signals. If either signal goes low, the driver enable terminal is pulled low, triggering a protection mode. This invention enables rapid identification and protection against PWM signal anomalies, effectively improving the reliability of protection for motor drivers and electric servos.

The application relates to a high-speed analog comparator circuit with offset correction, which comprises a three-stage signal amplification stage circuit and a voltage offset correction circuit. The three-stage signal amplification stage circuit comprises a first-stage circuit part, a second-stage circuit part and a third-stage circuit part connected in cascade. The first-stage circuit part is used for providing a gain to attenuate noise, offset and kickback of the second-stage circuit part and the third-stage circuit part. The second-stage circuit part is used for exponentially increasing differential output of a signal. The third-stage circuit part adopts a bidirectional latch structure to minimize a regeneration time. The first-stage circuit part is further connected with an auxiliary input branch. The voltage offset correction circuit is used for charging and discharging a capacitor of the auxiliary input branch by detecting an output of the three-stage signal amplification stage circuit in a correction mode, so as to control a common-mode level of the auxiliary input branch and reduce voltage offset. The application can meet the requirement of high-speed high-precision ADC design.

This invention discloses a comparator circuit with a wide common-mode input range. By combining a common-gate differential pair and an auxiliary differential pair, a wide common-mode input range from ground voltage to voltages higher than the power supply voltage is achieved. When the common-mode voltage is low, only the auxiliary differential pair operates; when the common-mode voltage is in the middle range, both differential pairs operate simultaneously to obtain maximum gain; when the common-mode voltage is high, only the common-gate differential pair operates. This design solves the problem of limited common-mode input range in traditional comparators.

A power supply circuit includes an output voltage generation circuit configured to generate an output voltage higher than an input voltage, a threshold voltage generation circuit configured to generate a threshold voltage lower than the input voltage, a comparator circuit configured to assert an output signal when the output voltage rises above the threshold voltage, and a threshold voltage varying circuit configured to decrease the threshold voltage when the input voltage increases above a reference voltage.

A data line and a charging device are provided. The data line includes a Type-A interface, a first interface, a wire, and a circuit identification module. The Type-A interface is correspondingly connected to a VBUS pin, a D+ pin, a D− pin, and a GND pin in the first interface. The circuit identification module includes a pull-up resistor, a switch circuit, a filter circuit, and a comparator circuit. The comparator circuit controls the first end and the second end or the third end of the switch circuit to be connected.

This invention provides a power-on detection circuit and a chip. An enable control circuit is added before the voltage divider circuit. During chip power-on, the enable control circuit outputs an enable control signal to enable the voltage divider circuit only after the power supply voltage reaches a first threshold. This avoids the problem of misjudgment by the comparator circuit due to the voltage divider circuit's voltage division establishment speed being equal to or faster than the reference voltage establishment speed. Thus, during chip power-on, problems such as the chip failing to start normally or irreversible damage caused by the output of the power-on detection circuit being incorrectly flipped can be avoided, thereby improving the chip's power-on safety and operational reliability.

A comparator 300 comprising: a logic circuitry configured to receive two binary inputs A and B, and identify if the binary inputs are same or different, where the logic circuitry comprises a plurality

The application provides an emergency power supply starting circuit, and belongs to the technical field of integrated circuits, and comprises a high-voltage input end for providing a high-voltage input; a voltage storage circuit comprising a first resistor R1 and a first capacitor C1, and an input end connected with the high-voltage input end; a comparator circuit comprising a comparator U1, a positive input end connected with an output end of the voltage storage circuit, a negative input end for providing a low-voltage input, and an output end connected with a control switch group; and the control switch group is connected with a control chip; the comparator U1 in the comparator circuit is reversed according to the voltage storage circuit and the low-voltage input, controls on-off of the control switch group, and supplies power to the control chip for starting, so that the problem that the existing emergency power supply starting circuit has high power consumption for high-voltage power taking and has high requirements on the control chip is solved.

This invention provides a comparator circuit with latching function and its control method. The comparator circuit with latching function uses an initial voltage provided by a pre-comparison module. The initial voltage is dynamically adjusted based on the input comparison voltage to generate a first current variable. This first current variable is converted into a control voltage, and a first comparison result is output based on the control voltage. The first comparison result is compared and positive feedback latched by the latching module to obtain a second comparison result. This comparator circuit with latching function, designed for low-to-medium precision and low-frequency applications, replaces the redundant design and related bias circuits of multi-stage operational amplifier cascades with a pre-comparison module. The common-mode voltage bias is integrated into the structure of the pre-comparison module, simplifying the circuit structure. This comparator circuit does not interfere with the preceding or following circuits, reducing process sensitivity.

A digital hardware circuit and method for performing reduction operations that achieves constant timing depth regardless of input count. The invention replaces conventional sequential binary tree approaches with a parallel matrix comparison architecture where multiple comparator circuits simultaneously compare input signals against each other. Combinatorial logic circuits process comparison outputs to generate dominance signals indicating which input satisfies the reduction criteria, and selection logic outputs the final result. The parallel approach maintains exactly three logic levels regardless of number of processing inputs, enabling significantly higher clock frequencies than conventional methods whose timing depth increases logarithmically with input count. Applications include matrix multiplication engines, floating-point arithmetic units, and artificial intelligence accelerators where reduction operations for maximum / minimum finding, normalization, and other computations are performed millions of times per second. The constant timing depth enables operation at frequencies exceeding 1 GHz while providing scalable performance.

The utility model discloses a kind of under-voltage latching circuits with recovery time, including power supply voltage detection module and recovery time generation module;Power supply voltage detection module is composed of sampling circuit and first comparator circuit, and recovery time generation module is composed of charge pump circuit and second comparator circuit;The under-voltage latching circuit with recovery time further includes band gap reference circuit and logic circuit.The utility model can realize accurate recovery time.Through logic circuit, the voltage of first comparator and second comparator output is calculated, can avoid under-voltage latching during power-on process of power supply to generate false inversion signal.In addition, as the case shown in the preceding figure 3, recovery time generation module can effectively avoid the situation of power fluctuation, and more effectively protect the circuit.Recovery time can be adjusted by increasing charging current control circuit.Low cost, easy to design, easy to copy, smaller layout area, low cost.

A circuit is described herein which may be used as an electronic fuse. According to one example, the circuit includes an integrated circuit (IC) with a chip contact for connecting, during operation, a filter circuit. The IC further includes a driver configured to drive a power transistor in accordance with a logic signal; a squaring circuit configured to receive a current sense signal that represents a load current passing through the power transistor and to output, at the chip contact, a first current that represents the squared load current; a comparator circuit configured to compare a voltage present at the chip contact with a reference voltage; and a control logic configured to generate the logic signal and to cause a switch-off of the power transistor dependent on an output signal of the comparator circuit.