764 results about "Comparators circuits" patented technology

The present disclosure provides a digital low-dropout regulator (DLDO) and an electronic device using the same. The DLDO includes a voltage comparator circuit, a switch control circuit, a power switch module, and an asynchronous clock generation circuit. The voltage comparator circuit compares a reference voltage with the output voltage to output a comparison result signal. The switch control circuit generates a switch control signal based on the comparison result signal. The power switch module is controlled by the switch control signal to switch between the on state and the off state, thereby adjusting the output voltage. The asynchronous clock generation circuit generates a reference clock signal that is asynchronous with the system clock signal used in the load circuit and has a higher clock frequency. This allows the switch control circuit to update the switch control signal based on the reference clock signal.

The embodiment of the invention relates to the technical field of digital signal processing, and discloses a DC-DC module control method and device, a medium and a product. Comprising the following steps: performing electrical parameter sampling on a DC-DC module, and judging whether a current working mode is a Buck mode or a Boost mode through a comparator circuit; calculating the deviation between the output voltage and the target voltage in the real-time electrical parameters, generating a PWM duty ratio adjusting signal, and generating a plurality of paths of staggered PWM driving signals through a phase shift circuit; performing power distribution on the multiple paths of staggered PWM driving signals, and adjusting the conduction time of each path of switch tube to obtain a current-sharing control signal; and analyzing the real-time electrical parameters, the current working mode, the PWM duty ratio adjustment signal, the multi-path staggered PWM driving signal and the current-sharing control signal to obtain a dynamic adjustment strategy. The technical problem that the control accuracy and efficiency of the DC-DC module are low can be at least solved.

A zero current detection device is proposed. The device may include a scaling circuit unit configured to generate a first voltage which is scaled from a target voltage. The device may also include a mirroring circuit unit configured to generate a mirroring current when the first voltage is higher than or equal to a reference voltage. The device may further include a comparator circuit unit configured to compare the target voltage and a ground voltage when the mirroring current is input.

Provided is voltage regulator circuit including an input node for receiving an input supply voltage, an output node for producing an output regulated voltage, and a switchable pass element arranged between the input and output nodes. A comparator circuit compares the output regulated voltage to a dynamic threshold to produce a control signal to control the switchable pass element. The control signal being asserted results in the switchable pass element being turned on, and vice-versa. A threshold selection and shaping circuit shapes the output regulated voltage or the dynamic threshold so that: (i) in response to assertion of the control signal, the difference between the dynamic threshold and the output regulated voltage is abruptly increased and subsequently gradually decreased towards a target static value, and (ii) in response to de-assertion of the control signal, the difference is abruptly increased and subsequently gradually decreased towards a target static value.

A system includes: 1) a battery configured to provide an input voltage (VIN); 2) switching converter circuitry coupled to the battery, wherein the switching converter circuitry includes a power switch; 3) a load coupled to an output of the switching converter circuitry; and 4) a control circuit coupled to the power switch. The control circuit includes: 1) a switch driver circuit coupled to the power switch; 2) a summing comparator circuit configured to output a first control signal that indicates when to turn the power switch on; and 3) an analog on-time extension circuit configured to extend an on-time of the power switch by gating a second control signal with the first control signal, wherein the second control signal indicates when to turn the power switch off.

Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN<VOUT), the comparator circuit disables the control circuit and enables the driver circuit, which in turn fully turns on a high-side switching element during high-side on-phase. In contrast, during start-up operation or an output short-to-ground condition (VIN≥VOUT), the comparator circuit disables the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side switching element, so the current through the switching element is regulated, and the switching node voltage is regulated to about a threshold voltage higher than VIN. In this manner, the comparator circuit controls the driver circuit and the control circuit, which in turn allow the boost converter to operate in a normal fashion even when VIN is higher than VOUT.

The invention discloses a drive circuit for inhibiting crosstalk of SiC MOSFET bridge arms, and relates to the technical field of power electronics, and the drive circuit is characterized in that a grid electrode of each bridge arm SiC MOSFET is connected with a push-pull circuit, a grid electrode voltage clamping circuit is connected in parallel between the push-pull circuit and the grid electrode of the SiC MOSFET, the G ends of two field effect transistors of the push-pull circuit are connected with PWM1 signals, and the G ends of the two field effect transistors of the grid electrode voltage clamping circuit are connected with the PWM M1 signals. An electrical isolation barrier sigma 1 exists between a PWM1 signal and the G end of the field effect transistor, the D end of the field effect transistor is connected to the grid electrode of the SiC MOSFET, the grid electrode voltage clamping circuit comprises a capacitor C and an auxiliary MOS transistor which are connected in series, and the G end of the auxiliary MOS transistor is further connected with a comparator circuit; the system is easy to integrate, the control strategy is simple, and no extra control signal is included.

The invention discloses a hysteresis comparator circuit capable of externally setting a threshold value, which comprises an input voltage ui, a positive and negative threshold voltage preset circuit, comparators A1, A2 and A3 and an A3 in-phase end voltage bias circuit, an output voltage uo, + / -Vcc and + Vcc are connected with-Vcc through a resistor R1, potentiometers P1 and P2 which are connected in parallel, a resistor R2 and form the positive and negative threshold voltage preset circuit, the sliding end of P1 is connected with the anti-phase end of A1, and the sliding end of P2 is connected with the anti-phase end of A3. The sliding end of the P2 is connected with the anti-phase end of the A2, the voltage ui is connected with the in-phase ends of the operational amplifier A1 and the operational amplifier A2 at the same time, the output end of the A1 is connected with the in-phase end of the operational amplifier A3 through the R3, the output end of the operational amplifier A2 is connected with the in-phase input end of the operational amplifier A3 through the resistor R4, the anti-phase input end of the operational amplifier A3 is connected with the working ground, and the output end of the operational amplifier A3 is connected with the in-phase input end of the operational amplifier A3 through the resistor R5. And the output end of the operational amplifier A3 outputs the output voltage uo.

The invention discloses a high-voltage power supply high-selection circuit and a control method thereof, the high-voltage power supply high-selection circuit comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1-INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6, the floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS, two inputs of the high-voltage floating comparator circuit are respectively connected with input signals V1 and V2, and the high-voltage floating comparator circuit is connected with the high-voltage PMOS tube PDM5 and the high-voltage PMOS tube PDM6. The inverters INV1-INV4 generate two inverted signals A and B according to an output signal of the high-voltage floating comparator circuit, a high-voltage power supply end of the high-voltage floating comparator circuit, a source electrode of the high-voltage PMOS tube PDM5 and a source electrode of the high-voltage PMOS tube PDM6D are connected with a floating high voltage HVDD, and a low-voltage power supply end of the high-voltage floating comparator circuit is connected with a floating low voltage HVSS. According to the invention, the high-voltage power supply high-selection circuit is realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention belongs to the technical field of analog integrated circuits, and particularly relates to a comparator circuit for a successive approximation type ADC (Analog to Digital Converter), which comprises a pre-amplifier stage circuit and a latch stage circuit, the pre-amplifier stage circuit is a cross coupling operational amplifier, and the latch stage circuit is a stroke-arm type latch comparator; a clock signal CLK is respectively input to the power supply ends of the cross coupling operational amplifier and the latch comparator; the positive input end of the cross-coupled operational amplifier is connected with a VIP signal, the negative input end of the cross-coupled operational amplifier is connected with a VIN signal, the negative output end of the cross-coupled operational amplifier is connected with the negative input end of the latch comparator, and the positive output end of the cross-coupled operational amplifier is connected with the positive input end of the latch comparator; a two-stage structure is adopted in the circuit structure, the characteristic that the first-stage operational amplifier is easy to process low voltage is combined with the characteristic that the second-stage latch is easy to process high voltage, and the voltage comparison speed of the comparator is effectively increased.

The invention relates to a dual-mode storage-calculation-encryption integrated circuit and an operation method thereof, in particular to an integrated circuit with both a PUF (Physical Unclonable Function) mode and an eCIM (Enhanced Common Information Model) mode. The dual-mode signal processor, the vector coding circuit, the word line driving circuit, the bit line driving circuit, the external signal decoding circuit, the selector circuit, the comparator circuit, the analog-to-digital converter and the shift adder circuit are arranged on the periphery; according to the PUF mode, the coupling complexity of the PUF in the spatial dimension is improved through complementary word lines, nonlinear XOR operation is achieved in each basic unit through a pairing method of two state complementary transistors, Hamming distance comparison between two columns is introduced, and the machine learning modeling attack resisting safety of the PUF is improved; according to the eCIM mode, an encrypted data weight matrix stored in a transistor is protected through XOR encryption, high-energy-efficiency and high-parallelism in-memory calculation operation is achieved through a nonvolatile transistor array, and high-parallelism in-situ decryption in-memory calculation is completed through complementary word lines.

The invention discloses an electronic device and a voltage leakage circuit, the electronic device comprises a control circuit and a power circuit, the control circuit is connected with the power circuit and is used for controlling the power circuit to perform leakage or stop leakage, and the control circuit comprises a voltage division circuit; the comparison circuit is connected with the voltage division circuit and is used for receiving the first voltage from the voltage division circuit and comparing the first voltage with a preset reference voltage; the driving circuit receives the first reference voltage, is connected with the comparison circuit and the power circuit, and is used for outputting the first reference voltage to the power circuit when the first voltage is greater than or equal to the reference voltage so as to control the power circuit to discharge; one end of the hysteresis circuit is connected with the power circuit, the other end of the hysteresis circuit is connected between the voltage division circuit and the comparison circuit, and the hysteresis circuit is used for increasing the first voltage when the driving circuit outputs the first reference voltage to the power circuit. The power circuit is controlled through the voltage division circuit, the comparison circuit and the driving circuit, the cost can be reduced, and the occupied space is small.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

An oscillator circuit, a corresponding radar sensor, a vehicle, and an operating method are disclosed. An oscillator includes a tunable resonant circuit having an inductor and a variable capacitor coupled between a first node and a second node, and a set of capacitors selectively coupled between the first node and the second node. An input control node receiving an input control signal is coupled to the variable capacitor and the set of capacitors. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits having hysteresis compares the input control signal with the set of different voltage thresholds to generate a set of control signals. The capacitors in the set of capacitors are selectively coupled between the first node and the second node according to the control signals in the set of control signals.

In disclosed embodiments, a voltage sensor of a computing device is configured to determine a voltage level of a supply voltage provided by a power supply to processor circuitry. Comparator circuitry may perform a comparison operation that compares the determined voltage level to a threshold. A temperature sensor may determine a temperature of at least a portion of processor circuitry. Power control circuitry may initiate a power management operation to adjust voltage margin based on a result of the comparison operation. Additionally, the power management circuitry may control the comparator circuitry to impose an offset on the comparison operation. The power control circuitry may determine a magnitude of the offset based on a pre-determined effect of the determined temperature on voltage margin parameters for at least a portion of the processor circuitry.

The invention provides a hysteresis comparator circuit and system, and relates to the technical field of integrated circuits, and the hysteresis comparator circuit comprises a differential comparison module, a tail current bias module, a self-adaptive shunt module and an output module. The output end of the tail current bias module, the first port of the differential comparison module and the second port of the adaptive shunt module are all connected to a first node, and the second port of the differential comparison module is connected with the second port of the output module. When the common-mode input range is normal, the adaptive shunt module is turned off, and the bias current output by the tail current bias module flows to the first port of the differential comparison module. When the common-mode input range is abnormal, the self-adaptive shunt module is conducted, and the self-adaptive shunt module is used for extracting part of bias current output by the tail current bias module so as to reduce the value of current flowing to the first port of the differential comparison module. The influence of the change of the common-mode voltage on the current flowing to the first port of the differential comparison module is weakened, so that the common-mode input range of the hysteresis comparator is widened.

In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.

Sense amplifier circuits are disclosed that are particularly useful in sensing neural responses in an implantable pulse generator (IPG). The IPG includes a plurality of electrodes, one of which is selected as a sensing electrode and another of which is selected as a reference to differentially sense neural responses in a manner that subtracts a common mode voltage (e.g., a stimulation artifact) from the measurement. These circuits include a differential amplifier that receives the selected electrodes at its inputs, and a comparator circuit for evaluating each differential amplifier input to determine whether its magnitude is consistent with the input requirements of the differential amplifier. Based on these determinations, an enable signal is generated that notifies whether the output of the differential amplifier is effectively providing a neural response at any point in time. In addition, a clamp circuit is connected to the differential amplifier inputs to clamp the magnitude of these inputs to prevent damage to the differential amplifier.

According to an embodiment, a max-pooling neuron with first and second integrator circuits, a comparator circuit, a Schmitt trigger circuit, and a pair of switches is provided. The first and second integrator circuits, respectively filter a first and a second input train from a first and a second neuron of a previous layer to generate a corresponding first and second filtered input train. The comparator circuit amplifies a difference between the first and second filtered input trains and generates an amplified differential signal. The Schmitt trigger circuit generates a binary output signal based on the amplified differential signal. The pair of switches have a common first terminal coupled to an output node of the max-pooling neuron and a common control terminal coupled to the output terminal of the Schmitt trigger circuit. The other terminals of the pair of switches are coupled to respective input trains.

In a described example, a circuit includes a comparator circuit including an input, a first output, and a second output. An offset control circuit includes a first input, a second input, a first output, and a second output, in which the first input is coupled to the first output of the comparator circuit, the second input is coupled to the second output of the comparator circuit. A first delay circuit is coupled between the first input and the first output of the offset control circuit. A second delay circuit is coupled between the second input and the second output of the offset control circuit. An offset calibration circuit has a first input and a second input, in which the first input is coupled to the first output of the offset control circuit, the second input is coupled to the second output of the offset control circuit.

The invention relates to the technical field of battery management, and provides a battery balance charge and discharge control method and system, and the method comprises the steps: constructing a voltage comparator circuit model of a multi-section series lithium battery pack, and calculating the electric quantity fullness corresponding to the multi-section series lithium battery pack based on the voltage comparator circuit model; scheduling charging and discharging process data corresponding to the plurality of serially connected lithium battery packs from the control upper computer, constructing a volt-ampere characteristic curve corresponding to the plurality of serially connected lithium battery packs, and calculating a vitality index of the plurality of serially connected lithium battery packs; the method comprises the following steps: acquiring temperature sensing signals corresponding to a plurality of serially connected lithium battery packs in real time, performing signal conditioning on the temperature sensing signals to obtain standard temperature signals, converting the standard temperature signals into temperature digital values, and calculating thermal stability coefficients corresponding to the plurality of serially connected lithium battery packs based on the temperature digital values; and identifying an unbalanced battery pack and a to-be-balanced battery pack in the plurality of lithium battery packs connected in series, and executing balance control processing of the unbalanced battery pack to obtain a control result. The invention aims to improve the accuracy of battery balance charge and discharge control.

A voltage tester system / device for safety application in AC & DC electrical systems and method thereof. The system / device includes a voltage presence indicator (VPI) circuit including plurality of zener diodes, bi-directional current-limiter circuits, VPI-LEDs and an absence of voltage tester (AVT) circuit including plurality of comparator circuits, optocouplers, DC-DC converters, microcontroller, power-management circuit, battery, LEDs and diodes. The VPI circuit converts electrical energy potential between the lines in range of 3 to 3394 volts (phase to neutral) / 5.2 to 5879 volts (phase to phase) into electrical inputs that drives VPI-LEDs to produce light output. The AVT circuit helps in checking circuit wires intactness with their respective busbars and verify absence of hazardous voltage by providing positive indication with a GREEN-light when safe voltage level is attained at connected leads, and voltage is less than a preset threshold value.

A gate driver circuit includes a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on-state and an off-state; at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sense value representative of a voltage transient of the power switch; a comparator circuit configured to compare the sense value to a threshold, and further configured to generate a comparison result based on whether the sense value satisfies the threshold; and a short circuit detector configured to detect a short circuit event based on the on-state of the power switch being detected and based on the comparison result indicating that the sense value satisfies the threshold.

A current comparator comprising: a P-type metal oxide semiconductor field effect transistor, PMOS FET (614), and an N-type metal oxide semiconductor field effect transistor, NMOS FET (615). The source of the PMOS FET is connected to a first comparator input terminal (610). The source of the NMOS FET is connected to a second comparator input terminal (611). The drain of the PMOS FET is connected to a current-comparator-input-node (602). The drain of the NMOS FET is connected to the current-comparator-input-node. The gate of the PMOS FET is connected to a first bias-voltage-node (VP). The gate of the NMOS FET is connected to a second bias-voltage-node (VN). The current comparator also includes a bias circuit (613) that provides a bias voltage to each of the first and second bias-voltage-nodes, and a current-comparator-circuit (601). A current-comparator-circuit-input-terminal (602) is connected to the current-comparator-input-node in order to receive a difference-current-input signal (IIn), which is representative of the difference between a first current input signal and a second current input signal. The current-comparator-circuit is configured to provide a current comparator output signal (Vout) as a digital voltage signal based on the received difference-current-input signal.

The invention relates to a pulse width modulation silicon resonant pressure sensor closed-loop circuit and a debugging method, the pulse width modulation silicon resonant pressure sensor closed-loop circuit comprises a resonant sensor, a current and voltage conversion circuit, a comparator circuit, an amplitude control circuit and a pulse width modulation generation circuit, and the comparator circuit converts the amplified frequency signal into a square wave signal, generates a pulse signal through the pulse width modulation generation circuit, and is connected to the driving end of the resonator to generate a driving signal to form a closed-loop system. Wherein the amplitude control circuit is used for detecting the signal amplitude of the sensor and generating a control signal to adjust the impedance of the pulse width modulation generation circuit so as to adjust the pulse width of the driving signal and finally realize the stable closed loop of the sensor. According to the method of the closed-loop circuit based on pulse width modulation, the structure of the closed-loop driving circuit is optimized, the number of components is reduced, the pull-in risk is reduced, and the stability of the closed loop is improved.

An analog-to-digital converter (ADC) circuit includes a first comparator circuit, a second comparator circuit, and an interpolation circuit. The first comparator circuit includes a first input terminal to receive a first reference voltage signal and a second input terminal to receive an input voltage signal. The second comparator circuit includes a first input terminal to receive a second reference voltage signal and a second input terminal to receive the input voltage signal. The interpolation circuit includes a first input terminal coupled to a first output terminal of the first comparator and a second input terminal coupled to a first output terminal of the second comparator.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention provides a wide dynamic range methane detection system based on synchronous accumulation and system reconstruction. The device is characterized by comprising a modulated laser (1), a gas absorption cell (2), a photoelectric detector (APD) (3), a variable gain trans-impedance amplifier (TIA) (4) based on a digital potentiometer, a dual-threshold voltage comparator circuit (5) and a microcontroller processing unit (6). The device can be used for large-dynamic-range real-time monitoring of the methane gas concentration, and the problem that a traditional TDLAS system is prone to saturation or limited in detection limit when the concentration span is large is effectively solved. The method can be widely applied to the fields of gas concentration detection, industrial safety control and the like.

The invention discloses an overvoltage protection circuit and method. The circuit comprises a sampling circuit, a current mirror circuit, a charging circuit and a comparator circuit, the sampling circuit is used for sampling the voltage of the voltage detection end to obtain a sampled voltage; the current mirror circuit is used for scaling down the sampling voltage and charging the charging circuit; and the comparator circuit is used for detecting the voltage of the charging circuit and sending an overvoltage protection signal when determining that the charging voltage is greater than a preset overvoltage protection threshold value. According to the overvoltage protection circuit, the current flowing through the first capacitor is scaled down through the current mirror by the current mirror circuit, then the second capacitor is charged by the scaled-down current, and when the voltage on the capacitor reaches the threshold value, overvoltage protection is triggered. The voltage sampling network is a capacitor and has no static power consumption. And the capacitor can be integrated into the chip, so that the system integration level can be effectively improved.