2288 results about "Comparators circuits" patented technology

A lighting control circuit comprises a dimming level detection circuit, a waveform generator and a comparator circuit. The dimming level detection circuit is configurable to generate a first voltage level signal corresponding to a selected one of at least two different types of dimming signals selected from among an AC phase cut dimming signal, a DC voltage level dimming signal or a PWM dimming signal. The waveform generator is configured to output a periodic waveform. The comparator circuit is configured to compare the periodic waveform with the first voltage level signal to generate an output waveform having a duty cycle corresponding to a dimming level of the one of the at least two different input dimming signals and a frequency corresponding to the frequency of the periodic waveform. Also, methods of controlling lighting.

A method for calibrating an optical reflectance proximity sensor and then measuring proximity in a repeating cycle or on demand, the sensor including one or more wavelength transmitting diodes, one or more wavelength receiving diodes, an ambient correction circuit, and a comparator circuit, and further teaching steps for powering on the sensor, canceling the ambient signal during a calibration period, transmitting wavelengths to and receiving reflectance from an object in the path of the transmitted wavelengths, and measuring a reflectance pulse width and comparing the value to a preset value to determine proximity.

There is provided a lighting control circuit comprising a duty cycle detection circuit, an averaging circuit, a waveform generator and a comparator circuit. The duty cycle detection circuit generates a first periodic waveform having a duty cycle and frequency corresponding to an input waveform duty cycle and frequency. The averaging circuit generates a first signal having a voltage level corresponding to the duty cycle of the first periodic waveform. The waveform generator outputs a second periodic waveform having a frequency different from the input waveform frequency. The comparator circuit compares the second periodic waveform with the first signal to generate an output waveform having a duty cycle corresponding to the input waveform duty cycle and a frequency corresponding to the frequency of the second periodic waveform. Also, there are provided methods.

One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase change materials or perovskite materials are typically used in resistive memory devices and have the ability to change the resistance reversibly and repeatable with applied electrical pulses. The present invention reversible resistor trimming circuit comprises a resistance bridge network of a matching resistor and a reference resistor to provide inputs to a comparator circuit which generates a comparing signal indicative of the resistance difference. This comparing signal can be used to control a feedback circuit to provide appropriate electrical pulses to the matching resistor to modify the resistance of the matching resistor to match that of the reference resistor.

Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and / or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.

A method and apparatus for measuring battery depletion in an implantable medical device is presented. The apparatus includes first and second switch pairs disposed in series between the battery and a load, and connected in a parallel arrangement with respect to one another. A capacitor is connected in a first polarity between the battery and the load when only first and fourth switches are closed and in a second polarity when only second and third switches are closed. A comparator circuit causes the switches to reverse the capacitor's polarity based on a comparison of the voltage drop across the capacitor to a threshold value. A counter counts the number of times the capacitor reverses polarity, which is proportional to the amount of charge transferred from the battery during its lifetime in the device and indicative of the battery's level of depletion.

A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V− input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.

Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and / or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.

A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller than those generated by current sources of the other charge pump circuit. The loop filter has a first capacitive element connected to a charge / discharge node, and a second capacitive element connected to the charge / discharge node through a resistive element. The first capacitive element is charged and discharged by the one charge pump circuit, while the second capacitive element is charged and discharged by the other charge pump circuit. A charging current source of the one charge pump circuit operates simultaneously with a discharging current source of the other charge pump circuit, i.e., the charge pump circuits operate in opposite phase.

Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value. The pre-code selection circuit is operable to determine a selectable configuration of the first data detector circuit based at least in part on the first comparison value and the second comparison value.

A novel voltage regulator includes an indictor, a switching transistor, a rectifier, an error amplifier circuit, a first voltage comparator circuit, a second voltage comparator circuit, an oscillator circuit, and a driver circuit. The first voltage comparator circuit outputs a modulation signal. The second voltage comparator circuit activates an enable signal when the error voltage exceeds the second reference voltage. The oscillator circuit outputs a clock signal with a fixed frequency according to the enable signal. The oscillator circuit enters a first state when the enable signal is activated and deactivated within a period of time shorter than a threshold time, and enters a second state when the enable signal remains activated during a period of time longer than the threshold time. The driver circuit generates the switching control signal based on the clock signal and the modulation signal.

A buck-boost regulator for converting an input voltage to an output voltage which includes an inductor, an error circuit providing an error voltage, buck and boost switching circuits, buck and boost ripple circuits, and buck and boost hysteretic comparator circuits. The buck switching circuit switches a first end of the inductor, the buck ripple circuit replicates ripple current through the inductor based on the buck pulse signal and provides a buck ripple voltage, and the buck hysteretic comparator circuit develops the buck pulse signal based on a buck window voltage range using the error voltage. The boost switching circuit switches a second end of the inductor, the boost ripple circuit replicates ripple current through the inductor based on the boost pulse signal and provides a boost ripple voltage, and the boost hysteretic comparator circuit develops the boost pulse signal based on a boost window voltage range using the error voltage.

A control circuit is incorporated in a switching regulator for monitoring and maintaining a bootstrap voltage to allow the switching regulator to operate at or near 100% duty cycle. The control circuit includes a circuit receiving the bootstrap voltage and generating a monitor voltage, a comparator circuit receiving the monitor voltage and a first voltage indicative of a switching output voltage and generating an output signal having a first state when the monitor voltage is equal to or less than the first voltage, a logic circuit receiving the output signal and generating drive control signals to driver circuits driving the high-side and low-side power switches. The logic circuit generates the drive control signals in response to the output signal of the comparator circuit having the first state to cause the high-side power switch to turn off and the low-side power switch to turn on, thereby recharging the bootstrap voltage.

There has been a problem in battryless RFID chips that a high voltage AC signal is generated when an antenna is exposed to a high electromagnetic field, and a DC voltage that is obtained through rectification of the AC signal becomes a high voltage accordingly. As a result, heat generation of a logic circuit and a clock generator circuit or element break down occur. The invention takes the following measures: a DC voltage generated through rectification of an AC signal is compared with a reference voltage in a comparator circuit, and a switch element is turned ON when the DC voltage becomes higher so as to add capacitance to an antenna circuit. Accordingly, resonance point of an antenna changes which in turn attenuates an AC signal generated in the antenna circuit, thereby suppressing a DC voltage.

A steady state frequency control circuit for a variable frequency regulator including an open loop frequency control circuit, a frequency detector and a comparator circuit. The variable frequency regulator provides a clock signal indicating actual operating frequency and has a frequency control parameter for adjusting steady state operating frequency. The frequency detector receives the clock signal and provides a frequency sense signal which is compared with a steady state frequency reference signal to provide a frequency adjust signal. The frequency control parameter is adjusted by the frequency adjust signal to control steady state frequency. A method of controlling steady state frequency of a variable frequency regulator includes using open loop frequency control, determining the operating frequency and providing a frequency sense signal, comparing the frequency sense signal with frequency reference signal and providing a frequency adjust signal, and adjusting the frequency control parameter based on the frequency adjust signal.

Suppression malfunction of an authentication circuit for authenticating a battery pack. Signal line for applying an intermediate potential between the power supply and ground and for reading the potential of a thermistor for detecting the temperature is used as a transmission path for exchanging data between a battery pack and main device. A master-authentication circuit and slave-authentication circuit comprise level-correction circuits, which are connected to the signal line by way of a voltage-comparator circuit. The level-correction circuits are constructed such that they correct the signal applied to the signal line so that it is greater than or less than the unstable-region voltage, and outputs it to the input end of the authentication circuits, so that unstable-region voltage is not applied to the input end. Output circuits overlap in turn authentication information onto the signal line when performing authentication, and the level-correction circuits receive the respective information, and authentication is performed.

A semiconductor circuit including: an A / D converter circuit which converts an inputted first signal into a second signal. The A / D converter circuit includes a comparator circuit which compares a voltage of the first signal and a reference voltage; an A / D conversion controller circuit which outputs a digital signal in accordance with comparison results given by the comparator circuit, as a fourth signal and which outputs, in accordance with the third signal, a digital signal corresponding to the first signal, as the second signal; and a D / A converter which converts an inputted fourth signal into an analog signal and which outputs the analog signal as the reference signal. The comparator circuit includes a transistor having a first gate and a second gate. The first signal is inputted to the first gate, the reference signal is inputted to the second gate.

A system and method for efficient input / output (I / O) port overvoltage protection of a high-speed port. An interfacing system for connecting peripheral devices to a computing system comprises ports for conveying serial communications bidirectional signals and an overvoltage protection circuit. The protection circuit prevents an overvoltage condition on one port in response to an overvoltage event on a corresponding second port. In one embodiment, the interfacing system connects USB peripheral devices to an automotive infotainment system comprising an automotive battery potiential greater than a USB power supply. In addition, the overvoltage protection circuit is able to transmit signals between the two ports without signal attenuation defined by an industry standard specification such as Universal Serial Bus (USB) Implementers Forum (IF) eye pattern diagram test. The overvoltage protection circuit is configured to have a small footprint, and, therefore, does not utilize a power reference and comparator circuit.

The present invention is a method and system for providing improved isolation for power supplies while minimizing power dissipation. A body diode of a MOSFET may be utilized with a comparator circuit. The comparator circuit may detect current flow across the MOSFET and may turn the MOSFET on. This may shunt the diode with a low drain to source resistance limiting power dissipation across the diode to an amount of the drain to source current squared (Ids2) times the drain to source resistance of the MOSFET when on (RDSon). Use of the comparator circuitry may reduce the time delay associated with turning the MOSFET off to prevent a high reverse inrush current within a power supply.

A fast motion estimation system that determines a reference macroblock or sub-block combination within a reference frame for a current macroblock in a current frame includes a memory, a reference macroblock search circuit, a sub-block combination search circuit, and a comparator circuit. The reference macroblock search circuit determines a motion vector, multiple difference values, and a cost value for each macroblock within the reference frame according to a fast motion estimation search pattern, and stores the motion vector and the difference values in the memory. The sub-block combination search circuit searches the motion vector and the difference values in the memory for determining a corresponding one of multiple lowest cost sub-block combinations for each of multiple sub-block motion modes. The comparator circuit determines a lowest cost macroblock and selects from among the lowest cost macroblock and the lowest cost sub-block combinations to determine the reference macroblock.

A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a comparator circuit coupled to a reference clock and a phase-corrected output signal. The frequency synthesizer circuit also includes a loop filter coupled to the comparator circuit. The frequency synthesizer circuit also includes an oscillator coupled to the loop filter. The frequency synthesizer circuit also includes a fractional divider coupled to an output of the oscillator. The frequency synthesizer circuit also includes phase correction circuitry that corrects a phase of an output of the fractional divider to produce the phase-corrected output signal.

An electronic fault detection unit is provided that has a first register, a second register, a comparator circuit, and a timer circuit. The first and second register can be written from a first software portion, and a second software portion, respectively. The comparator circuit is arranged to detect that both the first and second register have been written, verify a relationship between first data written to the first register and second data written to the second register, and signal a fault upon said verification failing. The timer circuit is arranged to signal a fault if said verification of the comparator circuit does not occur within a time limit.