432 results about "Comparators circuits" patented technology

The invention discloses a high-voltage power supply high-selection circuit and a control method thereof, the high-voltage power supply high-selection circuit comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1-INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6, the floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS, two inputs of the high-voltage floating comparator circuit are respectively connected with input signals V1 and V2, and the high-voltage floating comparator circuit is connected with the high-voltage PMOS tube PDM5 and the high-voltage PMOS tube PDM6. The inverters INV1-INV4 generate two inverted signals A and B according to an output signal of the high-voltage floating comparator circuit, a high-voltage power supply end of the high-voltage floating comparator circuit, a source electrode of the high-voltage PMOS tube PDM5 and a source electrode of the high-voltage PMOS tube PDM6D are connected with a floating high voltage HVDD, and a low-voltage power supply end of the high-voltage floating comparator circuit is connected with a floating low voltage HVSS. According to the invention, the high-voltage power supply high-selection circuit is realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention discloses an electronic device and a voltage leakage circuit, the electronic device comprises a control circuit and a power circuit, the control circuit is connected with the power circuit and is used for controlling the power circuit to perform leakage or stop leakage, and the control circuit comprises a voltage division circuit; the comparison circuit is connected with the voltage division circuit and is used for receiving the first voltage from the voltage division circuit and comparing the first voltage with a preset reference voltage; the driving circuit receives the first reference voltage, is connected with the comparison circuit and the power circuit, and is used for outputting the first reference voltage to the power circuit when the first voltage is greater than or equal to the reference voltage so as to control the power circuit to discharge; one end of the hysteresis circuit is connected with the power circuit, the other end of the hysteresis circuit is connected between the voltage division circuit and the comparison circuit, and the hysteresis circuit is used for increasing the first voltage when the driving circuit outputs the first reference voltage to the power circuit. The power circuit is controlled through the voltage division circuit, the comparison circuit and the driving circuit, the cost can be reduced, and the occupied space is small.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

In disclosed embodiments, a voltage sensor of a computing device is configured to determine a voltage level of a supply voltage provided by a power supply to processor circuitry. Comparator circuitry may perform a comparison operation that compares the determined voltage level to a threshold. A temperature sensor may determine a temperature of at least a portion of processor circuitry. Power control circuitry may initiate a power management operation to adjust voltage margin based on a result of the comparison operation. Additionally, the power management circuitry may control the comparator circuitry to impose an offset on the comparison operation. The power control circuitry may determine a magnitude of the offset based on a pre-determined effect of the determined temperature on voltage margin parameters for at least a portion of the processor circuitry.

In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.

In a described example, a circuit includes a comparator circuit including an input, a first output, and a second output. An offset control circuit includes a first input, a second input, a first output, and a second output, in which the first input is coupled to the first output of the comparator circuit, the second input is coupled to the second output of the comparator circuit. A first delay circuit is coupled between the first input and the first output of the offset control circuit. A second delay circuit is coupled between the second input and the second output of the offset control circuit. An offset calibration circuit has a first input and a second input, in which the first input is coupled to the first output of the offset control circuit, the second input is coupled to the second output of the offset control circuit.

A voltage tester system / device for safety application in AC & DC electrical systems and method thereof. The system / device includes a voltage presence indicator (VPI) circuit including plurality of zener diodes, bi-directional current-limiter circuits, VPI-LEDs and an absence of voltage tester (AVT) circuit including plurality of comparator circuits, optocouplers, DC-DC converters, microcontroller, power-management circuit, battery, LEDs and diodes. The VPI circuit converts electrical energy potential between the lines in range of 3 to 3394 volts (phase to neutral) / 5.2 to 5879 volts (phase to phase) into electrical inputs that drives VPI-LEDs to produce light output. The AVT circuit helps in checking circuit wires intactness with their respective busbars and verify absence of hazardous voltage by providing positive indication with a GREEN-light when safe voltage level is attained at connected leads, and voltage is less than a preset threshold value.

An analog-to-digital converter (ADC) circuit includes a first comparator circuit, a second comparator circuit, and an interpolation circuit. The first comparator circuit includes a first input terminal to receive a first reference voltage signal and a second input terminal to receive an input voltage signal. The second comparator circuit includes a first input terminal to receive a second reference voltage signal and a second input terminal to receive the input voltage signal. The interpolation circuit includes a first input terminal coupled to a first output terminal of the first comparator and a second input terminal coupled to a first output terminal of the second comparator.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention provides a wide dynamic range methane detection system based on synchronous accumulation and system reconstruction. The device is characterized by comprising a modulated laser (1), a gas absorption cell (2), a photoelectric detector (APD) (3), a variable gain trans-impedance amplifier (TIA) (4) based on a digital potentiometer, a dual-threshold voltage comparator circuit (5) and a microcontroller processing unit (6). The device can be used for large-dynamic-range real-time monitoring of the methane gas concentration, and the problem that a traditional TDLAS system is prone to saturation or limited in detection limit when the concentration span is large is effectively solved. The method can be widely applied to the fields of gas concentration detection, industrial safety control and the like.

A switching regulator includes: a switching circuit that switches an input voltage based on a gate control signal, and outputs a switching voltage; a voltage difference detector that compares the switching voltage with a threshold value depending on the input voltage, and outputs a comparison result signal; and a control circuit that generates a gate control signal based on an output voltage to which the switching voltage is fed back after smoothed and the comparison result signal, and outputs the gate control signal to the switching circuit. The voltage difference detector includes: an integration circuit that generates a pseudo-output voltage obtained by integrating the switching voltage on time and substantially equal to the output voltage; and a comparator circuit that compares the pseudo-output voltage with a threshold value depending on a power supply voltage, and outputs the comparison result signal.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

A continuity detector for determining the continuity of a Unit Under Test (UUT). The detector comprises a housing defining an interior volume, an electronics package disposed within the interior volume defined by the housing assembly, a first test contact and a second test contact to interface with the electrical wire or harness assembly, a precision resistance standard disposed within the housing and electrically coupled to the electronics package, and a power source disposed within the housing assembly. The first test contact and the second test contact are external to the interior volume. The first test contact and the second test contact are electrically coupled to the electronics package. The electronics package comprising a resistance measurement device and a comparator circuit. The comparator circuit is configured to determine if the resistance of the UUT is greater than, less than, or equal to the resistance of the resistance standard.

The embodiment of the invention provides a hysteresis comparator circuit and a hysteresis comparator, the hysteresis comparator circuit comprises an open-loop operational amplifier circuit, the open-loop operational amplifier circuit is used for receiving a reference input and a comparison input, and determining a comparison output according to the reference input and the comparison input; the current feedback control circuit is connected with the open-loop operational amplifier circuit and used for controlling hysteresis current to be input to the open-loop operational amplifier circuit according to the comparison output, and the open-loop operational amplifier circuit feeds back and adjusts hysteresis voltage under the action of the hysteresis current; the bias voltage providing circuit is connected with the open-loop operational amplifier circuit and used for providing bias voltage for the open-loop operational amplifier circuit, and the bias voltage is used for controlling on-off of the open-loop operational amplifier circuit. The hysteresis comparator solves the technical problems that the hysteresis amount in the hysteresis comparator in the prior art is influenced by the power supply voltage and the hysteresis window is asymmetric.

A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. The circuit includes a first-stage positive feedback module, a second-stage triggering and clocking module, a second-stage positive feedback amplification module, and a third-stage positive feedback latching module. By employing a three-stage positive feedback structure, this invention places the corresponding differential signal nodes in the same feedback loop at each stage, significantly enhancing the comparator's amplification rate and metastability suppression capability. Furthermore, by introducing a fast timing control mechanism, the second-stage amplification, clock reset generation, and third-stage latching operations can be executed in parallel, effectively shortening the critical path delay and significantly improving the overall comparison speed. The electronic device includes the aforementioned comparator circuit. This invention effectively solves the bottlenecks of traditional comparators in terms of speed and reliability and is suitable for high-speed, high-precision data conversion systems.

The invention discloses a motor forward and reverse rotation driving circuit and system, and the circuit comprises a reference voltage supply circuit which is provided with a reference voltage output end; the first reference voltage providing circuit is provided with a first reference voltage output end; the reference voltage output end and the first reference voltage output end are respectively connected with the first comparator circuit; wherein the reference voltage is gradually changed from the first reference voltage to the second reference voltage, the first reference voltage is located between the first reference voltage and the second reference voltage, so that the reference voltage is smaller than the first reference voltage in a first time period and larger than the first reference voltage in a second time period, and the first time period and the second time period are not overlapped; and the first comparator circuit is connected with the motor driving circuit. When the motor rotates positively and negatively, a single chip microcomputer is not needed, the cost is reduced, software burning is not needed, and the process is simple during mass production.

Content-addressable memory-in-display (CAMiD) electronic displays and circuitry are provided. An electronic display may include a pixel active array and a number of content-addressable control cells. Each control cell controls a respective display pixel of the pixel active array. Each control cell includes a comparator to generate a control signal to control the respective display pixel of the pixel active array based on a comparison between pixel data for the respective display pixel and one or more counters corresponding to a gray level.

The utility model relates to a PD detection alarm protection circuit of a laser. The PD detection alarm protection circuit comprises a PD sensor, a resistance voltage division circuit, an in-phase proportion amplification circuit, a comparator circuit and a voltage reference circuit, the PD sensor collects a PD photocurrent signal of the laser and then sends the PD photocurrent signal to the resistance voltage division circuit; the resistance voltage division circuit converts the PD photocurrent signal into a PD voltage signal and then sends the PD voltage signal to the in-phase proportion amplification circuit; the in-phase proportional amplification circuit amplifies the PD voltage signal and then transmits the PD voltage signal to one input end of the comparator circuit, the other input end of the comparator circuit is connected with the voltage reference circuit, and the output end of the comparator circuit outputs a processed PD signal; by optimizing a pre-stage amplification framework and a post-stage reference design, the detection reliability is remarkably improved while the cost is reduced, and the detection response speed is very high. And real-time monitoring can be realized through an upper computer. The system is especially suitable for a safety protection system of industrial laser equipment.

The invention discloses an LVDS (Low Voltage Differential Signaling) receiving circuit with a wide common-mode input range. The LVDS receiving circuit comprises a common-mode conversion circuit, a main comparator circuit, a secondary comparison circuit and a logical judgment circuit, the common-mode conversion circuit is used for converting an external wide common-mode input differential signal into a signal with constant common-mode voltage and no attenuation of the differential signal; the main comparator circuit identifies the converted differential signal to complete differential-to-single-ended data conversion; the secondary comparator circuit is composed of two low-speed comparators; and the logic judgment circuit judges the output of the main comparator and the window comparator to ensure that the output of the input end of the circuit group is a constant level under the short circuit and disconnection conditions, so that the function of dynamic failure protection of the circuit is realized. The wide common-mode input circuit can realize discrimination of wide common-mode input signals ranging from-4V to 5V, and has a dynamic failure protection function.

A delta-sigma modulator includes a comparator circuit having an output that provides a digital signal indicative of a voltage of a signal received at an input of the comparator circuit. The modulator includes a continuous-time path from a modular input to an input of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path and providing a first feedback current controlled by the comparator circuit output and a second second feedback loop providing a second feedback current controlled by the comparator circuit output to a second integrating node of the path, the second integrating node connected to the input of the comparator and to a capacitor.

The application provides a reverse voltage protection circuit and a bus transceiver, and the reverse voltage protection circuit comprises a comparator, the input port and the output port of the circuit are connected with the input end of the comparator, the comparator is used for comparing the voltage of the input port and the output port, and outputs a comparison signal; a trigger circuit receives the comparison signal, turns on / off a MOS tube connected between the input port and the output port according to the comparison signal; and the MOS tube is used for preventing abnormal voltage of the output port from flowing back to the input port. By using the above circuit, the trigger circuit can be turned on or turned off by comparing the voltage of the input port and the output port, the MOS tube is controlled in the off state by the trigger circuit, the abnormal voltage is prevented from flowing back to the input port, the function of the high-voltage diode is replaced by the reverse voltage protection circuit, the use of the high-voltage diode is reduced, and the manufacturing difficulty and the manufacturing cost of the chip are reduced.

The present technology is directed to a method, circuit and system for improved power management, and in an aspect there is provided control circuitry for controlling operation of an associated power multiplexer circuit, the control circuitry including: a first input to receive a first voltage; a second input to receive a second voltage; comparator circuitry to determine the level of the first voltage relative to the second voltage and to generate a first control signal when the second voltage reaches a first threshold level relative to the first voltage, where the first control signal is to indicate a desired output of the associated power multiplexer circuit.

Memory circuit with a memory array comprising first memory cells and second memory cells, each of the first memory cells being configured to store a data bit, and each subset of the second memory cells being configured to store repair bits, the repair bits indicating a location of a corresponding first memory cell and a random bit; register circuits, the register circuits being configured to transmit or lock the multiple repair bits; a comparator circuit coupled to the register circuits being configured to provide a match signal in response to the finding that an address signal matches the location of the corresponding first memory cell indicated by the repair bits;and a multiplexer coupled to the comparator circuit, configured to output the random bit instead of the data bit stored by the corresponding first memory cell based on the matching signal.

The invention discloses an oscillator circuit with low power consumption and quick start and a control method thereof, the oscillator circuit comprises a starting circuit, a bias current generating circuit and an oscillating circuit, the input end of the starting circuit is connected with starting current IStart, the first output end of the starting circuit is connected with the first input end of the bias current generating circuit, and the second output end of the bias current generating circuit is connected with the oscillating circuit. The second output end of the starting circuit is connected with the second input end of the bias current generating circuit, and the oscillating circuit mirrors the current of the bias current generating circuit and alternately charges and discharges the two capacitors to generate OSC signals. Charging and discharging current is generated in the circuit, a comparator circuit is not adopted, the requirement and power consumption of an external circuit are greatly reduced, frequency selection switching and synchronous switching of the starting circuit can be carried out, and the starting time of the circuit is prolonged.

An example apparatus includes: alternating current (AC) source circuitry having an input and an output; comparator circuitry having an input and an output, the output of the comparator circuitry coupled to the input of the AC source circuitry; integrator circuitry having an output of the integrator circuitry coupled to the input of the comparator circuitry; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the output of the AC source circuitry, the second terminal of the capacitor coupled to the integrator circuitry.

This disclosure provides an external constant current circuit based on a DC-DC converter. The external constant current circuit includes a signal conversion operational amplifier circuit, a comparator circuit, a current regulation circuit, and a buffer. Specifically, the signal conversion operational amplifier circuit acquires the output current of the DC-DC converter, converts and amplifies the output current into a first voltage signal. The comparator circuit then compares the first voltage signal with an external reference voltage signal to output a second voltage signal. When the output current exceeds the constant current threshold, the current regulation circuit adjusts the current injected into the voltage feedback pin using the second voltage signal, thereby regulating the output current and maintaining it constant at the constant current threshold. This solves the problem of how to more efficiently implement constant current functionality in chips based on existing DC-DC converters.