592 results about "Comparators circuits" patented technology

Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN<VOUT), the comparator circuit disables the control circuit and enables the driver circuit, which in turn fully turns on a high-side switching element during high-side on-phase. In contrast, during start-up operation or an output short-to-ground condition (VIN≥VOUT), the comparator circuit disables the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side switching element, so the current through the switching element is regulated, and the switching node voltage is regulated to about a threshold voltage higher than VIN. In this manner, the comparator circuit controls the driver circuit and the control circuit, which in turn allow the boost converter to operate in a normal fashion even when VIN is higher than VOUT.

The invention discloses a high-voltage power supply high-selection circuit and a control method thereof, the high-voltage power supply high-selection circuit comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1-INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6, the floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS, two inputs of the high-voltage floating comparator circuit are respectively connected with input signals V1 and V2, and the high-voltage floating comparator circuit is connected with the high-voltage PMOS tube PDM5 and the high-voltage PMOS tube PDM6. The inverters INV1-INV4 generate two inverted signals A and B according to an output signal of the high-voltage floating comparator circuit, a high-voltage power supply end of the high-voltage floating comparator circuit, a source electrode of the high-voltage PMOS tube PDM5 and a source electrode of the high-voltage PMOS tube PDM6D are connected with a floating high voltage HVDD, and a low-voltage power supply end of the high-voltage floating comparator circuit is connected with a floating low voltage HVSS. According to the invention, the high-voltage power supply high-selection circuit is realized.

An integrated circuit includes a first multiplexer, a second multiplexing-input, a first clocked comparator, and a second clocked comparator. A first input node is connected to a first multiplexing-input of the first multiplexer, a first multiplexing-input of the second multiplexer, a first comparing-input of the first clocked comparator, and a first comparing-input of the second clocked comparator. A second input node is connected to a second multiplexing-input of the first multiplexer and a second multiplexing-input of the second multiplexer. An output of the first multiplexer is connected to second comparing-input of the first clocked comparator, and an output of the second multiplexer is connected to a second comparing-input of the second clocked comparator. The integrated circuit also includes an offset control circuit connected to a comparator-output of the first clocked comparator and a comparator-output of the second clocked comparator.

The invention discloses an electronic device and a voltage leakage circuit, the electronic device comprises a control circuit and a power circuit, the control circuit is connected with the power circuit and is used for controlling the power circuit to perform leakage or stop leakage, and the control circuit comprises a voltage division circuit; the comparison circuit is connected with the voltage division circuit and is used for receiving the first voltage from the voltage division circuit and comparing the first voltage with a preset reference voltage; the driving circuit receives the first reference voltage, is connected with the comparison circuit and the power circuit, and is used for outputting the first reference voltage to the power circuit when the first voltage is greater than or equal to the reference voltage so as to control the power circuit to discharge; one end of the hysteresis circuit is connected with the power circuit, the other end of the hysteresis circuit is connected between the voltage division circuit and the comparison circuit, and the hysteresis circuit is used for increasing the first voltage when the driving circuit outputs the first reference voltage to the power circuit. The power circuit is controlled through the voltage division circuit, the comparison circuit and the driving circuit, the cost can be reduced, and the occupied space is small.

A demodulation circuit includes a slope detector circuit and a comparator circuit. The slope detector circuit is configured detect a change in the voltage and determine if the voltage rate of change meets or exceeds one of a rise threshold or a fall threshold. The comparator circuit is configured to set an upper limit and lower limit for rate of change, compare the voltage rate of change to the limits, determine that the voltage rate of change meets or exceeds the limits, if the voltage rate of change meets or exceeds the rising and falling rate of change limits, (v) set a lower limit for a falling rate of change, (vi) receive the voltage rate of change and determine that the voltage rate of change meets or exceeds the fall or rise threshold, if the voltage rate of change meets or exceeds the falling or rising rate of change.

An oscillator circuit, a corresponding radar sensor, a vehicle, and an operating method are disclosed. An oscillator includes a tunable resonant circuit having an inductor and a variable capacitor coupled between a first node and a second node, and a set of capacitors selectively coupled between the first node and the second node. An input control node receiving an input control signal is coupled to the variable capacitor and the set of capacitors. The tunable resonant circuit is tunable based on the input control signal. A biasing circuit biases the tunable resonant circuit to generate a variable frequency output signal between the first node and the second node. A voltage divider generates a set of different voltage thresholds, and a set of comparator circuits having hysteresis compares the input control signal with the set of different voltage thresholds to generate a set of control signals. The capacitors in the set of capacitors are selectively coupled between the first node and the second node according to the control signals in the set of control signals.

In disclosed embodiments, a voltage sensor of a computing device is configured to determine a voltage level of a supply voltage provided by a power supply to processor circuitry. Comparator circuitry may perform a comparison operation that compares the determined voltage level to a threshold. A temperature sensor may determine a temperature of at least a portion of processor circuitry. Power control circuitry may initiate a power management operation to adjust voltage margin based on a result of the comparison operation. Additionally, the power management circuitry may control the comparator circuitry to impose an offset on the comparison operation. The power control circuitry may determine a magnitude of the offset based on a pre-determined effect of the determined temperature on voltage margin parameters for at least a portion of the processor circuitry.

In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.

In a described example, a circuit includes a comparator circuit including an input, a first output, and a second output. An offset control circuit includes a first input, a second input, a first output, and a second output, in which the first input is coupled to the first output of the comparator circuit, the second input is coupled to the second output of the comparator circuit. A first delay circuit is coupled between the first input and the first output of the offset control circuit. A second delay circuit is coupled between the second input and the second output of the offset control circuit. An offset calibration circuit has a first input and a second input, in which the first input is coupled to the first output of the offset control circuit, the second input is coupled to the second output of the offset control circuit.

A voltage tester system / device for safety application in AC & DC electrical systems and method thereof. The system / device includes a voltage presence indicator (VPI) circuit including plurality of zener diodes, bi-directional current-limiter circuits, VPI-LEDs and an absence of voltage tester (AVT) circuit including plurality of comparator circuits, optocouplers, DC-DC converters, microcontroller, power-management circuit, battery, LEDs and diodes. The VPI circuit converts electrical energy potential between the lines in range of 3 to 3394 volts (phase to neutral) / 5.2 to 5879 volts (phase to phase) into electrical inputs that drives VPI-LEDs to produce light output. The AVT circuit helps in checking circuit wires intactness with their respective busbars and verify absence of hazardous voltage by providing positive indication with a GREEN-light when safe voltage level is attained at connected leads, and voltage is less than a preset threshold value.

A gate driver circuit includes a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on-state and an off-state; at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sense value representative of a voltage transient of the power switch; a comparator circuit configured to compare the sense value to a threshold, and further configured to generate a comparison result based on whether the sense value satisfies the threshold; and a short circuit detector configured to detect a short circuit event based on the on-state of the power switch being detected and based on the comparison result indicating that the sense value satisfies the threshold.

A current comparator comprising: a P-type metal oxide semiconductor field effect transistor, PMOS FET (614), and an N-type metal oxide semiconductor field effect transistor, NMOS FET (615). The source of the PMOS FET is connected to a first comparator input terminal (610). The source of the NMOS FET is connected to a second comparator input terminal (611). The drain of the PMOS FET is connected to a current-comparator-input-node (602). The drain of the NMOS FET is connected to the current-comparator-input-node. The gate of the PMOS FET is connected to a first bias-voltage-node (VP). The gate of the NMOS FET is connected to a second bias-voltage-node (VN). The current comparator also includes a bias circuit (613) that provides a bias voltage to each of the first and second bias-voltage-nodes, and a current-comparator-circuit (601). A current-comparator-circuit-input-terminal (602) is connected to the current-comparator-input-node in order to receive a difference-current-input signal (IIn), which is representative of the difference between a first current input signal and a second current input signal. The current-comparator-circuit is configured to provide a current comparator output signal (Vout) as a digital voltage signal based on the received difference-current-input signal.

An analog-to-digital converter (ADC) circuit includes a first comparator circuit, a second comparator circuit, and an interpolation circuit. The first comparator circuit includes a first input terminal to receive a first reference voltage signal and a second input terminal to receive an input voltage signal. The second comparator circuit includes a first input terminal to receive a second reference voltage signal and a second input terminal to receive the input voltage signal. The interpolation circuit includes a first input terminal coupled to a first output terminal of the first comparator and a second input terminal coupled to a first output terminal of the second comparator.

Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

The invention provides a wide dynamic range methane detection system based on synchronous accumulation and system reconstruction. The device is characterized by comprising a modulated laser (1), a gas absorption cell (2), a photoelectric detector (APD) (3), a variable gain trans-impedance amplifier (TIA) (4) based on a digital potentiometer, a dual-threshold voltage comparator circuit (5) and a microcontroller processing unit (6). The device can be used for large-dynamic-range real-time monitoring of the methane gas concentration, and the problem that a traditional TDLAS system is prone to saturation or limited in detection limit when the concentration span is large is effectively solved. The method can be widely applied to the fields of gas concentration detection, industrial safety control and the like.

The invention discloses an overvoltage protection circuit and method. The circuit comprises a sampling circuit, a current mirror circuit, a charging circuit and a comparator circuit, the sampling circuit is used for sampling the voltage of the voltage detection end to obtain a sampled voltage; the current mirror circuit is used for scaling down the sampling voltage and charging the charging circuit; and the comparator circuit is used for detecting the voltage of the charging circuit and sending an overvoltage protection signal when determining that the charging voltage is greater than a preset overvoltage protection threshold value. According to the overvoltage protection circuit, the current flowing through the first capacitor is scaled down through the current mirror by the current mirror circuit, then the second capacitor is charged by the scaled-down current, and when the voltage on the capacitor reaches the threshold value, overvoltage protection is triggered. The voltage sampling network is a capacitor and has no static power consumption. And the capacitor can be integrated into the chip, so that the system integration level can be effectively improved.

A switching regulator includes: a switching circuit that switches an input voltage based on a gate control signal, and outputs a switching voltage; a voltage difference detector that compares the switching voltage with a threshold value depending on the input voltage, and outputs a comparison result signal; and a control circuit that generates a gate control signal based on an output voltage to which the switching voltage is fed back after smoothed and the comparison result signal, and outputs the gate control signal to the switching circuit. The voltage difference detector includes: an integration circuit that generates a pseudo-output voltage obtained by integrating the switching voltage on time and substantially equal to the output voltage; and a comparator circuit that compares the pseudo-output voltage with a threshold value depending on a power supply voltage, and outputs the comparison result signal.

The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a high-precision low-power-consumption dynamic comparator circuit suitable for an SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The high-precision low-power-consumption dynamic comparator circuit is designed by adopting two-stage pre-amplification and a latch structure, a first-stage pre-amplification circuit A1 is a gain amplification stage, and a second-stage pre-amplification circuit A2 is a gain amplification stage; the effects of simplifying the circuit structure, reducing power consumption and eliminating kickback noise are achieved by adopting a dynamic operational amplifier of a cross-coupled load, the second-stage pre-amplification circuit A2 serves as an extra gain stage, an output signal from the first-stage pre-amplification circuit A1 can be quickly amplified by adopting a cross-coupled load structure, and the kickback noise is eliminated. The third-stage latch circuit A3 improves the speed of the comparator, the latch adopts a dynamic structure and is controlled by a dynamic clock, the latch does not work during resetting, and the static power consumption of the comparator is reduced.

A system for autonomous compliance with legal regulations in smart contracts; the system includes: a regulatory data collection unit comprising a network interface controller physically connected to an external communications port, a hardware-based public key infrastructure circuit configured to validate digital certificates of regulatory servers, and a direct memory access controller configured to transfer authenticated regulatory update packets from the network interface controller to a volatile buffer memory without processor intervention; a Compliance Code Conversion Unit with a hardware lexicon scanner implemented as a finite state machine and embedded in reconfigurable FPGA logic blocks, a microcontroller executing a hardware-based lexical analysis pipeline stored in firmware registers, and a translation cache memory configured to temporarily store tokenized compliance rules before writing them to a non-volatile instruction memory; a policy evaluation and enforcement unit comprising a transaction verification processor connected to a secure enclave memory, a hardware comparator circuit configured to compare transaction parameters with compliance thresholds stored in the secure enclave memory, and a logic gate circuit configured to generate execution gate signals that selectively allow, block, or modify smart contract execution signals transmitted to a blockchain execution processor; and an audit logging unit with a cryptographic hashing circuit configured to generate block hashes of enforcement records, a timestamp oscillator configured to generate temporal signatures of compliance enforcement actions, and a Merkle tree generation circuit configured to create tamper-proof hierarchical hash structures, with the enforcement records being passed to a decentralized storage interface for anchoring in the chain or distributed ledger.

Circuits and methods are provided that use a comparator circuit within a multi-level converter to identify a signal that controls access to a loop circuit. A loop circuit receives multiple signals requesting multiple currents from the loop circuit. A comparator within the loop circuit determines a control signal indicating one of the multiple signals that controls the loop circuit, where the one of the signals that controls the loop circuit is associated with a lowest current from multiple currents.

A continuity detector for determining the continuity of a Unit Under Test (UUT). The detector comprises a housing defining an interior volume, an electronics package disposed within the interior volume defined by the housing assembly, a first test contact and a second test contact to interface with the electrical wire or harness assembly, a precision resistance standard disposed within the housing and electrically coupled to the electronics package, and a power source disposed within the housing assembly. The first test contact and the second test contact are external to the interior volume. The first test contact and the second test contact are electrically coupled to the electronics package. The electronics package comprising a resistance measurement device and a comparator circuit. The comparator circuit is configured to determine if the resistance of the UUT is greater than, less than, or equal to the resistance of the resistance standard.

Laser circuits are disclosed herein that include, in one example, a proxy laser drive cell and a proxy comparator circuit for deriving a laser driver bias control using one or more constant current supplies. Comparator circuits are disclosed that are adapted to generate an output based on a proxy voltage having first and second voltage components wherein one of the voltage components is developed based on one or more constant current supplies indicative of laser control current.

The embodiment of the invention provides a hysteresis comparator circuit and a hysteresis comparator, the hysteresis comparator circuit comprises an open-loop operational amplifier circuit, the open-loop operational amplifier circuit is used for receiving a reference input and a comparison input, and determining a comparison output according to the reference input and the comparison input; the current feedback control circuit is connected with the open-loop operational amplifier circuit and used for controlling hysteresis current to be input to the open-loop operational amplifier circuit according to the comparison output, and the open-loop operational amplifier circuit feeds back and adjusts hysteresis voltage under the action of the hysteresis current; the bias voltage providing circuit is connected with the open-loop operational amplifier circuit and used for providing bias voltage for the open-loop operational amplifier circuit, and the bias voltage is used for controlling on-off of the open-loop operational amplifier circuit. The hysteresis comparator solves the technical problems that the hysteresis amount in the hysteresis comparator in the prior art is influenced by the power supply voltage and the hysteresis window is asymmetric.

A comparator circuit with dynamic hysteresis. A common source branch is configured to conduct a differential current at first and second intermediate outputs responsive to a differential input at first and second inputs, and a common gate branch is configured to generate a voltage at a third intermediate output responsive to the differential current at the first and second intermediate outputs. A hysteresis branch includes a hysteresis current generator including first and second replica transistors having source / drain paths coupled in parallel, and gates coupled to the first and second inputs, respectively. A hysteresis capacitor is coupled between the sources of the first and second replica transistors and the common terminal. Current mirror circuitry is coupled to the source / drain paths of the first and second replica transistors, to supply a hysteresis current responsive to the absence of current conducted by the parallel first and second replica transistors.

A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first and second switching devices are in parallel between the matching capacitor and a reference voltage. The comparator circuit further includes a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor an input voltage. The comparator circuit further includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further includes a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

Circuits and methods are provided that use a comparator circuit within a multi-level converter to identify a signal that controls access to a loop circuit. A loop circuit receives multiple signals requesting multiple currents from the loop circuit. A comparator within the loop circuit determines a control signal indicating one of the multiple signals that controls the loop circuit, where the one of the signals that controls the loop circuit is associated with a lowest current from multiple currents.

A neural network circuit is described that includes a first sample-and-hold circuit, a reference voltage generation circuit, a first comparator circuit, and a first output circuit. The first sample-and-hold circuit generates a first analog voltage based on a first output current output by a first neural network computation array. The reference voltage generation circuit generates a reference voltage based on a first control signal. The first comparator circuit is connected to the first sample-and-hold circuit and the reference voltage generation circuit, and outputs a first level signal based on the first analog voltage and the reference voltage. The first output circuit samples the first level signal based on a second control signal, and outputs a first computation result that meets the first computation precision.

The invention discloses a low-power-consumption column parallel monoclinic ADC (Analog to Digital Converter) circuit adopting a floating comparator circuit, a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor reading circuit and a CMOS image sensor. The low-power-consumption column parallel monoclinic ADC circuit adopting the floating comparator circuit comprises a floating comparator, an M-bit calculator, an M-bit latch and a parallel-serial conversion circuit which are connected in sequence, and the floating comparator is provided with a pixel signal input end and a ramp signal input end and is connected with a ramp generator through the ramp signal input end. According to the low-power-consumption column parallel monoclinic ADC circuit of the floating comparator circuit, the topological structure of a traditional floating comparator is improved, and an input overturning point of the comparator is kept on a set level; in the comparison stage of the monoclinic ADC, the voltage reduction amplitude of the floating capacitor is reduced, and it is ensured that the comparator is in a normal working state in the whole comparison stage.

This invention relates to the field of integrated circuit technology and discloses a three-stage positive feedback comparator circuit and electronic device based on fast timing. The circuit includes a first-stage positive feedback module, a second-stage triggering and clocking module, a second-stage positive feedback amplification module, and a third-stage positive feedback latching module. By employing a three-stage positive feedback structure, this invention places the corresponding differential signal nodes in the same feedback loop at each stage, significantly enhancing the comparator's amplification rate and metastability suppression capability. Furthermore, by introducing a fast timing control mechanism, the second-stage amplification, clock reset generation, and third-stage latching operations can be executed in parallel, effectively shortening the critical path delay and significantly improving the overall comparison speed. The electronic device includes the aforementioned comparator circuit. This invention effectively solves the bottlenecks of traditional comparators in terms of speed and reliability and is suitable for high-speed, high-precision data conversion systems.

The invention discloses a motor forward and reverse rotation driving circuit and system, and the circuit comprises a reference voltage supply circuit which is provided with a reference voltage output end; the first reference voltage providing circuit is provided with a first reference voltage output end; the reference voltage output end and the first reference voltage output end are respectively connected with the first comparator circuit; wherein the reference voltage is gradually changed from the first reference voltage to the second reference voltage, the first reference voltage is located between the first reference voltage and the second reference voltage, so that the reference voltage is smaller than the first reference voltage in a first time period and larger than the first reference voltage in a second time period, and the first time period and the second time period are not overlapped; and the first comparator circuit is connected with the motor driving circuit. When the motor rotates positively and negatively, a single chip microcomputer is not needed, the cost is reduced, software burning is not needed, and the process is simple during mass production.