59results about How to "Improve retention characteristics" patented technology

A liquid crystal display device includes pixels, gate lines and source lines, active elements, a gate driver circuit, a source driver circuit, and a timing controller circuit. The source driver circuit conducts a prescribed operation of supplying the source signals of positive polarity and negative polarity having a prescribed voltage to the source lines during a vertical blanking interval, and electrically cutting the source lines off after the supply of the source signals while establishing a short circuit between adjoining source lines supplied with the source signals of opposite polarities, thereby causing the source lines to hold a prescribed DC voltage value.

The invention relates to the technical field of semiconductor manufacture, in particular to a three-dimensional memory and a manufacture method thereof. The three-dimensional memory comprises a substrate, a tunneling layer, a plurality of charge capture layers and a plurality of charge barrier layers, wherein the substrate is provided with a stacking structure and channel holes which penetrate through the stacking structure along a direction vertical to the substrate, the stacking structure comprises interlayer insulation layers and grid electrode layers, and the interlayer insulation layers and the grid electrode layers are alternately stacked along a direction vertical to the substrate; the tunneling layer covers the inner wall surface of the channel holes; each charge capture layer is positioned between two adjacent interlayer insulation layers and is in contact with the tunneling layer; and each charge barrier layer is positioned between each grid electrode layer and each interlayer insulation layer as well as each charge capture layer and each grid electrode layer. By use of the three-dimensional memory, the migration of current carriers in the charge capture layers along a channel direction can be prevented, and the retention characteristics of the three-dimensional memory are improved.

The invention relates to an operation method for increasing a high-density multi-valued storage characteristic of a non-volatile flash memory. The operation method comprises the following steps of: (1), adjusting an initial state of a local captured type non-volatile flash storage unit to threshold voltage of minus 2V to minus 1 V at first: adjusting to the threshold voltage by adopting a bilateral belt-belt tunnelling hot hole injection (BBHH) erasing method; and then carrying out a transient FN operation so as to promote charges in a channel to be distributed uniformly; (2), repetitively carrying out the step (1) for many times, wherein the initial state is adjusted to the threshold voltage of minus 2V to minus 1 V through the bilateral BBHH and FN operation steps, and the fact that the threshold voltage in a channel region is same everywhere is finally realized; (3), taking the threshold as the multi-valued storage initial state, and carrying out a multi-valued unitary programming operation on an NOR type local captured storage unit; and (4), carrying out a -FN process for a short time at one time after achieving a programming state. The operation method disclosed by the invention is capable of increasing holding characteristic and tolerance characteristic of a storage device.

The invention relates to a TFT-LCD array substrate and a making method thereof. The array substrate comprises a gate line, a data line, a thin film transistor, a pixel electrode and a common electrode line, wherein the gate line, the data line and the thin film transistor are formed on the substrate, and the pixel electrode and the common electrode line form a storage capacitor, a pulse electrodeis arranged between the common electrode line and the pixel electrode and is used for enabling the storage capacitor to have a first capacitance value when the pixel electrode is started to be charged and enabling the storage capacitor to have a second capacitance value when pixel electrode charging is finished, and the first capacitance value is smaller than the second capacitance value. In the invention, because the pulse electrode is arranged between the common electrode line and the pixel electrode, on the one hand, the storage capacitor has the smaller capacitance value when pixel electrode charging is started so as to lower load of the thin film transistor and enhance the charging capability of the thin film transistor, and on the other hand, the storage capacitor has the larger capacitance value when pixel electrode charging is finished to strengthen the holding property of voltage of the pixel electrode and lower the leaping voltage of the pixel electrode at the moment that the thin film transistor is closed.

The invention relates to a method for improving properties of a non-volatile floating-gate organic thin film transistor type memorizer, and provides a non-volatile floating-gate organic thin film transistor type memorizer with a bottom-gate top contact structure. According to the non-volatile floating-gate organic thin film transistor type memorizer with the bottom-gate top contact structure, a charge storage layer adopts an organic insulation polymer film doped with quantum dot material; the quantum dot material is of a core-shell structure, and the highest occupied molecular orbital of the nuclear material is higher than that of a shell material, the lowest unoccupied molecular orbital of the nuclear material is lower than that of the shell material, a quantum well is formed between the nuclear material and the shell material, so that the captured electric charges are limited in the nuclear material, the electric charge capture ability of the charge storage layer is improved, and then the memory window of the non-volatile floating-gate organic thin film transistor type memorizer is increased, retention characteristics thereof are significantly improved. The provided method is simple, easy to operate, low in invested cost and enhances the memory property of the memorizer.

The invention discloses a multi-layer floating gate nonvolatile memory structure and a production method thereof, wherein the multi-layer floating gate nonvolatile memory structure comprises a silicon substrate, a silicon dioxide layer, a silicon nanocrystals / high temperature oxide multilayer structure, a polysilicon layer, a silicon dioxide layer, grid and source / drain region formed by sculpturing on the silicon substrate, and a side wall formed by sculpturing on the silicon dioxide layer. The invention solves the defects because the traditional Flash technology node can downsized, utilizes the multi-layer floating gate to storage charge to enhance a storage window, so that the reliability of the floating grid for storing charge can be increased and the retention performance of a floating device can be improved.

The invention provides a three-dimensional NAND type ferroelectric memory, a manufacturing method and an operation method; the three-dimensional NAND type ferroelectric memory takes the inherent electric field adjusting effect of a ring gate device into consideration, namely compared with a flat-plate laminated gate, in a ring gate dielectric laminated layer, the electric field is enhanced in thedielectric layer with small radius and the electric field is weakened in the dielectric layer with large radius; a ferroelectric layer is integrated on the small-radius inner ring of the ring gate, and a dielectric layer is integrated on the outer ring of the large radius, so that the electric field distribution is effectively adjusted, the electric field of the dielectric layer is reduced, and the electric field of the ferroelectric layer is enhanced, and therefore the reliability of the ferroelectric memory is effectively improved, namely, the storage window is enlarged, the durability of the device is improved, and the retention characteristic of the device is improved.

The invention relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, wherein a stacked structure is formed on the surface of the substrate; a channel hole penetrating through the stacked structure to the surface of the substrate; a functional sidewall covering the sidewall of the channel hole and including an electron barrier layer, anelectron capturing layer and a tunneling layer which are successively stacked from the sidewall of the channel hole to the inside of the channel hole; and a diffusion barrier layer between the electron barrier layer and the electron capturing layer and/or between the electron capturing layer and the tunneling layer. The semiconductor structure has high retention characteristics.

A non-volatile memory device including a metal-insulator transition (MIT) material is provided. The non-volatile memory device includes a gate stack having a tunneling layer, a charge trap layer, a blocking layer and a gate electrode formed on a substrate, wherein at least one of the tunneling layer and the blocking layer is formed of an MIT (metal-insulator transition) material.

The invention belongs to the technical field of antibiosis and disinfection of hygiene protection articles. The invention relates to a spray, and particularly discloses a long-acting antibacterial andvirus-killing hygienic protection article spray and application thereof. The formula of the spray comprises the following components in percentage by silver concentration: 0.01 to 1.0 percent of polyhexamethylene biguanide hydrochloride, 0.001 to 0.1 percent of nano-silver gel, 0.5 to 5 percent of quaternary ammonium salt, 0.0001 to 0.001 percent of melaleuca alternifolia oil, 2 to 15 percent oforganic silicon, 1 to 10 percent of propylene glycol and the balance of water. The spray for the protective articles is lasting in antibacterial effect, the spray is uniformly sprayed on the surfacesof the used sanitary protective articles until the sanitary protective articles are wet, and the sanitary protective articles can be reused after being dried. After the mask treated by the protectivearticle spray is washed with water for three times, the antibacterial rate is kept at 95% or above under the condition of keeping good air permeability.

The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

The invention discloses an erasure method for a memory unit. The erasure method is characterized by comprising the steps of S1, receiving a programming operation instruction; S2, selecting a memory unit, connecting a word line and a bit line of the selected memory unit to a first programming voltage, suspending a word line of an unselected memory unit, and connecting a bit line of the unselected memory unit to a voltage source; S3, applying a programming pulse to the selected memory unit; S4, applying an erasure voltage pulse to a well CWELL of the selected memory unit; and S5, performing programming verification, and if the verification succeeds, then ending the programming operation, otherwise, performing the step S2. According to the erasure method for the memory unit, provided by an embodiment of the invention, the erasure pulse is applied to the well of the memory unit after the memory unit is programmed each time, so that electrons captured on a surface layer of the memory unit can be erased and the data retention property of the memory unit can be enhanced.

The invention provides a manufacturing method of a three-dimensional memory. The method is used in a process of forming sacrificial layers. The top sacrificial layer has a first etching selection ratio A for the bottom sacrificial layer; the top sacrificial layer has a second etching selection ratio B for the middle sacrificial layer; A and B satisfy a relational expression that: A<= B<=1, and A is not equal to 1; and therefore, material components are changed in the deposition stage of the sacrificial layers; the etching rate of the sacrificial layers is changed in the process of removing thesacrificial layers by wet etching; the etching rate of the sacrificial layer on the lower layer is higher than that of the sacrificial layer on the upper layer; the difference of the etching rates can balance the difference of the etching rates of the lower sacrificial layer and the upper sacrificial layer caused by an etching load effect in the process; damage to part of a charge barrier layer in contact with the upper sacrificial layer is reduced; the problem of uneven damage of the charge barrier layer at the upper position and the lower position is effectively solved; and the step coverage capacity of the charge barrier layer at the upper position and the lower position is improved.

In an information processor including memory devices such as DRAMs and others, by reducing the power consumption of memory devices and efficiently repairing defect bits, a highly reliable information processor is realized. In an information processor including an external memory such as a DRAM, a second memory whose power consumption at the access time is smaller than that of the external memory is disposed, and cache data of the external memory and repair data are stored in this second memory. To an input address given from a central processing unit via a primary cache controller, a memory controller determines a hit or a miss with reference to a tag memory for cache and a tag memory for repair, and when one or both of tag memory for cache and a tag memory for repair are hit, it accesses the second memory.

The invention provides a 3D NAND memory device. A through channel hole is formed in a stacking layer on a substrate, a gate layer on a side wall of the channel hole is provided with a gap, the gap andan adjacent insulating layer form grooves, a storage function layer is formed in the groove and is positioned between an end surface of the gate layer and the channel layer, thus, storage units are connected through the channel layer, charge storage layers of the storage units are isolated by the insulating layers, so carriers are prevented from migrating along the channel direction, mutual influence among the storage units is reduced, and the retention characteristic of the storage device is improved.

Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.