Semiconductor storage

Abstract

The respective sources of drive transistors included in memory cells that are located in each of multiple columns and connected to a corresponding one of bit line pairs are connected commonly to a low voltage power supply VSS via an assertion transistor. When data is written, the assertion transistor for the memory cells connected to a selected one of the bit line pairs and located in the identical column is negated, so that the sources of the drive transistors in the memory cells in that column are allowed to float. Consequently, even with a low power supply voltage, it is possible to write the data into a single selected memory cell, while data in the unselected memory cells can be retained favorably.

Description

technical field [0001] The present invention relates to lower voltage and lower power consumption of semiconductor memories. Background technique [0002] Image 6 A conventional SRAM circuit is shown. This SRAM has a plurality of memory cells 1A to 1D arranged in an array. Since these memory cells have the same structure, the memory cell 1A will be described as an example. The memory cell 1A is composed of two load transistors MP1A, MP2A, two transfer transistors MN1A, MN2A, and two drive transistors MN3A, MN4A. The gates of the two transfer transistors MN1A, MN2A are connected to the word line WLn, and the drains are connected to the bit lines BITO, NBITO. The sources of the two load transistors MP1A and MP2A are connected to the high-voltage power supply VDD, and the sources of the two drive transistors MN3A and MN4A are connected to the low-voltage power supply VSS. Two latch circuits are formed by the load transistors MP1A, MP2A and the drive transistors MN3A, MN4A,...

AI Technical Summary

Problems solved by technology

[0013] But when Figure 8 In the conventional semiconductor memory shown in , for example, when the bit line pair BITO, NBITO is selected, and for example, when the word line WLn is selected, in the selected memory cell 1A, the transfer transistors MN1A, MN2A Turn on, use the source potential control signal SLn to make the sources of the driving transistors MN3A and MN4A into a floating state, and transmit the potential difference of the bit lines BITO and NBITO to the memory cell 1A to write data, but even in the same row In the non-selected memory cell 1C, since the transfer transistors MN1C and MN2C are also turned on, and the sources of the drive transistors MN3C and MN4C are also in a floating state, the data stored at the storage nodes DC and NDC of the non-selected memory cell 1C are also turned on. Possibility of being overwritten

Therefore, a plurality of memory cells 1A, 1C connected to the same word line (for example, WLn) cannot be selected by the column selectors 3A, 3B.

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