150results about How to "Reduce the risk of electric leakage" patented technology

The invention belongs to the field of welding materials, and particularly relates to a halogen-free, low-residue, high-impedance and cleaning-free flux, which comprises the following components: 2-15wt% of activator, 0.05-2wt% of dispersing agent, 0.5-4wt% of film-forming agent, 0.1-4wt% of additive and 75-97.35wt% of solvent. Compared with the prior art, the flux has the advantages that the expansion ratio of the flux is higher than 80% of the standard, the flux is moderate in weldability and halogen-free, ionic contamination is at the highest I grade, the flux is applicable to high-reliability electronic products, the surface insulation resistance of the flux is at a 1010 grade after a copper mirror corrosion test, and the flux has the advantages that the flux is high in insulation impedance, high in insulation resistance, low in electric leakage risk, low in solid content, environment-friendly, clean and cleaning-free, residue is less, a post-weld board is tack-free and the like.

The invention relates to a solar module and a preparation method thereof. The solar module comprises at least two battery packs in series connection; each battery pack comprises at least two cell trains in parallel connection; each cell train comprises at least two cell cutting blades in series connection, and connecting pieces used for installing adjacent cell cutting blades in series; the cell cutting blades are formed by cutting solar cells along an extending direction perpendicular to main grids. Each cell cutting blade possesses a cut end and an uncut end which are opposite, wherein the uncut end of the cell cutting blade is opposite to the cut end of an adjacent cell cutting blade, and a gap is left therebetween for the penetration of a connecting piece; one end of the connecting piece is in connection with the front surface electrode at the uncut end of the cell cutting blade, and the other end penetrates the gap to be in connection with the back electrode at the cut end of the adjacent cell cutting blade. The solar module reduces short circuit, thereby cuts electric leakage risks, and is in favor of application.

The invention discloses a method for manufacturing a high-performance double-layer polysilicon bipolar transistor. The method comprises the following steps that 1), LOCOS and CVD are adopted to deposit SiO2 to form a composite isolation structure, and high-temperature process time is reduced; 2), the SiO2 is used as an etching stopping layer of base polysilicon, and etching damage is avoided; 3), a composite side wall structure is formed through SiO2 and N+polysilicon, and emitter resistance is reduced. The method has the advantages that on the premise of not lowering the isolation effect, the high-temperature process time is reduced, therefore, a relatively thin epitaxial layer can be adopted, the better microwave performance is obtained, SiO2 is adopted as the etching stopping layer, the etching damage to the silicon epitaxial layer is eliminated, breakdown characteristics are improved, current amplifying coefficients are increased, and noise coefficients are reduced. The composite side wall structure with SiO2 and N+polysilicon is adopted, it can be guaranteed that emitter-base electric isolation is carried out, and meanwhile the emitter resistance is lowered, the current amplifying coefficients are increased, and the noise coefficients are reduced.

The invention provides an LED vertical chip structure and a manufacturing method thereof. The method comprises the following steps of S1, providing a sapphire substrate and growing an unintentionally-doped GaN layer, an N-type GaN layer, a multi-quantum well layer and a P-type GaN layer successively on the substrate; S2, forming several discrete P electrodes; S3, forming several discrete first bonding metal layers which cover the P electrodes; and providing a bonding substrate and forming several discrete second bonding metal layers on a surface of the bonding substrate; S4, carrying out alignment bonding on the first bonding metal layers and the second bonding metal layers; S5, removing the sapphire substrate; S6, removing the unintentionally-doped GaN layer, and using a dry method etching technology to form a cutting channel, wherein the cutting channel avoids an area where the bonding metal layers are located; and S7, forming an N electrode. In the invention, a graphical bonding structure (formed by several discrete bonding metal layers) is adopted so that a metal splashing problem generated when ICP etches the cutting channel is effectively avoided; and a chip electric leakage risk is reduced so that chip reliability is effectively increased.

The invention provides a power distribution cabinet which is easy to maintain, which includes a cabinet body, and evenly distributed accommodation boxes are fixedly installed on both sides of the inner wall of the cabinet, and a cover plate is hinged on one side of the accommodation box through a rotating shaft to accommodate The bottom of the inner cavity of the box is fixed with a slide rail, one side of the outer surface of the slide rail is slidably connected with a slider through a chute opened, one side of the slider is fixedly connected with a torsion spring, and the other side of the slider is welded with a first As for the connecting rod, one end of the first connecting rod is hinged to the second connecting rod through a rotating shaft, and one end of the first arc-shaped rod extends to the inside of the through groove. The easy-to-maintain power distribution cabinet, through the arrangement of the accommodation box, enables the wires and electrical appliances inside the cabinet to be placed in categories and fixedly installed. The opening of the plate makes it easier to open the cover plate, thereby facilitating the maintenance of the electrical appliances and electric wires inside the storage box.

The invention discloses a method of eliminating etching residues of emitting electrode polycrystalline silicon in duotriode type transistor technology. A base region germanium-silicon outer extension layer is developed. A layer of an oxidation film is developed on the base region germanium-silicon outer extension layer. The oxidation film and the germanium-silicon outer extension layer are etched through a drying method, thus a base electrode of the duotriode type transistor is formed. The oxidation film on the base electrode can be clearly eliminated by using the drying method. A medium film is deposited by the composition of the oxidation film and a nitride film. The medium film is etched, thus an emitting electrode window is formed. The emitting electrode polycrystalline silicon is deposited and an ion is injected. The emitting electrode is formed by etching. End surfaces on two sides of an outer base region polycrystalline silicon are filled by the medium layer forming the emitting electrode window, thus the residue on two sides of the base electrode polycrystalline silicon when the emitting electrode polycrystalline silicon is etched is prevented. The problem that the emitting electrode polycrystalline silicon is residued when the emitting electrode polycrystalline silicon is etched is solved, thus risks of leakage of the base electrode and a collecting electrode are solved. Distance between the base electrode polycrystalline silicon and a deep contacting hole is reduced and an integration level of a device is improved.

The action switch structure of refrigerator distributor includes water supply button set below water taking port and capable of sliding up and down, link rod linked with the water supply button to rotate with the vertical motion of the water supply button, and action switch capable of being turned on or off with the action of the link rod. The present invention avoids electric leakage of the action switch caused by the water from the distributor effectively owing to the link rod to separate the water taking button from the action switch by certain distance, and the preventing wall between the action switch and the water taking port.

The invention discloses an integrated circuit device and a manufacturing method thereof. The integrated circuit device comprises a plurality of stacked semiconductor devices; each semiconductor devicecomprises a substrate and a dielectric layer formed on the substrate, and the dielectric layers of two adjacent semiconductor devices are combined together in the stacking direction; a plurality of functional devices and a plurality of isolation structures are formed in the dielectric layer of at least one of the semiconductor devices, and the isolation structures are used for isolating the adjacent functional devices; each isolation structure comprises an isolation trench and a filler applied in the isolation trench, and an opening of the isolation trench is located in the surface, back on to the substrate, of the dielectric layer. According to the invention, the electric leakage risk and the capacitance coupling risk between the functional devices can be effectively reduced, and the reliability of metal interconnection on the hybrid bonding interface is effectively improved, so that the wafer bonding stability is improved.

The invention discloses a display device, display system and manufacturing method. The display device comprises a display panel and a chip on film, wherein the chip on film comprises a driving chip, afirst electrode array, a second electrode array and a plurality of leads, the driving chip is provided with a plurality of chip pins; a plurality of chip pins are respectively led out by electrodes in the first electrode array; a second electrode array is used for providing a plurality of signal channels between the driving chip and the display panel; and the plurality of leads are respectively used for connecting the effective pins in the plurality of chip pins to the corresponding signal channels, so that the effective pins are electrically connected with the corresponding driving terminalson the display panel, when the plurality of chip pins comprise at least one idle pin and at least one effective pin, the leads, the effective pins and the driving terminals are the same in number. The chip of the display device comprises at least one idle pin, and the wiring density of the lead is reduced, so that the short circuit and electric leakage risks of the display device caused by overlarge wiring density are reduced, and the problem of increased coupling capacitance is avoided.

The invention discloses a pixel defining layer and a manufacturing method thereof, a display panel and a manufacturing method thereof and a display device. The pixel defining layer comprises a first pixel defining layer arranged on a substrate; a second pixel defining layer located at the side of the first pixel defining layer away from the substrate, wherein the orthographic projection of the surface of the second pixel defining layer close to the substrate on the substrate covers the orthographic projection of the surface of the first pixel defining layer away from the substrate on the substrate, and the second pixel defining layer is made of hydrophobic material. Ink climbing on the pixel defining layer can be effectively suppressed, the electric leakage risk of the device layer of theorganic light emitting diode can be reduced and the film formation uniformity can be improved.

The invention provides a GOA circuit and a liquid crystal display device. A thin film transistor connected in a diode mode is added to a pull-up control circuit on the basis of a conventional GOA circuit, and a reverse signal with the phase, opposite to the signal connected to the pull-up control circuit, is connected, thereby enabling a drain electrode of a first thin film transistor of the pull-up control circuit to be connected with a high-potential DC signal. Therefore, there is no need of a new DC signal line. Accordingly, the GOA circuit achieves a purpose that the drain electrode of thefirst thin film transistor is connected with the high-potential DC signal through a conventional signal under the condition that a fan-out space of the GOA circuit is not increased, and can greatly reduce the electric leakage risk of an n-th-stage GOA unit node Q(n) at a potential maintaining stage, thereby improving the reliability of the GOA circuit, enabling the size of a frame not to be increased, and facilitating the implementation of the narrow-frame design of a display panel.

The invention relates to a method for forming a gate isolation groove of a three-dimensional storage device and a photomask used by the method. The method for forming the gate isolation groove of thethree-dimensional storage device comprises the following steps of providing a semiconductor structure, wherein the semiconductor structure comprises a lamination structure, and a channel hole array isarranged on the lamination structure; photoetching the semiconductor structure by using the photomask, wherein the photomask is provided with one or more lines for forming one or more gate isolationgrooves, and at least one of the lines is bent towards a center of the photomask; and etching the semiconductor structure to form one or more gate isolation grooves. By the method, the distance between the gate isolation groove and each channel hole in each line of channel holes adjacent to the gate isolation groove can be trend to be consistent, and an electric leakage risk of the three-dimensional storage device is reduced.

The invention is applicable for the technical field of a cable, and discloses a high-insulation cable with high flexibility and easy to bend. The high-insulation cable with high flexibility and easy to bend comprises a conductor, a high-insulation layer and a sheath, wherein the sheath comprises a low smoke zero halogen flame-retardant inner layer and a low smoke zero halogen flame-retardant outer layer, second protruding thorns are densely arranged on an external circumferential surface of the low smoke zero halogen flame-retardant inner layer and are internally embedded onto an internal circumferential surface of the low smoke zero halogen flame-retardant outer layer, the conductor is formed by twisting a single conductor line or a plurality of conductor lines and is coated in the high-insulation layer, and first protruding thorns are densely arranged on an external circumferential surface of the high-insulation layer and are internally embedded onto an internal circumferential surface of the low smoke zero halogen flame-retardant inner layer coated at the periphery of the high-insulation layer. The high-insulation cable with high flexibility and easy to bend is reasonable in structure, adjacent layers are highly engaged, the high-insulation cable with high flexibility and easy to bend still has relatively high bending and flexible performance in a low-temperature environment, is long in service life, and has a high insulation effect, and the risk of electric leakage is reduced.

The invention discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a substrate; an isolation layer covering the substrate; a laminated structure covering theisolation layer and comprising a plurality of gate conductor layers and interlayer insulating layers which are alternately stacked; and a plurality of channel columns penetrating through the laminated structure and the isolation layer, wherein the substrate is provided with a plurality of epitaxial parts, the channel columns are respectively in contact with the corresponding epitaxial parts and the gate conductor layers are separated from the epitaxial structures by the isolation layer at the epitaxial parts. The channel columns are in contact with the epitaxial parts acting as the epitaxialstructures to provide the selection transistor and the storage transistor of the 3D memory device with the laminated structure. Compared with the conventional process, the substrate is directly connected into the form of having the epitaxial parts to replace the scheme of forming the epitaxial structures in contact with the substrate at the bottom of the channel hole in the conventional process soas to avoid the problems of inconsistent height of the epitaxial structures in the deep hole, uneven surface and difficult control of ion doping concentration.

The invention discloses a red phosphorus flame-retardant reinforced nylon composite material and application thereof. The red phosphorus flame-retardant reinforced nylon composite material comprises the following components by weight: 35-55 parts of nylon resin, 3-20 parts of thermoplastic polyester, 5-20 parts of a red phosphorus flame retardant, and 10-45 parts of a reinforcing filler, wherein the thermoplastic polyester is selected from one or a combination of two of polyethylene terephthalate (PET) and polybutylene terephthalate (PBT). A certain amount of thermoplastic polyester is added into a red phosphorus flame-retardant reinforced nylon composite material system, so that the release amount of PH3 gas in the thermal forming processing process of the composite material, especially under the condition of relatively high thermal forming processing temperature, can be effectively reduced, the harm to the body health of personnel is reduced, and the use safety of the material is improved; and the composite material is suitable for the fields of connectors, socket connectors, circuit breakers, low-voltage switches and the like in electronic and electrical appliances.

The invention provides a manufacturing method of a three-dimensional memory. The method is used in a process of forming sacrificial layers. The top sacrificial layer has a first etching selection ratio A for the bottom sacrificial layer; the top sacrificial layer has a second etching selection ratio B for the middle sacrificial layer; A and B satisfy a relational expression that: A<= B<=1, and A is not equal to 1; and therefore, material components are changed in the deposition stage of the sacrificial layers; the etching rate of the sacrificial layers is changed in the process of removing thesacrificial layers by wet etching; the etching rate of the sacrificial layer on the lower layer is higher than that of the sacrificial layer on the upper layer; the difference of the etching rates can balance the difference of the etching rates of the lower sacrificial layer and the upper sacrificial layer caused by an etching load effect in the process; damage to part of a charge barrier layer in contact with the upper sacrificial layer is reduced; the problem of uneven damage of the charge barrier layer at the upper position and the lower position is effectively solved; and the step coverage capacity of the charge barrier layer at the upper position and the lower position is improved.

The invention discloses a novel cylindrical super capacitor. The capacitor possesses a shell. The shell is a structure with two open ends. An electrical core is arranged in the shell. An upper end opening of the shell is provided with a leading-out terminal. A lower end of the leading-out terminal is connected to an upper end of the electrical core. An insulation sealing gasket is arranged between an upper side surface of the leading-out terminal and the shell, and a sealing washer is arranged between a side portion of the leading-out terminal and an inner wall of the shell. A current collector is arranged in the leading-out terminal. A lower end of the current collector is welded with the electrical core through the current collector and an electrical core welding spot. A lower end opening of the shell is provided with an afflux leading-out terminal. The afflux leading-out terminal is welded with the electrical core through the current collector and the electrical core welding spot. The capacitor has advantages that the shell, the leading-out terminal, the electrical core and the afflux leading-out terminal are separated through the insulation sealing gasket or the sealing washer so that the shell is not charged completely, an electric leakage risk is reduced and a short circuit is not generated; two ends of the shell are connected so that installation and welding are convenient; and through the structure, die cost can be reduced.