445 results about "Surface electrode" patented technology

The invention relates to a three-dimensional spiral high-density neural electrode and a preparation method and application thereof. The three-dimensional spiral high-density neural electrode comprises a probe structure and a plurality of electrode sites. The probe structure is formed by curling a planar flexible electrode precursor, and at least one end of the probe structure is provided with a spiral outer surface of a three-dimensional spiral line structure. Electrode sites are distributed along a spiral path, have a size of 5-1000 [mu] m, and are used for contacting biological tissues. On the planar flexible electrode precursor, electrode sites are arranged on one or more straight lines forming an inclined angle alpha with the axial direction of the probe, and the spatial distribution is matched with the edge. Compared with the prior art, the method has the advantages that the constraint of a traditional wiring mode is broken through, the integration of high-density three-dimensional channels is realized under a micro size, and a new generation of solution is provided for a high-precision brain-computer interface, deep brain stimulation and a three-dimensional electroencephalogram.

The invention relates to the field of rehabilitation instruments, in particular to an intelligent pneumatic hand function rehabilitation training system which comprises a flexible exoskeleton glove provided with a pneumatic muscle array and used for assisting fingers of a user in grasping training. The fingertip position of the glove is connected with a magnetorheological damper through a flexible cable, and the magnetorheological damper is used for providing dynamic resistance in the training process. The electrical stimulation module is used for activating hand muscle groups in a targeted manner through a surface electrode and enhancing neuromuscular control; the sensor module is used for collecting physiological data of a user in real time; the physiological data comprises electromyographic signals and tissue blood oxygen saturation; the control unit is used for switching training modes, by means of the intelligent air pressure hand function rehabilitation training system, the training intensity can be matched with the real-time ability of a patient all the time, and the rehabilitation training effect is improved.

A method of manufacturing a semiconductor device includes: preparing semiconductor substrate having a front surface and a back surface opposite to each other, the semiconductor substrate being of a first conductivity type; forming a device structure in the semiconductor substrate, at the front surface; performing thermal oxidation to form a gate insulating film and depositing a polysilicon to form a plurality of gate electrodes; removing the polysilicon at the back surface of the semiconductor substrate while leaving an oxide film formed at the back surface and a side surface of the semiconductor substrate by the thermal oxidation; forming a surface electrode on the device structure; and forming a plating film on the surface electrode while continuing to leave the oxide film at the back surface and the side surface of the semiconductor substrate.

An acoustic wave device includes a piezoelectric layer including first and second major surfaces, an IDT electrode on one of the first and second major surfaces, and including electrode fingers arranged in an arrangement direction, and a support facing the second major surface, and including an acoustic reflection portion facing the second major surface. The electrode fingers include a first electrode finger at an outermost position in the arrangement direction and a second electrode finger adjacent thereto. A product of a width, height, and density of one of the first and second electrode fingers is greater than a product of a width, height, and density of a central electrode finger. When the thickness of the piezoelectric layer is denoted by d and a center-to-center distance between adjacent electrode fingers is denoted by p, d / p is less than or equal to about 0.5.

The present application provides a method for performance evaluation and structure optimization of a high-power semiconductor laser chip, and a system for performance evaluation. Wherein the method for performance evaluation of a high-power semiconductor laser chip comprises: setting a window in an N-surface electrode of a chip to be tested; maintaining the chip to be tested in an operating state, wherein spontaneous radiation is generated in an active area of a quantum well of the chip to be tested; imaging the spontaneous radiation at a position outside the chip to be tested; acquiring, by using a spectrometer outside the chip to be tested, a spectrum of the spontaneous radiation to obtain a two-dimensional distribution of temperature of the quantum well of the chip to be tested in the operating state; and acquiring, by using a CCD camera outside the chip to be tested, an image of the spontaneous radiation to obtain a two-dimensional distribution of carriers in the quantum well of the chip to be tested in the operating state. The method for performance evaluation and structure optimization of a high-power semiconductor laser chip provided by the present application can get the temperature distribution and the carrier concentration distribution of the chip to be tested in the operating state with a resolution that is freely adjustable, the operation is convenient and easy to implement, and the accuracy of evaluation results is effectively improved.

An acoustic wave device includes a piezoelectric layer with first and second major surfaces, an IDT electrode on at least one of the first and second major surfaces and including electrode fingers arranged in a predetermined direction, a support facing the second major surface and including an acoustic reflection portion on the second major surface side, and a load film in a region that, in plan view in a first direction, overlaps at least one end portion of the IDT electrode in the arrangement direction. The end portion includes a first electrode finger positioned outermost in the arrangement direction, and d / p is about 0.5 or less where d is a thickness of the piezoelectric layer and p is a center-to-center distance between adjacent ones of the electrode fingers.

A semiconductor light emitting device includes an edge-emitting element including emitters, a first front-surface electrode, a second front-surface electrode, first wires, and second wires. The emitters include a first emitter including a first element electrode, and a second emitter including a second element electrode. The first front-surface electrode is electrically connected to the first element electrode. The second front-surface electrode is electrically connected to the second element electrode. The first wires are electrically connecting the first element electrode to the first front-surface electrode. The second wires are electrically connecting the second element electrode to the second front-surface electrode. In plan view, a largest distance between adjacent ones of the second wires in the first direction is greater than a largest distance between adjacent ones of the first wires in the first direction.

A device and system for real-time visualization of the electrophysiologic activity of a brain, particularly at the cortical surface. The neural device can acquire, process, and display high-spatiotemporal-resolution electrophysiologic data in real-time across entire electrode arrays spanning many thousands of electrodes over identified anatomic regions. The system is compatible with thin-film cortical surface electrodes that record from neural tissues without damaging those tissues. The system can be used to guide diagnostic and therapeutic actions with high precision, and also provides the basis for a brain-computer interface.

A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

An acoustic wave device includes a piezoelectric layer including first and second main surfaces facing in a first direction, an IDT electrode on at least one of the first or second main surface and including electrode fingers arranged in an arrangement direction, a support facing the second main surface and including an acoustic reflection portion, and a protective film on at least one of the first or second main surface. In a region that overlaps, in plan view in the first direction, a first of the electrode fingers outermost in the arrangement direction, the protective film includes a surface of a first step where a side surface of the protective film is exposed in a direction intersecting an extending direction of the first electrode finger. When d is a thickness of the piezoelectric layer and p is a center-to-center distance between adjacent electrode fingers, d / p is about 0.5 or less.

The utility model relates to the technical field of photovoltaic cells, and discloses a selective passivation contact structure and a double-sided selective TOPCon cell. The selective passivation contact structure comprises a silicon wafer, the back surface of the silicon wafer is sequentially provided with a first tunneling oxide layer and first boron-doped polycrystalline silicon, and a back surface electrode contact region of the first boron-doped polycrystalline silicon is also provided with second boron-doped polycrystalline silicon; the thickness of the first boron-doped polycrystalline silicon is smaller than that of the second boron-doped polycrystalline silicon, the crystallization rate of the first boron-doped polycrystalline silicon is larger than that of the second boron-doped polycrystalline silicon, and the doping concentration of the first boron-doped polycrystalline silicon is larger than that of the second boron-doped polycrystalline silicon. The selective passivation contact structure can reduce parasitic absorption of light, reduce recombination and improve the passivation effect and the transverse transmission performance of carriers, so that the open-circuit voltage, the short-circuit current, the fill factor and the cell efficiency of the double-sided selective TOPCon cell can be further improved.

An acoustic wave device includes a piezoelectric layer including first and second main surfaces, an IDT electrode on one of the first and second main surfaces, and including electrode fingers, a support facing the second main surface, and including an acoustic reflection portion at a portion closer to the second main surface of the piezoelectric layer, and a load film extending over a region that overlaps, when viewed in plan in the first direction, at least electrode fingers from a fourth one of the electrode fingers from a first outer end in an arrangement direction to a fourth one of the electrode fingers from a second outer end in the arrangement direction. d / p is less than or equal to about 0.5 where d denotes a thickness of the piezoelectric layer, and p denotes a center-to-center distance between adjacent two of the electrode fingers.

The invention discloses a uterus electromyographic signal generation method based on a deep generative model, which comprises the following steps: 1, acquiring uterus electromyographic signals of the abdomen of a pregnant woman through a multi-channel surface electrode, and carrying out filtering, noise reduction and normalization preprocessing; 2, performing short-time Fourier transform on the preprocessed signal to obtain time-frequency representation, and decomposing the time-frequency representation into low-frequency and high-frequency components; 3, respectively establishing reconstruction processes of the low-frequency component and the high-frequency component, and obtaining discrete potential representation through training; 4, on the basis of an encoder and a decoder which are subjected to reconstruction training, modeling is conducted on the low-frequency discrete sequence and the high-frequency discrete sequence through a bidirectional Transform prior model, and potential space distribution of the low-frequency discrete sequence and the high-frequency discrete sequence is learned; and 5, in a generation stage, sampling through a priori model to obtain a token sequence, and generating a high-quality uterine myoelectricity signal after decoding and inverse short-time Fourier transform. The signal generated by the method has high authenticity and stability while maintaining the consistency of the time sequence characteristics and the frequency spectrum, and can be applied to uterine contraction monitoring and premature delivery risk prediction.

A semiconductor device includes a semiconductor substrate having a principal surface and a rear surface opposite to the principal surface, a main electrode formed on the principal surface of the semiconductor substrate, a gate electrode formed in the principal surface side of the semiconductor substrate, and a rear surface electrode formed on the rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a drift layer, a low resistance region formed in the rear surface side of the drift layer and being lower in resistance than the drift layer, a high resistance region formed in the rear surface side of the low resistance region and being higher in resistance than the drift layer, and a buffer layer formed in the rear surface side of the high resistance region and containing phosphorus, and the high resistance region is thicker than the low resistance region.

To provide an IGBT (Insulative Gate Bipolar Transistor) which can reduce turn-on power loss and perform screening of a gate insulator.SOLUTION: An insulative gate bipolar transistor comprises: a gate trench 7a which extends in a specified extension direction set in advance in a plane view; a first insulator film 8a which is arranged at a bottom face of the gate trench 7a and at least a part of lateral face; a bottom gate conductive component 9a which is embedded in the gate trench 7a through the first insulator film 8a; a first split insulator film 10a which is arranged on the bottom gate conductive component 9a; an upper gate conductive component 11a which is embedded in the gate trench 7a through the first split insulator film 10a; a gate surface electrode 16 which is overlapped with one end of the gate trench 7a in the extension direction; a first contact hole 13c which electrically connects the gate surface electrode 16 with the bottom gate conductive component 9a; and a second contact hole 13a which electrically connects the gate surface electrode 16 with the upper gate conductive component 11a.SELECTED DRAWING: Figure 1

Provided is a vertical type device including a semiconductor substrate having an upper surface and a lower surface, and a lower surface electrode provided over the entire lower surface of the semiconductor substrate, the lower surface electrode including copper. The lower surface electrode may have a lowermost layer exposed at a surface farthest from the lower surface of the semiconductor substrate, the lowermost layer may include copper, a ratio of copper in the lowermost layer may be 50 wt% or more and 90 wt% or less, and a thickness of the lowermost layer may be 0.2 [mu] m or more and 0.8 [mu] m or less.

The invention relates to a three-dimensional semiconductor pixel detector and a manufacturing method thereof. A pre-prepared array carrier provided with a plurality of detection cavities arranged in an array is obtained, the inner surfaces of the detection cavities are provided with conductive layers, each detection cavity is internally provided with a central electrode of a detection pixel, the central electrodes are not in contact with the inner surfaces of the detection cavities, and the conductive layers are used as surface electrodes of the detection pixels; preparing a detection medium of a detection pixel in each detection cavity of the array carrier by adopting a preset low-temperature growth mode to obtain a three-dimensional semiconductor pixel detector comprising the array carrier and the detection pixel in each detection cavity; a detection medium in the detection cavity is located between the central electrode and the conductive layer; in each detection cavity, the detection medium surrounds the central electrode, and the surface electrode surrounds the detection medium. And the collection time of carriers can be greatly shortened, so that the saturation counting rate, the energy resolution and other performances are improved, the process is simple, the cost is low, and the applicable material range is wider.

Provided are: a thin film type temperature sensor in which a heat-sensitive thin film is formed on a part of the front surface of a substrate, and which has good responsiveness, can also provide accurate temperature measurement, and is particularly suitable for application to surface-mounted devices; and a temperature sensing structure employing the same.　In the temperature sensor, a heat-sensitive thin film is formed on a part of the front surface of a substrate. The temperature sensor includes an electrode set, the set comprising a pair of front surface electrodes and a pair of rear surface electrodes that are formed respectively on the front surface and the rear surface of the substrate and that oppose one another across the substrate at the periphery of the heat-sensitive thin film, pass-through electrodes that electrically connect the front surface electrodes and the rear surface electrodes, and connecting electrodes that are formed on the front surface and that electrically connect the heat-sensitive thin film and the front surface electrodes, wherein the heat-sensitive thin film and the connecting electrodes are formed such that the heights thereof are equal to or less than the height of the front surface electrodes in a heat-sensitive portion region of the front surface including, on the inside of said region, at least the front surface electrodes, the heat-sensitive thin film, and the connecting electrodes. Furthermore, in the temperature sensing structure, the temperature sensor is interposed between a main substrate and an electronic component.

A semiconductor module comprises: a first frame connected to a bottom surface electrode of a first semiconductor chip and having a first terminal protruding from the semiconductor module; a second frame connected to a top surface electrode of a second semiconductor chip and having a second terminal protruding from the semiconductor module; a third frame connected to the top surface electrode of the first semiconductor chip and the bottom surface electrode of the second semiconductor chip, and having a third terminal protruding from the semiconductor module; and fourth and fifth terminals connected to gate electrodes of the first and second semiconductor chips and protruding from the semiconductor module.The semiconductor module comprises at least either first opposing sub-areas parallel to a current flow direction in the second and third frames or second opposing sub-areas parallel to the current flow direction in the first frame of one of the neighboring semiconductor chip groups and the second frame of the other of the neighboring semiconductor chip groups.

The invention discloses a pi-shaped chip high-voltage pulse attenuation network resistor and a manufacturing method thereof, and belongs to the technical field of electronic components. The network resistor structure comprises a ceramic substrate, a resistive layer, a resistive layer R1, a resistive layer R2, a resistive layer R3, a surface electrode, a back electrode, a side electrode, an electrode nickel-plated layer, an electrode lead-tin-plated layer, a glass protection layer and an epoxy resin layer. The manufacturing method comprises the following steps: printing a surface electrode on the upper surface of a ceramic substrate, printing a back electrode on the lower surface of the ceramic substrate, printing a resistive layer bridged on the surface electrode, printing protective glass on the resistive layer, carrying out laser resistance trimming on the resistive layer, printing an epoxy resin protective layer and a mark on the protective glass, and sputtering a metal layer on the end surface. And preparing an electrode nickel-plated layer and a lead-tin-plated layer on the end surface. The problems that in the prior art, overheat burnout is likely to occur, electrodes are likely to be eroded in a humid or sulfur-containing environment, and the manufacturing precision and stability are difficult to improve and control are solved. The resistor is widely applied to the technical field of attenuation network resistors.

The utility model relates to the technical field of high-voltage lamp strips, in particular to a waterproof connector device of a spliced high-voltage lamp strip, which comprises a first lamp strip, a second lamp strip, a plug, an electrode column, a sleeve, a jack and a connector mechanism, the plug is fixedly connected with one end of the first lamp strip, the electrode column is fixedly connected with the surface of the plug, and the sleeve is fixedly connected with one end of the second lamp strip. The jacks are formed in the surface of the sleeve, the electrode columns are matched with the jacks, the connector mechanisms are arranged on the surfaces of the first lamp strip and the second lamp strip, each connector mechanism comprises a connecting assembly, a sealing assembly and a flow guide assembly, each connecting assembly comprises a first elastic piece, the first elastic pieces are fixedly connected with the surface of the plug, and the surface of the plug is fixedly connected with a second elastic piece. According to the utility model, through the arrangement of the joint mechanism, the two groups of lamp strips can be stably connected and conveniently disassembled, meanwhile, multiple waterproof treatment is carried out on the connecting part, so that water is prevented from flowing to the connecting part of the electrode column and the jack to cause a fault, and the usability of equipment is effectively improved.

An auricular stimulation device having surface electrodes biased towards each other, and offset from one another, is provided. The stimulation device can be positioned about the ear of a patient with each of the electrodes overlaying auricular ear tissue containing innervation supplied by an auricular branch of the vagus nerve. The electrodes transcutaneously stimulate the auricular branch. Also provided is a method of treating a patient using the auricular stimulation device. The stimulation device can be used for treating patients with conditions such as high blood pressure, depression, high blood glucose level, and tinnitus. Also provided is a diagnostic and therapeutic system having the auricular stimulation device, a smart device and a monitoring device. The smart device controls the auricular stimulation device based on biomarker information received from the monitoring device; and on information related to the patient, such as age, musculoskeletal stability, etc.; and / or on user input.

A semiconductor module includes a laminate substrate including an insulating plate and first and second circuit boards on an upper surface of the insulating plate, the first semiconductor device on an upper surface of the first circuit board, a first main terminal, and a first metal wiring board that electrically connects the first semiconductor device to the first main terminal. The first metal wiring board has a first bonding section bonded to an upper surface electrode of the first semiconductor device, a second bonding section bonded to an upper surface of the second circuit board, a first coupling section that couples the first bonding section to the second bonding section, a first raised section that rises upward from an end portion of the second bonding section. The first raised section has an upper end that is electrically connected to the first main terminal.

A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.

A SiC semiconductor device is provided that can improve the detection accuracy of the main current value of the current sensing unit by suppressing the escape of heat from the current sensing unit to the wiring material bonded to the sensing side surface electrode. A semiconductor device (1) is provided, the semiconductor device (1) comprising: a SiC semiconductor substrate, a source portion (27) including a main current side unit cell (34), a current sensing unit (26) including a sensing side unit cell (40), a source side surface electrode (5) disposed above the source portion (27), and a sensing side surface electrode (6) disposed above the power sensing unit (26) and having a sensing side pad (15) bonded to a sensing side line, wherein the sensing side unit cell (40) is disposed at a position avoiding the direct lower portion of the sensing side pad (15).

The application is a urethral catheter with conductive structure, which comprises a flexible catheter, the flexible catheter enters the human bladder through the urethra, the outer surface of the flexible catheter is partially provided with a conductive structure, the conductive structure is arranged at the prostate part of the outer distal end of the flexible catheter to assist freezing and electric ablation, the flexible catheter is internally provided with a liquid guide channel and a liquid guide opening is arranged at the distal end of the flexible catheter, the urethral catheter has a temperature protection effect, a temperature protection channel is divided into a liquid inlet channel and a liquid outlet channel by an inner sleeve and an outer sleeve, a surface electrode on the outer wall of the inner sleeve is connected to the circuit of a host, and the conductive structure only conducts electricity and does not have an electrochemical reaction. The application is used for cooperating to complete electric effect or electric ablation diagnosis and treatment effect and freezing, radio frequency and microwave and other thermal ablation, can avoid cold and hot damage or electric damage to the urethra or the prostate, has a temperature adjusting function and a simple structure and is easy to adjust and control.

The application discloses a preparation method and structure for reducing the capacitance of a laser chip, and the method comprises the following steps: forming a passivated Pad layer on a P surface bonding area of a passivation layer of the chip, wherein the Pad layer is a medium layer with low adhesion to a gold layer; manufacturing a P surface electrode on the chip, and part of the P surface electrode is located on the Pad layer; based on the low adhesion between the passivated Pad layer and the gold layer, when a gold wire is bonded with the P surface electrode, the gold wire pulls up the part of the P surface electrode located on the Pad layer, and the gold wire and the P surface electrode remain connected. By filling a medium layer with low adhesion to the gold layer in the P surface electrode bonding area, the P electrode layer is pulled up when the gold wire is bonded through the bonding process, which is equivalent to greatly reducing the metal area of the P surface electrode, so that the capacitance of the chip electrode is greatly reduced.

The inductance structure comprises a magnet and a coil arranged in the magnet, a first folding pin and a second folding pin are formed at the two ends of the coil respectively, and each of the first folding pin and the second folding pin comprises a bottom face part and a side face part. The bottom surface parts of the first folding pin and the second folding pin are exposed out of the magnet and are flush with the bottom surface of the magnet to serve as bottom surface electrodes, and the side surface parts of the first folding pin and the second folding pin are exposed out of the magnet and are flush with the side surface of the magnet to serve as side surface electrodes. According to the embodiment, the welding effect of the inductor can be visually checked through the side electrodes, and the welding strength can be further improved due to the fact that the contact area of the inductor and the PCB is larger.

The embodiment of the present disclosure relates to the photovoltaic field, and provides a solar cell and a photovoltaic module, wherein the solar cell comprises a substrate, a doped conductive layer located on one side of the substrate, a passivation layer covering the surface of the doped conductive layer away from the substrate, and an electrode comprising a plurality of bottom electrodes arranged at intervals along a first direction, the bottom electrodes being electrically connected with the doped conductive layer, and a top electrode extending along the first direction, the top electrode covering the surface of the bottom electrode, and the surface of the top electrode away from the substrate being wavy, and comprising at least one wave crest and at least one wave trough, the wave trough of the top electrode being opposite to at least one bottom electrode, and the wave crest of the top electrode being opposite to at least one bottom electrode at intervals. The cost can be reduced while ensuring the performance of the cell.

1. Name of the product in this design: Body of a surface electrode. 2. Purpose of this design: The body surface electrode and its main body are used in conjunction with a nerve and muscle stimulator to stimulate the vagus nerve in the ear. 3. The key design features of this product are the shape of the main body of the surface electrode. 4. The picture or photo that best illustrates the key design points: Design 1 3D diagram 1. 5. Design 1 is designated as the basic design. 6. Other situations requiring explanation: Other explanation: The dotted lines in the figure indicate the parts of this design that are not claimed.