The application discloses an FPGA double-output
lookup table mapping method based on iterative
pairing selection, which comprises the following steps: introducing a
pairing flow mechanism in the iterative mapping process based on
cut sets, evaluating the
interconnection and the
pairing ability between candidate cuts on line in the
cut selection stage, and sorting and selecting the cuts by using the pairing flow
score in the tolerance window; after the
cut is determined, a weighted pairing graph is constructed, global pairing is carried out through conflict-aware graph matching, and a double-output LUT is formed; and the pairing awareness is integrated into each round of the multi-round iterative mapping, compared with the existing method of decoupling mapping and packing, more high-quality pairing cuts can be found, and better effects can be achieved in area and depth.