FPGA dual-output lookup table mapping method based on iterative pairing selection

Abstract

The application discloses an FPGA double-output lookup table mapping method based on iterative pairing selection, which comprises the following steps: introducing a pairing flow mechanism in the iterative mapping process based on cut sets, evaluating the interconnection and the pairing ability between candidate cuts on line in the cut selection stage, and sorting and selecting the cuts by using the pairing flow score in the tolerance window; after the cut is determined, a weighted pairing graph is constructed, global pairing is carried out through conflict-aware graph matching, and a double-output LUT is formed; and the pairing awareness is integrated into each round of the multi-round iterative mapping, compared with the existing method of decoupling mapping and packing, more high-quality pairing cuts can be found, and better effects can be achieved in area and depth.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation (EDA) technology, and more specifically to an FPGA dual-output lookup table mapping method based on iterative pairing selection. Background Technology

[0002] Traditional single-output LUT mapping methods based on cuts, represented by FlowMap and DAOmap, and further refined in open-source tools like ABC, enumerate feasible k-input cuts for each node in the Boolean network, and select a representative cut for each node based on single-output objectives such as depth, area flow, and edge flow, thus obtaining the LUT mapping for the entire network. Here, a cut is defined as a subset of leaf nodes of a node such that any path from the main input to that node passes through at least one leaf node in the subset; area flow and edge flow approximate global resource occupancy through fan-out propagation. The utilization of dual-output LUTs is usually handled in a "packaging" phase after mapping, such as WireMap-style edge recovery and splittable LUT minimization processes. Their common characteristic is that they can only attempt to merge already selected cuts, and cannot replace them with other candidate cuts during the packaging phase. Once the representative cut for each node is determined during the mapping phase, these back-end processes cannot improve input sharing by replacing alternative cuts. As a result, many dual-output opportunities that could have been achieved by selecting cuts that are slightly worse than the optimal single-output metrics but have better pairability are permanently lost, leading to a poor trade-off between area and logic depth. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to provide an FPGA dual-output lookup table mapping method based on iterative pairing selection. In the iterative process of cut selection, a pairing flow (PF) mechanism is introduced, so that the selected cut has good pairability while satisfying the traditional depth / area main objectives. Global dual-output pairing is obtained through conflict-aware graph matching, thereby outperforming the decoupled mapping-packaging process in terms of both area and logic depth, without destroying the stability of the original ABC style iterative mapping.

[0004] Technical solution: The FPGA dual-output lookup table mapping method based on iterative pairing selection described in this invention includes the following steps:

[0005] Step 1: Enumerate feasible cuts for each node in the Boolean network and generate a set containing multiple candidate cuts for each node;

[0006] Step 2: For each node, perform preliminary screening from its candidate cut set based on the single output optimization objective, define a tolerance window that is close to the optimal cut in terms of performance indicators, and determine the cuts within the window as candidate cuts;

[0007] Step 3: For each cut in the set of candidate cuts, evaluate the probability of forming a valid double-output pair with neighboring nodes in the network in the future, and weight and aggregate the pairing probability evaluation values ​​of multiple key neighboring nodes to generate a pairing flow score.

[0008] Step 4: Within the tolerance window, use the paired flow score as an auxiliary decision-making criterion when single output targets are similar, and select a representative cut for each node;

[0009] Step 5: After obtaining the representative cuts of all nodes, check whether any node pair and its corresponding representative cut satisfy the physical constraint of sharing the same double-output lookup table. The constraint includes that the total number of inputs after merging the two cuts does not exceed the maximum allowed number of inputs of the double-output lookup table, and that there is a shared input between the two cuts. All node pairs that satisfy the physical constraints are regarded as candidate pairs, and a weighted pairing relationship graph is constructed using the original pairing score that measures the quality of the pairing as the weight.

[0010] Step 6: Perform conflict-aware graph matching on the weighted pairing graph, select non-conflicting node pairs in descending order of pairing quality to form the final global dual-output pairing set; map nodes belonging to the same pairing to the same dual-output lookup table hardware unit.

[0011] Furthermore, in step 1, the tolerance window refers to a preset small percentage range within which the cost of the candidate cut is allowed to deviate from the current optimal cut cost in terms of single output cost, so as to leave room for optimization in pairing selection without significantly sacrificing single output performance.

[0012] Furthermore, in step 3, when evaluating the pairing probability between a candidate cut and its neighboring nodes, multiple candidate cuts of the neighboring nodes themselves are collected, and the original pairing flow scores of the current candidate cut and each candidate cut of the neighboring nodes are summed with probability weights to quantify the pairing probability with the neighboring nodes whose final cut has not been determined in the form of expected value.

[0013] Furthermore, in step 3, the original paired flow score is determined by the scale of the shared input between the two cuts and the difference in the depth of the two nodes at the logical level. The more shared input and the closer the logical depth, the higher the score, as shown in the following formula:

[0014]

[0015] in The shared input number for the two cuts. The maximum number of valid inputs allowed for the target dual-output LUT. The difference in logical depth between the two nodes. This represents the penalty coefficient for deep mismatch.

[0016] Furthermore, in step 3, when generating the pairing stream score, a preset number of neighboring nodes with the highest expected pairing score are selected to participate in the calculation, and weight coefficients are assigned in decreasing order according to the ranking, so that the neighboring nodes with the highest pairing probability contribute the most to the final score.

[0017] Furthermore, in step 6, the conflict-aware graph matching process specifically includes: sorting all candidate pairing edges according to their weight values ​​from high to low; sequentially traversing the sorted edges, and whenever an edge is encountered where neither of its two endpoints has been selected by another better pairing, confirming the pairing relationship and locking the two nodes; continuing this process until all edges have been traversed to ensure that each node is assigned to at most one double-output lookup table.

[0018] Furthermore, the iterative mapping includes sequentially executed time-delay guided mapping, multi-round area flow guided mapping and multi-round area guided mapping, with each round executing steps (1)-(6).

[0019] Furthermore, when enumerating feasible cuts, the computational complexity of enumeration and storage is controlled to a range that grows linearly with the network size by setting a maximum input limit for a single-output lookup table, applying a dominance pruning strategy, and limiting the upper limit of the number of candidate cuts retained by each node.

[0020] An electronic device according to the present invention includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the program to implement the steps of any of the methods described herein.

[0021] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described herein.

[0022] Beneficial Effects: Compared with existing technologies, this invention has the following significant advantages: This invention embeds the pairing flow mechanism and conflict-aware graph matching into an ABC-style multi-round cut optimization process. Without disrupting the original depth / area primary objective, it guides cut selection using PF only within a tolerance window, thereby selecting representative cuts that satisfy both the primary objective and facilitate pairing. Finally, global graph matching determines the final dual-output pairing. Compared with the decoupled "mapping before packaging" method, this invention considers pairability during the mapping stage, enabling the discovery of more high-quality pairing opportunities. Attached Figure Description

[0023] Figure 1This is a schematic diagram of the dual-output LUT architecture and constraints of the present invention. The diagram shows two logic functions u and v and their input sets; when both are mapped to the same dual-output LUT, it contains two sub-LUTs, sharing inputs and connecting to the two sub-LUTs, and unique inputs are connected to their respective sub-LUTs; the correspondence between the total number of different inputs, the number of shared inputs and parameters I_dual, I_shared, etc. is also marked.

[0024] Figure 2 This is a schematic diagram of the PF-guided cut selection and conflict-aware graph matching process of the present invention. The left side of the figure shows the base graph structure of the Boolean network or cut; the upper right shows the process of using PF to select cuts when the main objectives such as depth, area, and edges are within the ε tolerance range; the lower right shows the process of constructing a pairing graph from representative cuts and performing graph matching according to edge weights to obtain the final pairing set.

[0025] Figure 3 This is a schematic diagram of the ABC-based mapping process of the present invention; the diagram shows the four-stage process of the input circuit through time-delay guided mapping, iterative area flow guided mapping, iterative area guided mapping, and final graph matching and pairing; each stage includes cut enumeration, cut selection, PF score calculation and graph matching and pairing. Detailed Implementation

[0026] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0027] like Figure 3 As shown, this embodiment of the invention provides an FPGA dual-output lookup table mapping method based on iterative pairing selection, including the following steps:

[0028] (1) A unified abstract parameter is used to describe the dual-output LUT: This is the maximum number of inputs available for a single output in single-output mode (e.g., 6). This represents the maximum number of inputs to the dual-output lookup table in dual-output mode. This represents the maximum number of inputs that can be shared between the two output channels in dual-output mode. This represents the maximum number of independent inputs per channel in dual-output mode. Typical parameter examples are as follows: For series, ;for series, Appendix Figure 1 The input partitioning of the two sub-LUTs can be shown.

[0029] (2) Feasible cut enumeration: On the Boolean network, feasible input cuts k are enumerated for each node in topological order, forming a candidate cut set for each node. The leaf set of cut c under node v is denoted as The feasibility of cutting is satisfied: ,in Maximum number of inputs for a single-output LUT (and) Consistent, usually =6). Cut enumeration adopts an expansion method starting from the pre-eviction level of nodes, and applies dominance pruning and size control rules; at the same time, the upper limit of the number of cuts retained in each node is set to a constant P, thereby reducing the cut enumeration and storage complexity from Reduced to .

[0030] (3) Tolerance Window and Candidate Cut Set: For each node, first sort the candidate cuts lexicographically by single output metric (depth, area, edge, etc.), and only retain those whose single output cost falls within " The cuts within the range of '' constitute the candidate cut set for that node; where Tolerance ratio, 5% is used in practice. That is, the cut set to be selected is composed of those satisfying " "All the cuts make up the whole" This represents the cost corresponding to the current optimal cut.

[0031] (4) Leaf set representation of cuts and double-output valid constraints: Each cut is represented by its leaf set. For two selected cuts (v, cv) and (u, cu), the union size and intersection size of the leaf sets of the two cuts are defined as follows: , The valid constraint for dual outputs is: and ;in The maximum number of valid inputs allowed for the target dual-output LUT. The total number of inputs after merging must not exceed [a certain limit]. Furthermore, both cuts must share at least one input.

[0032] (5) Original pairing score: for two specific cuts and The original pairing score is defined as

[0033]

[0034] in The shared input number for the two cuts. The difference in logical depth between the two nodes. They are nodes Logical depth This is the deep mismatch penalty coefficient (which can be set to 1).

[0035] (6) Expected pairing score: Since the final cut of the neighbor node u has not yet been determined in the iteration, the current cut With nodes Expected pairing score by Each candidate cut The pairing scores are obtained by summing them using probability weighting:

[0036]

[0037] probability The cut is obtained by normalizing the candidate cut's scores on metrics such as depth, area, and edge using negative exponential scaling:

[0038]

[0039] in is the normalized regular score of cut cu, and β is the scaling parameter (which can be 2 to 6) used to represent the soft preference of node u in selecting cut cu.

[0040] (7) Pairing Flow (PF) Score and Aggregation: For a candidate cut c of the current node, first calculate its expected pairing score with all its neighbors, sort the neighbors in descending order of the score, and take the top M neighbors. (M defaults to 4), which means that the following conditions are met:

[0041]

[0042] Assign decreasing weights to the first M neighbors:

[0043]

[0044] Where ρ∈(0,1) is the attenuation ratio (e.g., 0.85). The paired flow score of this candidate cut is defined as follows:

[0045]

[0046] In the set of candidate cuts, the PF score is used as an auxiliary sorting criterion when the primary objectives are similar, and the representative cut of the node is selected.

[0047] like Figure 2 As shown, global pairing and conflict-aware graph matching: After obtaining the representative cuts of all nodes, check whether each pair of nodes' representative cuts satisfies the double-output valid constraint; calculate the original pairing score for node pairs that satisfy the constraint, and construct a weighted graph with nodes as vertices and the original pairing scores of valid pairings as edge weights. Process edges in descending order of edge weight: If neither of the two nodes of an edge is matched, add the pair to the pairing set and mark both ends as matched. This yields the global double-output LUT pairing set.

[0048] (9) Multi-round iterative process: The overall mapping process includes delay-guided mapping, multi-round area flow-guided mapping and multi-round area-guided mapping. In each round, feasible cut enumeration, candidate cut set construction, PF score calculation and cut selection are performed, as well as (when the final mapping needs to be output) global graph matching and pairing based on the current representative cut.

[0049] Wherein: Dual-output LUT constraints: Two logic functions (corresponding to nodes v and u, whose selected cuts are respectively) and A variable can be mapped to the same physical dual-output LUT if and only if the following constraints are satisfied. Represents a node In cutting The leaf set below (the set of leaf nodes contained in the cut). Represents a node In cutting The leaf collection below.

[0050] .

[0051] in The union of two leaf sets contains the number of nodes, i.e., the number of nodes. The cut Leaf sets and nodes The cut The size of the set after taking the union of the leaf sets. This value represents the size of the set if the leaf sets are... The total number of different inputs required when mapping to the same dual-output LUT and merging the two functions.

[0052] .

[0053] in This represents the number of nodes contained in the intersection of two leaf sets, i.e., the size of the intersection of the two leaf sets. This value also represents the number of inputs that the two functions can share. The larger the value, the more shared inputs there are, and the more suitable it is to be merged into the same dual-output LUT.

[0054] The valid constraint for dual outputs is:

[0055] .

[0056] This formula states that the total number of distinct inputs after merging must not exceed the maximum number of valid inputs allowed by the target dual-output LUT. Otherwise, it cannot be implemented within a single physical dual-output LUT.

[0057] .

[0058] This indicates that the two cuts share at least one input; if they do not share any input, the input sharing capability of the dual-output LUT cannot be utilized, and therefore it is not considered a valid pairing.

[0059] Definition of Boolean Networks and Cuts: A Boolean network consists of nodes and directed edges. Nodes represent logical operations, and edges represent signal dependencies. The main input and constants are considered leaf nodes without predecessors. For a node v, a cut c is a set of leaf nodes in several predecessor directions of v, satisfying that any path from the main input to v passes through at least one node in this set; this set is called the leaf set of cut c under node v, denoted as L(v,c), and its size |L(v,c)| is called the size of the cut. The set of candidate cuts for node v is denoted as C(v).

[0060] Feasibility conditions for cutting:

[0061]

[0062] Where K is the maximum number of inputs to a single-output LUT (usually...). ,and (Consistent). This formula indicates that the size of the cut must not exceed the number of inputs that a single-output LUT can accommodate, which is a necessary condition for the cut to be feasible; otherwise, the cut cannot be implemented with a single-output LUT.

[0063] The specific process of enumerating feasible cuts is as follows:

[0064] (1) Traverse each node in the Boolean network in topological order to ensure that the cut of its predecessor node has been generated when processing a certain node.

[0065] (2) For the current node v, starting from the cut of its direct predecessor node, generate candidate cuts of v through incremental signal expansion and satisfy the constraints.

[0066] (3) Apply dominance pruning: If the leaf set of cut c is a proper subset of the leaf set of cut c', then retain c and discard c' to ensure that the cuts retained in C(v) are representative cuts that do not dominate each other.

[0067] (4) Each node v retains at most P cuts (P is a constant, corresponding to the "-C" parameter of ABC), thus reducing the cut enumeration and storage complexity from Reduced to , where N is the number of nodes in the Boolean network and K is the maximum cut size.

[0068] (5) The obtained candidate cut set C(v) for each node is used for subsequent cut selection and PF calculation.

[0069] Construction of Single-Output Metrics and Candidate Cut Sets: For the candidate cut set C(v) of node v, first sort it lexicographically by single-output objective (depth, area, edge, etc.). Imposing a tolerance range: Only retain cuts where the single-output cost falls within the range of " The cuts within the specified range constitute the candidate cut set for that node. That is, the candidate cut set consists of the cuts that satisfy the condition "". " is composed of all the cuts, in which The cost corresponding to the current optimal cut. This is set as the tolerance threshold (5% in practice). This ensures that cuts within the candidate cut set are close to the optimal cut on the primary objective, allowing for the introduction of pairing flows within the tolerance window. It provides a safe range as an auxiliary sorting criterion.

[0070] Leaf set representation and dual-output validity determination and original pairing score: cut At the node The corresponding leaf collection is as follows For two selected cuts The condition for a dual-output is and .

[0071] Original pairing score: for two specific cuts ,definition for:

[0072]

[0073] in The shared input number for the two cuts. The maximum number of valid inputs allowed for the target dual-output LUT; The difference in logical depth between the two nodes. They are nodes Logical depth; This is the penalty coefficient for deep mismatch (in practice, it is taken as 1). The closer the depth, the higher the score, encouraging pairing within the same or nearby layers.

[0074] Expected pairing score and pairing flow PF: Since the neighbor node u has not yet determined the final cut in the iteration, it may choose any cut from the candidate cuts. Current cut The expected pairing score with node u is obtained by... The pairing scores of each candidate cut are obtained by summing them by probability weights:

[0075]

[0076] The summation traversal candidate cut set Each cut in ; For nodes Select cut The probability is used to quantify the expected value of "pairability with neighbor u" when the cut is not fully determined.

[0077] probability The node is obtained by normalizing the candidate cut's scores on metrics such as depth, area, and edge using negative exponential scaling. Select cut Soft preference:

[0078]

[0079] in For cutting Normalized scores on conventional metrics such as depth, area, and edge (used only for formation probability); The scaling parameter controls the steepness of the probability distribution; in practice, it is typically set between 2 and 6. The denominator is the sum of the slopes of the probability distribution. All cuts Summing the results ensures that the sum of probabilities equals 1.

[0080] The calculation process and formula for Paired Flow (PF) score: for nodes Each candidate cut in the candidate cut set (1) Calculate its relationship with Each neighbor Expected pairing score (2) All neighbors Sort in descending order, take the first M neighbors, and denote them as... :

[0081] The default value is 4. (3) For the previous Each neighbor is assigned a decreasing weight:

[0082]

[0083] in For example, the attenuation ratio The weights decrease and normalize with ranking, making higher-ranked neighbors contribute more to PF. (4) This candidate cut The pairing stream score is defined as:

[0084]

[0085] In the selection set, with As an auxiliary sorting criterion (or tie-breaker) when primary objectives (depth, area, etc.) are similar, a representative cut for node v is selected; if the primary objective can uniquely determine the optimal cut, then This can serve as a basis for breaking a draw.

[0086] Global Pairing Algorithm: After obtaining the representative cuts of all nodes, global pairing is performed according to the following process. The algorithm constructs a weighted graph with nodes as vertices, valid pairings as edges, and the original pairing scores as edge weights. Then, it greedily matches the edges in descending order of edge weights to obtain a conflict-aware pairing set.

[0087] Input: Set of mapped nodes Representative cuts of each node , .

[0088] Output: Set of pairs Each element is a pair of nodes, indicating that the pair maps to the same double output. .

[0089] Step 1: Initialize the edge set EH to be empty.

[0090] Step 2: For each pair of nodes ,make .like Satisfy the dual-output valid constraint ( ), then calculate (Right now ).like Then the edge and border rights join in .

[0091] Step 3: Construct the graph In the graph, vertices are mapped nodes, edges represent valid pairing candidates, and edge weights are the original pairing scores.

[0092] Step 4: If If empty, return an empty set of pairs. .

[0093] Step 5: The edges are sorted from highest to lowest weight.

[0094] Step 6: Initialize all nodes Matching status .

[0095] Step 7: Let Traverse each edge in sorted order. :like and Then join in and order Otherwise, skip that edge. This greedy strategy ensures that edges with higher weights are selected first, while avoiding duplicate pairing of the same node (conflict awareness).

[0096] Step 8: Return .

[0097] Each pair of nodes in the LUT corresponds to a dual-output LUT; those not appearing in the LUT... The nodes in the LUT still exist in the form of a single-output LUT.

[0098] Multi-round iterative process and implementation results: The overall process consists of four stages: delay-guided mapping, multi-round area flow-guided mapping, multi-round area-guided mapping, and final graph matching and pairing. Each stage includes cut enumeration, cut selection, PF score calculation, and graph matching and pairing, ensuring that the pairing concept is integrated throughout multiple iterations.

[0099] Table 1

[0100] Typical benchmark circuit area and depth comparison for Versal and UltraScale+ dual-output LUT architectures

[0101] “RESYN ABC” is a single-output baseline scheme; “OURS” and “REFERENCE” are dual-output synthesis processes. Area optimization rate (saving rate) is calculated based on RESYN ABC; depth optimization rate (saving rate) is calculated based on the depth of the REFERENCE scheme.

[0102] ;

[0103] exist and Experiments were conducted on multiple reference circuits using two types of dual-output LUT architectures: ABC single-output mapping ( ( ) is used as the area baseline, with mainstream multi-output LUT mapping methods as a reference. In The present invention achieves an average area saving of approximately 36.78% compared to a single-output baseline, and further optimizes the area by approximately 2.34% and the average logic depth by approximately 3.10% compared to the control method; The average area reduction is approximately 23.71%, and compared to the control method, the area optimization and average logic depth optimization are approximately 3.64%. Some benchmarks (such as...) Significant improvements have been made in depth (etc.).

[0104] Experiments show that: compared to a single-output mapping baseline (such as...) ), in typical and On a dual-output LUT architecture, this invention can achieve an average area saving of approximately 36.78% and 23.71%; compared with mainstream multi-output LUT mapping methods, it can further achieve an area optimization of approximately 2.34% and a logic depth optimization of approximately 3.64%, while taking into account both area and depth, and has good engineering configurability.

Claims

1. A dual-output lookup table mapping method for FPGAs based on iterative pairing selection, characterized in that, Includes the following steps: Step 1: Enumerate feasible cuts for each node in the Boolean network and generate a set containing multiple candidate cuts for each node; Step 2: For each node, perform preliminary screening from its candidate cut set based on the single output optimization objective, define a tolerance window that is close to the optimal cut in terms of performance indicators, and determine the cuts within the window as candidate cuts; Step 3: For each cut in the set of candidate cuts, evaluate the probability of forming a valid double-output pair with neighboring nodes in the network in the future, and weight and aggregate the pairing probability evaluation values ​​of multiple key neighboring nodes to generate a pairing flow score. Step 4: Within the tolerance window, use the paired flow score as an auxiliary decision-making criterion when single output targets are similar, and select a representative cut for each node; Step 5: After obtaining the representative cuts of all nodes, check whether any pair of nodes satisfies the physical constraint that the representative cuts corresponding to them share the same double-output lookup table. The constraint includes that the total number of inputs after merging the two cuts does not exceed the maximum allowed number of inputs of the double-output lookup table, and that there is a shared input between the two cuts. All node pairs that satisfy the physical constraints are regarded as candidate pairs, and a weighted pairing relationship graph is constructed using the original pairing score that measures the quality of the pairing as the weight. Step 6: Perform conflict-aware graph matching on the weighted pairing graph, select non-conflicting node pairs in descending order of pairing quality, and form the final global double-output pairing set. Nodes belonging to the same pair are mapped to the same dual-output lookup table hardware unit.

2. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 1, characterized in that, In step 1, the tolerance window refers to a preset small percentage range within which the cost of the candidate cut can deviate from the current optimal cut cost in terms of single output cost, so as to leave room for optimization in pairing selection without significantly sacrificing single output performance.

3. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 1, characterized in that, In step 3, when evaluating the pairing probability between a candidate cut and its neighboring nodes, multiple candidate cuts of the neighboring nodes themselves are collected, and the original pairing flow scores of the current candidate cut and each candidate cut of the neighboring nodes are summed with probability weights to quantify the pairing probability with neighboring nodes whose final cuts have not been determined in the form of expected values.

4. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 3, characterized in that, In step 3, the original paired flow score is determined by the scale of the shared input between the two cuts and the difference in the depth of the two nodes in the logical hierarchy. The more shared input and the closer the logical depth, the higher the score, as shown in the formula below: ； in The shared input number for the two cuts. The maximum number of valid inputs allowed for the target dual-output LUT. The difference in logical depth between the two nodes. This represents the penalty coefficient for deep mismatch.

5. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 1, characterized in that, In step 3, when generating the pairing stream score, a preset number of neighboring nodes with the highest expected pairing score are selected to participate in the calculation, and weight coefficients are assigned in decreasing order according to the ranking, so that the neighboring nodes with the highest pairing probability contribute the most to the final score.

6. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 1, characterized in that, In step 6, the conflict-aware graph matching process specifically includes: sorting all candidate pairing edges according to their weight values ​​from high to low; sequentially traversing the sorted edges, and whenever an edge is encountered where neither of its two endpoints has been selected by a better pair, confirming the pairing relationship and locking the two nodes; continuing this process until all edges have been traversed to ensure that each node is assigned to at most one double-output lookup table.

7. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 1, characterized in that, The iterative mapping includes time-delay guided mapping, multi-round area flow guided mapping and multi-round area guided mapping executed sequentially, with each round executing steps (1)-(6).

8. The FPGA dual-output lookup table mapping method based on iterative pairing selection according to claim 1, characterized in that, When enumerating feasible cuts, the computational complexity of enumeration and storage is controlled to grow linearly with the network size by setting a maximum input limit for a single-output lookup table, applying a dominance pruning strategy, and limiting the upper limit of the number of candidate cuts retained by each node.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps of the method as described in any one of claims 1-8.

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