Integrated circuit device and manufacturing method thereof

A technology of integrated circuits and semiconductors, which is applied in the field of wafer hybrid bonding technology, can solve the problems of low reliability of metal interconnection and capacitive coupling, reduce the risk of leakage and capacitive coupling, improve reliability, and improve stability Effect

Inactive Publication Date: 2020-01-14
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to overcome the common problems of leakage and capacitive coupling between functional devices and functional devices in the prior art, and often have the defects of low reliability of metal interconnection on the hybrid bonding interface, An integrated circuit device and its manufacturing method are provided

Method used

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  • Integrated circuit device and manufacturing method thereof
  • Integrated circuit device and manufacturing method thereof
  • Integrated circuit device and manufacturing method thereof

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Embodiment Construction

[0069] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. Note that the aspects described below in conjunction with the drawings and specific embodiments are only exemplary, and should not be construed as limiting the protection scope of the present invention.

[0070] The following description is given to enable a person skilled in the art to make and use the invention and incorporate it into a specific application context. Various modifications, and various uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not limited to the embodiments given herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0071] In the following detailed description, numerous specific details are set forth in or...

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PUM

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Abstract

The invention discloses an integrated circuit device and a manufacturing method thereof. The integrated circuit device comprises a plurality of stacked semiconductor devices; each semiconductor devicecomprises a substrate and a dielectric layer formed on the substrate, and the dielectric layers of two adjacent semiconductor devices are combined together in the stacking direction; a plurality of functional devices and a plurality of isolation structures are formed in the dielectric layer of at least one of the semiconductor devices, and the isolation structures are used for isolating the adjacent functional devices; each isolation structure comprises an isolation trench and a filler applied in the isolation trench, and an opening of the isolation trench is located in the surface, back on to the substrate, of the dielectric layer. According to the invention, the electric leakage risk and the capacitance coupling risk between the functional devices can be effectively reduced, and the reliability of metal interconnection on the hybrid bonding interface is effectively improved, so that the wafer bonding stability is improved.

Description

technical field [0001] The invention relates to an integrated circuit device and a preparation method thereof, in particular to the field of wafer hybrid bonding technology. Background technique [0002] Wafer hybrid bonding (hybrid bonding) process can combine wafers of different materials together, and is currently widely used in various aspects of electronic manufacturing. [0003] At present, when performing hybrid bonding, the functional devices of the upper wafer and the lower wafer to be hybrid bonded are generally connected correspondingly. However, leakage problems and capacitive coupling (coupling) problems commonly exist between functional devices, and there are often problems of low reliability of metal interconnections on hybrid bonding interfaces, resulting in reduced stability of wafer bonding. Contents of the invention [0004] A brief summary of one or more aspects is presented below to provide a basic understanding of these aspects. This summary is not ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/065H01L21/764
CPCH01L21/764H01L25/0652H01L21/185H01L21/76283H01L21/7682H01L23/5226H01L24/08H01L24/80H01L2224/0346H01L2224/03602H01L2224/03616H01L2224/05647H01L2224/08058H01L2224/0807H01L2224/80345H01L2224/80357H01L2224/80895H01L2224/80896H01L2924/00014
Inventor 胡思平王涛严孟华子群
Owner YANGTZE MEMORY TECH CO LTD
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