1099 results about "Etching rate" patented technology

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention relates to the technical field of semiconductor manufacturing, in particular to an intelligent manufacturing process optimization method and system of an integrated industrial large model. Dynamic optimal combination solution of technological parameters such as photoetching dose, etching rate and film thickness is realized; an equipment operation instruction and an abnormal intervention strategy are generated in real time, and the accuracy and timeliness of operation are improved; and cross-process collaborative scheduling and bottleneck prediction are carried out, the whole production process is optimized, and finally the yield, efficiency and flexibility of semiconductor manufacturing are improved.

The invention relates to an experimental method for manufacturing a through hole by using gray exposure, and aims to realize a through hole structure with a specific inclination angle and depth-to-width ratio through collaborative design of photoetching and etching processes. The method comprises the following steps: determining a through hole angle and a depth-to-width ratio, selecting an etching condition, designing a gray mask structure based on an etching rate selection ratio, implementing gray exposure to obtain a mask pattern, etching, removing residual photoresist and finally forming a target through hole. And by regulating and controlling the selection ratio k of the mask to the substrate material, the inclination angle beta of the through hole and the depth H, designing the gray-scale mask morphology conforming to the target structure. The gray mask can be constructed by adopting gray photoresist or an optical modulation mask, and the inclination morphology parameter, the etching time and the etching rate of the gray mask meet a specific relation, so that high-precision structure control is realized. The method is suitable for the fields of MEMS, micro-optical devices and the like with high requirements on the morphology precision of the through hole, and has the effects of good structure consistency and high process repeatability.

The invention belongs to the technical field of laser processing, and provides a quartz crystal etching solution which comprises the following components in volume concentration: 10-30% of hydrofluoric acid, 1-5% of sulfuric acid, 0.1-0.3% of surfactant and the balance of water. By optimizing the proportion, the manufacturing precision and the production and manufacturing efficiency of the tuning fork wafer are improved. And the stable etching rate and the optimal etching surface are obtained, and meanwhile, the cost is saved for process replacement. The invention further provides a method for cutting the tuning fork of the quartz crystal through the laser. The method comprises the steps that S1, the cutting contour line of the tuning fork is preset on the quartz crystal; s2, performing laser cutting on the quartz crystal based on a preset cutting contour line, and forming a tuning fork contour on the quartz crystal; and S3, integrally soaking the quartz crystal in the quartz crystal etching solution, and separating out the tuning fork. The machining process of the quartz crystal tuning fork is simplified, the cutting quality is optimized, the method is suitable for the large-piece manufacturing process, and the cutting efficiency and the yield are greatly improved.

The invention provides an etching parameter adjusting method and device in MOSFET chip production, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining plasma density distribution data and an etching rate monitoring value of a wafer surface, and dynamically dividing the wafer surface into a plurality of segment independent control units; adjusting a radio frequency power distribution weight, and synchronously adjusting a reaction gas injection parameter; carrying out coupling analysis on the concentration gradient of the etching by-product and the matching degree of the surface morphology of the wafer; and when the deviation of the target value threshold is detected, temperature compensation and air pressure compensation are carried out. According to the method and the device, the technical problem of poor etching precision of the MOSFET chip caused by non-uniform etching rates of different regions in the etching process is solved, and the uniformity of the etching rates is improved through real-time monitoring and dynamic compensation, so that the etching precision of the MOSFET chip is improved.

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

The invention relates to a method for optimizing electroplating and etching process parameters, which comprises the following steps of: establishing an interface migration behavior relationship by analyzing the influence of metal ions, doped impurities and surface roughness factors on a reaction interface migration rate and a boundary layer flow behavior in an electroplating and etching process; interface migration behaviors are combined with parameter sensitivity analysis, the influence of process parameters on the interface behaviors is dynamically evaluated, and priority optimization sorting is carried out; dynamic interval zooming is carried out on the sensitive parameters by using the fitted sensitivity function, and a local adjustment range is generated according to material types and graph complexity; a preorder process memory mapping relation is introduced, and morphology evolution information recorded in the electroplating process is transmitted to an etching parameter optimization module; local fine adjustment is carried out on the etching rate, angle control and a disturbance mechanism, and the previous electroplating state is responded; collecting a fluctuation interface feedback signal; establishing a closed-loop optimization control loop of micro-disturbance, response evaluation and parameter correction; and the process consistency and the structure uniformity are improved.

Method to selectively diffuse dipole dopants into the high-k gate dielectric layer is provided. A method of the present disclosure includes an etching back process controlling DC and bias power, a periodical switching of the bias power is synchronized with a periodical switching of the DC power, leading to a balanced etching rate and uniform depth of recesses in dummy materials within the gate trenches for the subsequent selective diffusion process across different devices. Additionally, during the etching back process, a protective passivation layer can be formed as a barrier on the sidewall of the recess and / or at the bottom of the recess.

The invention provides an ion beam etching system with an etching rate in-situ monitoring function and an etching method, the ion beam etching system is provided with an objective table which can deflect by 90 degrees and an electrical test detection element which can move close to or far away from the objective table, and by the etching method, an ion source is not closed, a sample is not taken out, and the etching rate can be accurately measured. The etching depth can be accurately monitored by measuring the surface resistance of the sample in situ, the etching rate can be reduced in time, and the method is more suitable for the tape-out process. According to the ion beam etching system and the etching method, sputter spectrum monitoring is replaced by sample surface resistance detection, so that the test sensitivity is higher, the system cost is lower, the etching precision in magnetic tunnel junction preparation is greatly improved, the sample is prevented from being excessively etched, the thickness of a sample layer can be kept consistent, the resistance distribution is uniform, and the quality of the magnetic tunnel junction is improved. And the high success rate preparation of the SOT-MRAM memory with large capacity and small size is realized.

The invention relates to the technical field of semiconductor etching, in particular to a semiconductor etching method based on plasma coordinated regulation, which comprises the following steps: alternately using first plasma and second plasma on a semiconductor to be etched to obtain a plurality of groove structures with a preset depth-to-width ratio, the second plasma is used for cleaning side wall residues; detecting by using a laser interference measurement method to obtain an etching rate ratio and a side wall angle corresponding to each groove structure, and determining corresponding treatment according to the change condition of the etching rate ratio and the side wall angle, including maintaining the etching and cleaning parameters of the current stage, or adjusting the corresponding parameters of the first plasma according to the need, or corresponding parameters of the second plasma are adjusted according to needs. According to the method, the first plasma and the second plasma are cooperatively controlled to adjust the groove structure in each stage, so that the uniformity of the groove structure is improved, and the damage to the surface of the side wall is reduced.

The utility model provides a plasma cleaning device, and belongs to the technical field of semiconductor production equipment, the plasma cleaning device comprises a cavity, and a chamber is arranged in the cavity; the cover plate covers the upper end of the cavity; the remote plasma source is connected to the central position of the protruding part; the gas blocking part is arranged in the conical cavity; the first gas homogenizing plate is arranged below the gas blocking part; the second gas uniformizing plate is arranged below the first gas uniformizing plate; and a substrate table. The cover plate and the gas blocking part can uniformly disperse plasma gas fed by a remote plasma source into the cavity, then the plasma gas is further homogenized through the first gas homogenizing plate to ensure the gas uniformity of a substrate area, and meanwhile, the vacuum mechanism is generally connected to the bottom of the cavity, so that the gas is downwards pumped through the second gas homogenizing plate during gas pumping, and the gas uniformity of the substrate area is ensured. The gas uniformity in the chamber can be effectively ensured, so that the etching uniformity and the etching rate are improved.

The invention discloses a compatible molybdenum-aluminum mixed acid etching solution which comprises the following components in percentage by mass: 4%-7% of nitric acid, 55%-65% of phosphoric acid, 17%-28% of acetic acid, 0.5%-3% of an oxidizing additive, 0.05%-5% of a metal corrosion inhibitor and 10%-20% of deionized water, and the oxidizing additive is ceric nitrate and at least one selected from sodium nitrate, potassium nitrate and ammonium nitrate; the etching liquid does not contain other organic components except for organic carboxylic acid and organic carboxylate. According to the compatible molybdenum-aluminum mixed acid etching solution, on the basis that ceric nitrate is introduced, the content of nitric acid is reduced, the nitrate ion concentration is increased by adding nitrate, the overall oxidation performance of an etching solution system is improved, the etching rate ratio of different metals is adjusted, CD-Bias is reduced, the etching dip angles of a molybdenum single layer and a molybdenum-aluminum laminated layer are controlled to be kept at 20-50 degrees, and the problem of aluminum thorns is solved. The invention further discloses a molybdenum-aluminum etching method based on the compatible molybdenum-aluminum mixed acid etching solution.

The invention discloses an alkaline medium-coarsening micro-etching solution as well as a preparation method and a micro-etching method thereof, and relates to the technical field of printed circuit board production. The alkaline medium-coarsening micro-etching liquid is prepared from the following components in mass concentration: 5-30 g / L of ammonium chloride, 0.5-2 g / L of tetramethylammonium hydroxide, 5-15 g / L of ammonia water, 2-10% of a catalyst, 0.1-1% of a wetting agent, 0.2-2% of an accelerator, 0.3-1.5% of a stabilizer, 0.5-5% of a color difference regulator and the balance of deionized water. The invention provides an alkaline medium-coarsening micro-etching solution and a preparation method and a micro-etching method thereof, which can solve the problem of color change of a board surface after micro-etching of a circuit board and overcome the defect that a sulfuric acid hydrogen peroxide micro-etching system is easily polluted by chloride ions, and can effectively improve the problem that hydrogen peroxide is easily decomposed by replacing sulfuric acid hydrogen peroxide with an alkaline substance. And the micro-etching rate is stable.

The invention relates to the technical field of OLED (Organic Light Emitting Diode) manufacturing process etching processes, in particular to a silver etching solution for an OLED manufacturing process as well as a preparation method and application of the silver etching solution. The silver etching liquid comprises nitric acid, phosphoric acid, a buffer agent, a metal ion chelating agent and an ionic liquid inhibitor, the ionic liquid inhibitor comprises 1-butyl-3-methylimidazole phosphate, the metal ion chelating agent is selected from at least one of pyromellitic acid, diethylenetriamine pentaacetic acid and ethylenediamine tetramethylene phosphoric acid, and the buffer agent is selected from at least one of sodium chloride, sodium chloride and sodium chloride. The buffering agent comprises acetic acid, and all the components are prepared according to a specific mass ratio. The etching solution can balance the etching rate of silver and indium tin oxide, avoid silver residues and black spot defects, prolong the service life of the solution, reduce the use of a volatile buffer agent, adapt to the OLED fine manufacturing process, improve the product yield and reduce the production cost, and is suitable for etching of a metal substrate in the OLED manufacturing process.

The purpose of the present invention is to provide: an etching method exhibiting an excellent etching rate with respect to silicon; a method for manufacturing a semiconductor device; an etching apparatus; and an etching gas composition. The present invention pertains to an etching method for etching silicon by using a plasma gas obtained by converting an etching gas composition containing fluorine gas into plasma.

The utility model discloses a double-cavity processing system, which comprises two processing cavities used for respectively carrying out process processing on substrates arranged in the processing cavities; the main gas inlet channel is connected with a process gas source, and the gas flow divider assembly is arranged on the main gas inlet channel and used for dividing one path of process gas into four paths of process gas flows and supplying the four paths of process gas flows into the two processing cavities respectively; and the flow adjusting control unit is used for controlling the gas flow divider assembly according to the substrate processing results of the two processing cavities so as to adjust the process gas flow entering the two processing cavities. According to the utility model, the process gas flow in the two processing cavities is adjusted, so that the difference of the etching rate between the two processing cavities is reduced.

The invention discloses a self-adaptive etching control method for automobile circuit board manufacturing, and relates to the technical field of automobile circuit board manufacturing. The self-adaptive etching control method for manufacturing the automobile circuit board comprises the following steps: S1, real-time multi-source sensing: synchronously acquiring a copper layer etching rate, a three-dimensional shape and a bath solution temperature gradient through a multispectral confocal unit, an ultrasonic thickness measuring unit and a distributed temperature sensing unit which are integrated in an etching bath; s2, dynamic decision analysis; s3, multi-parameter cooperative execution: independently adjusting the pressure gradient, the atomization particle size and the oscillation frequency through a spraying pressure regulation and control unit, an etching agent atomization unit and a mechanical oscillation unit; s4, closed-loop process verification: feeding back etching uniformity, and dynamically correcting the decision model; through the steps of real-time multi-source sensing, dynamic decision analysis, multi-parameter cooperative execution and closed-loop process verification, accurate control over the automobile circuit board etching process is achieved, and the etching quality and efficiency are improved.

The invention discloses an antireflection film, a preparation method thereof and an optical device, and relates to the technical field of optics, the method comprises the steps that a composite material film layer is deposited on a substrate, the composite material film layer comprises a first material and a second material, and the etching rate of the first material is different from that of the second material during wet etching or dry etching; performing wet etching or dry etching on the composite material film layer to obtain a porous film layer; and sequentially carrying out cleaning treatment and drying treatment on the porous membrane layer. According to the anti-reflection film, the preparation method thereof and the optical device, the anti-reflection film of a porous structure is prepared by combining a coating technology commonly used in the industry and laboratories with a wet or dry etching method, equipment hardware does not need to be transformed, and the anti-reflection film is efficient and low in cost.

The invention discloses a super-lens design method based on etching uniformity compensation and an optimization system thereof. The super-lens design method specifically comprises the following steps: S1, etching a wafer and establishing an etching rate space distribution model; S2, designing layout partitions and distributing compensation coefficients; s3, pre-compensating the size of the nano structure; s4, generating a final mask and executing etching; according to the method, the space size pre-compensation of the nano structure is actively performed in the mask design stage, and the phase deviation caused by non-uniform etching depth is counteracted by using the change of the effective refractive index of the nano unit, so that the high-performance super lens is obtained under the non-ideal process condition, and the limitation of the process physical limit is broken through.

A method of fabricating an array substrate and an array substrate are disclosed. The array substrate includes a bonding portion, the bonding portion being fabricated by: providing a substrate, and forming a metal layer on the substrate; sequentially depositing a first and a second insulating layer material on the metal layer; etching the first and second insulating layer material respectively at a first etching rate and a second etching rate to form a first insulating layer having a first via hole and a second insulating layer having a second via hole, respectively, thus obtaining a composite insulating layer of a double-layer structure; forming on the composite insulating layer an electrode layer connected to the metal layer through the first and second via holes to form the bonding portion; where the first etching rate and the second etching rate are different, and the first and second via holes are arranged correspondingly.

A method for producing a nanochannel (200) is described with the following steps a) depositing a nanochannel sacrificial layer (3) using an ALD process on a substrate (1), which defines the subsequent channel height at least at one point b) depositing a first covering layer (4) on the nanochannel sacrificial layer (3) c) At least partially structuring and / or etching the nanochannel sacrificial layer (3) and the first cover layer (4) so ​​that a first exposed region (10) is formed d) At least partial etching of the now exposed nanochannel sacrificial layer (3) with an etching rate < 100nm / min, preferably <10nm / min, and particularly preferably <5nm / min and even more preferably <2nm / min, so that an under-etched second exposed region (20) is formed which defines the channel width e) depositing a second cover layer (5) onto the first cover layer (4) and the first exposed region (10) so that the second exposed region (20) is sealed and forms a nanochannel (200).

The invention relates to the technical field of circuit board etching, and discloses a PCB (printed circuit board) etching liquid homogenization system based on a liquid dynamic mixing structure, which comprises an etching tank, a protective plate is detachably mounted at the top of the etching tank, a rotating shaft is rotatably mounted in a space formed by the protective plate and the etching tank, a limiting part for clamping a PCB is arranged on the outer surface of the rotating shaft, and a swinging part for disturbing etching liquid is arranged in the etching tank; the limiting piece comprises a limiting frame fixedly connected to the outer surface of the rotating shaft, and the bottom of the limiting frame is fixedly connected with an abutting block. The PCB etching liquid homogenization system based on the liquid dynamic mixed structure can effectively solve the problems that in the prior art, products such as copper ions generated by reaction are locally accumulated, the concentration gradient can form a diffusion boundary layer, fresh etching liquid is prevented from being supplemented to the surface of a board, the etching rate is reduced, and the etching quality is influenced. Therefore, the etching rate of the surface of the circuit board is inconsistent, and the etching quality of the circuit board is affected.

Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material. The methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

The invention relates to a semiconductor etching BOE waste liquid resource reutilization method, and relates to the technical field of waste liquid treatment and resource recovery, and the semiconductor etching BOE waste liquid resource reutilization method comprises the following steps: S1, waste liquid pretreatment; step S2, silicon removal treatment; s3, removing an additive; step S4, activated carbon adsorption; and S5, component adjustment and refining. The resource recycling method of the BOE waste liquid for semiconductor etching has more excellent additive and metal ion removal rate, and is higher in BOE etching rate and better in surface flatness when being used for a panel.

The invention provides a composition, a resist underlayer film, a semiconductor device and a preparation method thereof. The composition comprises a silicon-containing resin, a solvent and an acid, the silicon-containing resin has a high branching degree, a new branching degree DB of the silicon-containing resin is defined according to the branching degree contributed by a Q structural unit and a T structural unit in the silicon-containing resin and in combination with a 29Si nuclear magnetic resonance spectrogram, and the branching degree DB of the silicon-containing resin is controlled to be within a proper range. The silicon-containing resin is added into the composition, so that a resist underlayer film formed by the composition has relatively high anti-reflection performance and relatively high dry etching rate at the same time.

The invention discloses a calibration method of photoelectron spectroscopy equipment, and relates to the field of semiconductors. The calibration method comprises the following steps: etching a film sample for the first time; carrying out X-ray bombardment on the etched film sample, and collecting a spectrogram; obtaining an etching thickness according to the current thickness of the etched film sample and the initial thickness of the film sample before etching; according to the etching thickness and the spectrogram, obtaining a relationship between the element content of the film sample and the etching depth so as to determine a first etching rate; etching the film sample with the determined first etching rate for the second time by adopting the same etching condition to obtain a second etching rate; when the first etching rate is the same as the second etching rate, it is judged that etching of the photoelectron spectroscopy equipment is stable, and the first etching rate or the second etching rate is determined as a reference etching rate; and when the first etching rate is different from the second etching rate, determining the second etching rate as a reference etching rate. The problems that an X-ray photoelectron spectrometer is stable in etching rate, poor in accuracy and the like can be solved.

The invention discloses a high aspect ratio deep silicon etching structure and a patterning method thereof. The patterning method comprises the following steps: providing a substrate made of silicon; forming a plurality of photoresist patterns on the surface of the substrate, wherein an opening is formed between every two adjacent photoresist patterns; bombarding the interface of the substrate at the inner bottom corner of the opening by using plasma of a first gas at a first ultralow temperature to form a first protective film; depositing a polymer layer on the substrate, the photoresist pattern and the first protective film for protection by using plasma of second gas at a second ultralow temperature; etching the polymer layer and the substrate by using plasma of a third gas at a third ultralow temperature; repeating the steps of depositing the polymer layer and etching until a high aspect ratio deep silicon etching structure is formed on the substrate; and removing the photoresist pattern. According to the invention, the uniform protection of the side wall under the conditions of smaller size and higher aspect ratio can be realized, and the etching rate can be improved.

The invention discloses an etching solution and a preparation method and an etching method thereof, and belongs to the technical field of microelectronics and display panel manufacturing. The etching liquid comprises the following components in percentage by mass: 50-70% of phosphoric acid, 5-30% of acetic acid, 5-15% of nitric acid, 0.1-0.5% of a water-soluble polymer, 0.05-0.3% of a boron-containing compound, 0.05-0.5% of an etching control agent and the balance of water. The water-soluble polymer is selected from one or more of water-soluble polymers containing a hydroxyl group, an amide group, an ether bond or a pyrrolidone group. The etching solution contains a specific water-soluble polymer, a protective layer can be formed on the surface of the photoresist, attack of high-concentration acid to the etching solution is effectively inhibited, and the cracking problem is avoided; meanwhile, through the synergistic effect of the boron-containing compound and the azole etching control agent, the etching rate, the slope angle and the key size loss can be accurately controlled, and therefore the excellent etching morphology meeting the requirement is obtained.

The invention discloses a growth method for reducing a Pit defect on a silicon carbide epitaxial surface, which comprises the following steps of: after epitaxial growth is completed, increasing the air flotation flow of a base, increasing the temperature in a reaction chamber, reducing the pressure in the reaction chamber and increasing the hydrogen flow, and entering an etching stage; hydrogen chloride gas is introduced discontinuously in the etching stage, and at least one introduction time period and an interruption time period after the introduction time period are included; the thermal instability of SiC at high temperature / low pressure is utilized, efficient decomposition is achieved through an H2 / HCl synergistic etching system, sub-damage and dislocation are reduced while the etching rate is increased, the thickness of the removed epitaxial layer can be accurately controlled, the Pit defect of the surface layer of the epitaxial layer is reduced, the crystallization quality of the epitaxial layer is kept, and the subsequent power device preparation requirement is met.