430 results about "Etching rate" patented technology

Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material. The methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

The invention discloses an etching solution and a preparation method and an etching method thereof, and belongs to the technical field of microelectronics and display panel manufacturing. The etching liquid comprises the following components in percentage by mass: 50-70% of phosphoric acid, 5-30% of acetic acid, 5-15% of nitric acid, 0.1-0.5% of a water-soluble polymer, 0.05-0.3% of a boron-containing compound, 0.05-0.5% of an etching control agent and the balance of water. The water-soluble polymer is selected from one or more of water-soluble polymers containing a hydroxyl group, an amide group, an ether bond or a pyrrolidone group. The etching solution contains a specific water-soluble polymer, a protective layer can be formed on the surface of the photoresist, attack of high-concentration acid to the etching solution is effectively inhibited, and the cracking problem is avoided; meanwhile, through the synergistic effect of the boron-containing compound and the azole etching control agent, the etching rate, the slope angle and the key size loss can be accurately controlled, and therefore the excellent etching morphology meeting the requirement is obtained.

The invention relates to an atomic layer etching system and method with a uniformity control mechanism. The ALE process includes a plurality of cycles, each cycle including a surface modification step and a sputtering step. The plasma source includes a center coil and an edge coil. The system supports the use of different selectable configurations in sputtering steps in different ALE cycles, capable of independently activating or closing the center coil and the edge coil. The flexibility provides a mechanism for adjusting the etching rate of the center and the edge of the substrate, so that non-uniformity (such as thickness difference) of the substrate to be processed is compensated. The system controller can generate a process formula based on the to-be-processed substrate data and the output specification so as to ensure that the etching process meets the expected performance requirement.

The invention relates to the technical field of etching solutions, and particularly discloses an etching solution for inhibiting etching of metallic titanium and application of the etching solution. The etching solution contains hydrofluoric acid, ammonium fluoride, an additive 1 and an additive 2; wherein the additive 1 is a fluorine capture type inhibitor, and the additive 2 is a surface adsorption type organic protective agent. The etching solution can effectively inhibit the corrosion of a titanium layer while keeping the high etching rate of silicon oxide, obviously improves the etching selection ratio of silicon oxide to titanium, has lower surface tension and higher uniformity, and is suitable for a wet etching scene with a complex structure. The additive 1 captures free fluorine ions through complexation or precipitation, the activity of the fluorine ions is reduced, and therefore the chemical attack on the titanium surface is reduced; and the additive 2 can form a transient adsorption protective film on the titanium surface to further delay the dissolution of titanium. The synergistic effect of the two additives can effectively inhibit titanium corrosion and maintain high etching efficiency.

The invention relates to the technical field of etching solutions, and discloses a molybdenum-aluminum-niobium etching solution for a TFT-LCD (Thin Film Transistor Liquid Crystal Display), which comprises the following components in percentage by mass: 50 to 60 percent of phosphoric acid, 3 to 8 percent of nitric acid, 5 to 10 percent of glacial acetic acid, 1 to 5 percent of aluminum nitrate, 0.1 to 0.5 percent of diphenyl thiourea, 1 to 5 percent of etidronic acid, 3.0 to 5.0 percent of sodium hexametaphosphate, 0.1 to 0.2 percent of fatty alcohol-polyoxyethylene ether, 0.5 to 0.8 percent of amino trimethylene phosphonic acid and the balance of ultrapure water. The invention further discloses a preparation method of the molybdenum-aluminum-niobium etching solution. According to the invention, a phosphorus nitrate vinegar system, a composite additive, a novel corrosion inhibitor, a metal ion chelating agent and a surfactant matched with the etching liquid are adopted, so that the molybdenum-aluminum-niobium multi-layer composite metal film can be simultaneously etched at one time; the etching solution has the advantages of being uniform in etching, capable of inhibiting Mo / Nb etching, high in selectivity, controllable in etching rate, free of residues, long in service life, high in stability and the like.

The present invention provides a method of depositing molybdenum in a feature and an associated apparatus, the method comprising: providing a substrate comprising molybdenum to be filled to a chamber, the feature having one or more openings; depositing a conformal thin film of molybdenum in the feature; non-conformally treating the conformal film to increase an etch rate, wherein the treatment preferentially acts on a portion of the conformal film proximate to the one or more openings relative to a portion of the conformal film farther from the one or more openings; etching the conformal film in a non-conformal manner; and depositing molybdenum within the feature.

The invention belongs to the technical field of MEMS (Micro Electro Mechanical System) manufacturing, and particularly relates to a deep corrosion method for a back cavity of an MEMS pressure sensor. Comprising the following steps: constructing a'preset reference-gradient rough corrosion-real-time correction-precise fine corrosion 'closed-loop control system: firstly, establishing a precise temperature-corrosion rate corresponding relation through a QC wafer experiment; according to the target depth of the back cavity, multiple rounds of gradient rate coarse corrosion processes are planned, the corrosion depths of all rounds are distributed according to the proportion from large to small, and the corrosion rate is decreased progressively along with the rounds through temperature regulation and control to rapidly approach 80%-95% of the target depth; the depth is detected immediately after each round of corrosion, and targeted correction of'parameter fine adjustment 'or'deviation compensation' is realized based on a double-threshold criterion; and finally, turning to multiple rounds of low-rate fine corrosion, continuing a gradient rate and a real-time correction strategy, and precisely closing a loop to a target depth. According to the invention, submicron level control of the depth of the back cavity is realized, the process stability and adaptability are high, and the performance consistency and the large-scale production yield of the MEMS pressure sensor are effectively improved.

The disclosure provides a laser, a preparation method of the laser and an optical module, and relates to the technical field of optical elements, so as to meet the demand of the optical module for high-power lasers. The laser comprises the following steps: growing an etching auxiliary layer on the surface of a wafer body of the laser, the longitudinal etching rate of the wafer body is greater than the transverse etching rate of the wafer body, the transverse etching rate of the etching auxiliary layer is greater than the transverse etching rate of the wafer body, and the wafer body comprises a quantum well layer; forming a mask layer above the etching auxiliary layer, and pre-treating the mask layer to form a BH pattern; etching the BH pattern, so that the top of the wafer body is etched into a BH mesa, the etching depth is below the quantum well layer, and the etching depth is below the quantum well layer; growing a current blocking layer on both sides of the BH mesa; removing the mask layer and the etching auxiliary layer; and forming a P-InP layer on the top of the BH mesa and the current blocking layer.

Provided is a method of processing a substrate in a reaction chamber, more particularly to a method of increasing a wet etch rate of SiCN layer in order to reduce an overhang from a SiCN layer formed on a stepped structure. The method comprises supplying a carbon-containing silicon source and a nitrogen gas simultaneously while applying a power, followed by performing a post treatment, wherein the wet etch rate of SiCN layer is modulated by the amount of nitrogen source supplied.

This invention relates to the field of semiconductor fabrication, specifically to an illumination device, method of use, and etching system for etching silicon wafer surfaces; a support stage for holding multiple silicon wafers; multiple light sources positioned directly above the support stage for illuminating the surface of the silicon wafers; a liquid crystal light shield disposed between the silicon wafers and the light sources, the transmittance of which can be adjusted by an electrical signal; and a control unit for controlling the transmittance of the liquid crystal light shield, so that the light emitted from the light sources forms multiple illuminated areas on the silicon wafer surface after passing through the liquid crystal light shield. The illumination device of this invention can control the TMAH etching rate of different areas on the silicon wafer surface, directly improving the TTV performance of the product, ensuring the flatness of the wafer surface after etching, effectively improving the stability of subsequent processes and product quality, while also significantly improving the product yield and further reducing material costs in the production process.

The invention relates to the technical field of semiconductor manufacturing, in particular to a technological method for improving uniformity and appearance of an LED chip based on ICP multi-stage etching, which comprises the following steps: placing an LED epitaxial wafer to be etched in an ICP reaction chamber, and introducing etching gas; plasma is started, at least two etching stages are executed in sequence, the set values of the upper electrode power and / or the lower electrode power of the at least two etching stages are different, and all the etching stages are switched according to the preset etching depth or time; and after the etching reaches the target total depth, the process is stopped. And the plasma density and the ion bombardment energy are effectively balanced through the optimized parameters in the second stage, so that the consistency of the etching rates in the wafers and between the wafers is greatly improved. The data of the embodiment shows that the inter-disk uniformity can be optimized to be within 4.80% from 4.50% of a traditional method.

This application provides a semiconductor structure and a method for trimming the same. A first structure to be trimmed is provided. The first structure to be trimmed includes a substrate layer, a first film layer, and a second film layer stacked sequentially. The second film layer includes multiple line structures, each with a first roughness. A third film layer is deposited on the first structure to be trimmed to obtain the second structure to be trimmed. The second structure to be trimmed is then subjected to ion beam etching to obtain a trimmed structure. In the trimmed structure, the line structures in the second film layer have a smaller second roughness. In this application, the deposited third film layer has different thicknesses at different locations. The first thickness of the third film layer on the top surface of the second film layer is greater than its second thickness on the side surface of the second film layer. This difference in thickness is used to compensate for differences in the etching rate of the second film layer. While improving the linewidth roughness or line edge roughness, this method ensures that the top of the second film layer is not excessively etched away, reducing top loss.

The invention provides a manufacturing method of a semiconductor structure, a first etching process is utilized to modify a first morphology of the semiconductor structure to obtain a transition morphology, and a first incident angle of the first etching process is determined according to a first corresponding relation among a first fluctuation difference value, an etching rate and an equivalent incident angle. The first fluctuation difference value is a difference value between the first highest point and the first lowest point in the first morphology. And modifying the transition morphology by using a second etching process to obtain a second morphology. A second incident angle of the second etching process is determined according to a second corresponding relation among a second undulation degree difference value, the etching rate and the equivalent incident angle, the second undulation degree difference value is a difference value between a second highest point and a second lowest point in the transition morphology, and the second morphology meets a planarization condition. According to the secondary etching process, the incident angle is determined by maximizing the etching rate difference value between the highest point and the lowest point, surface defect modification can be achieved, and global planarization of the semiconductor structure is achieved.

The invention relates to the technical field of semiconductors, in particular to a wafer-level lithium niobate quantum waveguide etching depth real-time prediction method, which specifically comprises the following steps of: dividing an etching region into a plurality of etching space partitions, and constructing an etching space partition identifier set; collecting an etching physical quantity set and plasma emission characteristic intensity, and binding the etching physical quantity set and the plasma emission characteristic intensity with the corresponding etching space partition identifiers to form an etching process characteristic sequence set; quantifying the etching rate evolution condition, and independently accumulating the etching rate to obtain an evolution result set; comparing the etching depth with a target etching depth region by region; meanwhile, the etching depth difference of the etching space partitions is judged, and the quantum waveguide position with the over-etching or under-etching risk is recognized. According to the invention, the problems of local degradation of the optical performance of the wafer-level lithium niobate quantum waveguide and reduction of the yield of devices in the prior art are solved.

A dry etching method for indium-containing III-V compound semiconductor materials, relating to the field of semiconductor laser processing technology, solves the problem of volatile InCl during etching of indium-containing compound semiconductor laser materials in existing technologies. x Deposition leads to decreased etching rates, cavity contamination, and high-temperature assisted etching causes mask loss, morphology degradation, and process instability. This invention addresses these issues by setting a cycle program that alternates between etching and rinsing pulses. During the etching stage, H2 is introduced to suppress the formation of non-volatile InCl3 products and simultaneously convert InCl3 products into InCl2, effectively inhibiting byproduct formation and improving etching efficiency. During the physical rinsing stage, Ar is used to effectively remove non-volatile InCl3 adhering to the surface of the etched material. x The product exposes the semiconductor substrate, promoting chemical pulses to carry out chemical reactions to etch the substrate, effectively preventing cavity contamination and a decrease in etching uniformity, and significantly improving the controllability and repeatability of the etching morphology.

A method for manufacturing a semiconductor structure includes forming a plurality of semiconductor stack portions spaced apart from each other by a plurality of recesses, each of which includes two sacrificial layer portions and a channel layer portion disposed therebetween, in which the channel layer portion has a plurality of crystal planes and is formed with a first straight lateral surface which is aligned with one of the crystal planes that has a lowest etching rate for an etchant to be used for laterally etching the channel layer portion among those of the crystal planes of the channel layer portion which are able to expose to the recesses; and laterally etching the channel layer portion using the etchant to permit the channel layer portion to be formed with a second straight lateral surface.

The application provides a deep silicon etching method and a semiconductor process equipment, and relates to the technical field of semiconductors. The deep silicon etching method comprises a first cycle step and a second cycle step. The first cycle step and the second cycle step both comprise an etching step for etching a silicon substrate to form a groove, a removal step for removing by-products, and a deposition step for forming a protective layer on the sidewall of the groove. The protective gas used in the deposition step of the second cycle step comprises an oxygen-containing gas, and the lower electrode power of the deposition step of the second cycle step is greater than that of the deposition step of the first cycle step. The deep silicon etching method can balance the etching rate of different regions of the isolation groove, optimize the depth micro-loading effect, and improve the depth consistency of the isolation groove. Meanwhile, the deposition step does not consume the mask layer, thereby reducing the consumption of the mask layer, ensuring the effective height of the mask layer, improving the morphology precision of the formed isolation groove and AA, and improving the electrical properties and yield of the product.

Provided is an adhesive composition for forming an adhesive layer between a support substrate and a semiconductor substrate or an electronic device substrate. The adhesive composition includes an adhesive component (A) that hardens by a hydrosilylation reaction, and the etching rate of the adhesive layer measured by a specific measurement method is 10 μm / min. or more.

The application discloses a high aspect ratio deep silicon structure patterning definition method and a high aspect ratio deep silicon structure, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: forming a plurality of photoresist patterns on the surface of a silicon substrate; at a first temperature, using a first gas as a deposition gas, depositing a polymer layer on the silicon substrate and the photoresist patterns; at a second temperature, using a second gas as an etching gas, etching the polymer layer and the silicon substrate; repeating the deposition and etching steps until a high aspect ratio deep silicon structure is formed on the silicon substrate; and removing the photoresist patterns. The first temperature and the second temperature are less than -40 DEG C, the first gas is CH4, CHF3 and H2, which is used for uniformly depositing an a-C:H:F cross-linked polymer layer, and the second gas is F2 and N2, which is used for improving the bottom etching rate and reducing the photoresist pattern loss. The application can uniformly protect the sidewall at a smaller size and a higher aspect ratio, and can improve the etching rate.

A wafer structure is disclosed comprising a top silicon layer with a polished surface, an oxide layer selectively removed in defined regions, and a bottom silicon layer. Selective oxide removal improves dicing, prevents small molecule ingress, and enhances MEMS device release and performance. The invention addresses challenges of conventional silicon-on-insulator (SOI) wafers, including jagged edges, particle generation during stealth dicing, slow and uncontrolled under-etch rates, and high resistive losses in radio frequency (RF) applications due to parasitic surface conduction. Patterning the oxide layer enables precise MEMS structure release, reduces die size, and improves RF isolation. The wafer structure is suitable for high-speed electronics, RF analog circuits, and MEMS devices such as resonators, accelerometers, and waveguides, offering improved manufacturability and device reliability.

The invention discloses a method for improving the yield of glass through holes, and the method comprises the steps: obtaining the internal morphology of a laser-induced modification region through three-dimensional point cloud data, and precisely calculating the modification depth; fusing the laser process parameters and the material attributes by adopting an improved convolutional neural network model, and predicting the etching rate and the standard deviation of each modified area; based on the same set of three-dimensional detection data, a rework compensation decision and an etching process are driven to optimize double closed loops, point-level laser secondary induction is carried out on an insufficient-depth area, array ultrasonic power distribution is dynamically adjusted according to a rate prediction result, and ultrasonic power is improved for a slow-speed area; and continuously fine-tuning model parameters through an online meta-learning adaptation mechanism to realize adaptive evolution of the process model. According to the method, detection, prediction, reworking and regulation are integrated in the same process track, the problems that internal induction defects cannot be recognized, the etching rate is uneven and the process depends on experience in a traditional process are solved, and the preparation yield and the process consistency of the TGV through holes are remarkably improved.

Provided is a plasma etching method with which it is possible to etch silicon at a high etching rate by using iodine fluoride in the presence of a carbon material or a silicon oxide material. This plasma etching method comprises an etching step for performing plasma etching of silicon in the presence of a carbon material or a silicon oxide material by using plasma obtained by converting an etching gas into plasma. The etching gas contains iodine fluoride and a hydrogen-containing compound. The hydrogen-containing compound is a compound that has a hydrogen atom in a molecule and does not have an oxygen atom in the molecule.

The application provides an Ag etching solution, a preparation method and application thereof. The Ag etching solution comprises the following components in a weight ratio: 40-80 parts of inorganic acid; 10-50 parts of organic acid; 0.05-1.5 parts of corrosion inhibitor; 0.1-2 parts of chelating agent; 1-7.5 parts of buffer; and 30-50 parts of ultrapure water. The application further discloses a preparation method of the Ag etching solution and application thereof in the field of etching ITO-Ag-ITO composite layers. The inorganic acid is selected from one or more of phosphoric acid, sulfuric acid, carbonic acid, boric acid, hydrobromic acid, iodic acid, hypoiodous acid, hydrofluoric acid and nitric acid. The inorganic acid is preferably phosphoric acid and nitric acid. The Ag etching solution has a stable etching rate for ITO-Ag-ITO, and is not damaged to the insulating layer and photoresist, and can be used in the OLED pixel electrode manufacturing process, and the Ag layer is not provided with burrs and is not shrunk after etching.

The application provides a method for improving the etching rate of aluminum metal, which adopts high-concentration nitrogen and other etching gases for etching, specifically, depositing an aluminum metal layer on a substrate, and coating photoresist on the surface; using a mixed gas of BCl3, Cl2 and N2 as etching gas to perform dry etching on the aluminum metal layer without photoresist coating, wherein the N2 concentration is 40-100 sccm. It is verified by experiments that after the nitrogen concentration exceeds 10-20 sccm which is used to realize passivation, further increasing the nitrogen concentration can significantly improve the etching rate, thereby reducing the production cost. The application breaks through the conventional cognition of using low-concentration nitrogen as passivation gas, and has a good application prospect in the etching of the aluminum metal layer.

The invention relates to the field of semiconductor preparation, in particular to an illumination device for silicon wafer surface etching, a using method and an etching system. The bearing table is used for bearing a plurality of silicon wafers; the plurality of light sources are arranged right above the bearing platform and are used for illuminating the surface of the silicon wafer; the liquid crystal shading plate is arranged between the silicon wafer and the light source, and the light transmittance of the liquid crystal shading plate can be adjusted through an electric signal; the control unit is used for controlling the light transmittance of the liquid crystal shading plate, so that light emitted by the light source forms a plurality of illumination areas on the surface of the silicon wafer after passing through the liquid crystal shading plate; the illumination device can control the TMAH etching rate of different areas on the surface of the silicon wafer, the TTV performance of a product is directly improved, the flatness of the surface of the wafer after etching is ensured, the stability of a subsequent process and the product quality are effectively improved, meanwhile, the yield of the product is remarkably improved, and the material cost in the production process is further reduced.

This invention discloses a method for fabricating a high-efficiency Micro-OLED structure, belonging to the field of OLED display technology. Addressing the problems of insufficient brightness, severe large-angle scattering light loss, and bottlenecks in improving light extraction efficiency in existing silicon-based Micro-OLEDs, this invention fabricates a silicon dioxide / silicon nitride bilayer dielectric layer on a CMOS substrate. Utilizing the difference in etching rates between the two layers, a parabolic reflective bowl anode is fabricated. The pixel definition layer, organic light-emitting layer, thin-film encapsulation layer, color filter layer, and planarization layer are then fabricated sequentially. Finally, a microlens array coaxial with the reflective bowl is fabricated, forming a synergistic light-gathering system. This invention can significantly reduce internal light loss in the device, significantly improve peak brightness and light extraction efficiency, is compatible with existing mass production processes, and meets the high-brightness application requirements of AR / VR near-eye displays.

This invention proposes a low-tension aluminum etching solution for displays and its preparation method, belonging to the field of etching solution technology. The solution includes the following raw materials: phosphoric acid, nitric acid, sulfuric acid, acetic acid, stabilizer, surfactant, and water. The preparation method of the stabilizer is as follows: S1. Sodium alginate is dissolved in water, and calcium chloride solution is added dropwise to emulsify and obtain nanospheres; S2. The nanospheres are added to an ethanol solution, a silane coupling agent is added, and the mixture is heated and stirred to obtain double-bond modified nanospheres; S3. The double-bond modified nanospheres, dimethylaminoethyl methacrylate, and an initiator are mixed, heated and stirred to react, centrifuged, filtered, and washed to obtain modified nanospheres; S4. The modified nanospheres are added to an organic solvent, an alkali and an alkyl chlorocarbon are added, heated and stirred to react, centrifuged, filtered, washed, and dried to obtain the stabilizer. Compared with existing aluminum etching solutions, this solution exhibits a high etching rate for aluminum, stable reaction, no residue, and virtually no side etching, showing broad application prospects.

The application provides a preparation method of a semiconductor device, comprising the following steps: providing a substrate, wherein the substrate is provided with a gate structure; forming a side wall oxide layer on the substrate and the gate structure; forming a stress memory layer on the side wall oxide layer and performing a first annealing process; removing the stress memory layer and part of the thickness of the side wall oxide layer; performing a nitrogen doping process on the remaining side wall oxide layer; and etching to remove the remaining side wall oxide layer. The unexpected effect of the application is that: by performing the nitrogen doping process on the remaining side wall oxide layer, nitrogen ions are doped into the remaining side wall oxide layer, so as to increase the etching rate when the remaining side wall oxide layer is etched to be removed, to ensure that the remaining side wall oxide layer can be removed completely, to avoid that the remaining side wall oxide layer on the substrate affects the formation of a subsequent metal contact layer, and to improve the conductive performance of the device.

The invention relates to the technical field of etching solutions, and particularly discloses a high-selectivity titanium silicon nitrogen / titanium nitride etching solution. The cleaning agent comprises the following raw materials in percentage by mass: 30-60% of an acidic medium; 10-25% of a diffusant; 1-10% of a complexing agent; 0.1-1% of an oxidizing agent; 0.01%-0.1% of a stabilizing agent; the complexing agent is a sulfur-containing compound. According to the etching solution, the oxidizing agent and the sulfur-containing compound are added to serve as complexing agents, the etching solution has a high selection ratio for TiSiN and TiN etching, when it is guaranteed that the titanium-silicon-nitrogen etching rate is 10-20 A / min, the titanium-silicon-nitrogen / titanium nitride selection ratio is increased to 50 or above, and the etching rate is stable.

This invention provides a through-hole encapsulation structure, an LTPO display screen, and an LTPS display screen, relating to the field of display screen encapsulation technology. It includes: a substrate, with a drilled structure formed on top of the substrate, in which multiple slits are etched; the drilled structure includes inorganic layers and metal layers stacked from bottom to top; a first support structure, a second support structure, and a third support structure are also formed above the drilled structure. The beneficial effect is that it uses a metal-inorganic material stack, and utilizes the different etching rates of the metal and inorganic materials to achieve lateral etching to form the drilled structure, resulting in better through-hole encapsulation performance compared to the traditional method of stacking organic and inorganic layers. For flexible through-hole encapsulation structures, adding a metal layer to the original connection hole layer and utilizing the different etching rates of the metal and inorganic materials to achieve lateral etching can form the drilled structure, simplifying the manufacturing process.