827 results about "Etching rate" patented technology

The invention relates to the technical field of semiconductor manufacturing, in particular to an intelligent manufacturing process optimization method and system of an integrated industrial large model. Dynamic optimal combination solution of technological parameters such as photoetching dose, etching rate and film thickness is realized; an equipment operation instruction and an abnormal intervention strategy are generated in real time, and the accuracy and timeliness of operation are improved; and cross-process collaborative scheduling and bottleneck prediction are carried out, the whole production process is optimized, and finally the yield, efficiency and flexibility of semiconductor manufacturing are improved.

The invention relates to an experimental method for manufacturing a through hole by using gray exposure, and aims to realize a through hole structure with a specific inclination angle and depth-to-width ratio through collaborative design of photoetching and etching processes. The method comprises the following steps: determining a through hole angle and a depth-to-width ratio, selecting an etching condition, designing a gray mask structure based on an etching rate selection ratio, implementing gray exposure to obtain a mask pattern, etching, removing residual photoresist and finally forming a target through hole. And by regulating and controlling the selection ratio k of the mask to the substrate material, the inclination angle beta of the through hole and the depth H, designing the gray-scale mask morphology conforming to the target structure. The gray mask can be constructed by adopting gray photoresist or an optical modulation mask, and the inclination morphology parameter, the etching time and the etching rate of the gray mask meet a specific relation, so that high-precision structure control is realized. The method is suitable for the fields of MEMS, micro-optical devices and the like with high requirements on the morphology precision of the through hole, and has the effects of good structure consistency and high process repeatability.

The invention provides an etching parameter adjusting method and device in MOSFET chip production, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining plasma density distribution data and an etching rate monitoring value of a wafer surface, and dynamically dividing the wafer surface into a plurality of segment independent control units; adjusting a radio frequency power distribution weight, and synchronously adjusting a reaction gas injection parameter; carrying out coupling analysis on the concentration gradient of the etching by-product and the matching degree of the surface morphology of the wafer; and when the deviation of the target value threshold is detected, temperature compensation and air pressure compensation are carried out. According to the method and the device, the technical problem of poor etching precision of the MOSFET chip caused by non-uniform etching rates of different regions in the etching process is solved, and the uniformity of the etching rates is improved through real-time monitoring and dynamic compensation, so that the etching precision of the MOSFET chip is improved.

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

The invention relates to a method for optimizing electroplating and etching process parameters, which comprises the following steps of: establishing an interface migration behavior relationship by analyzing the influence of metal ions, doped impurities and surface roughness factors on a reaction interface migration rate and a boundary layer flow behavior in an electroplating and etching process; interface migration behaviors are combined with parameter sensitivity analysis, the influence of process parameters on the interface behaviors is dynamically evaluated, and priority optimization sorting is carried out; dynamic interval zooming is carried out on the sensitive parameters by using the fitted sensitivity function, and a local adjustment range is generated according to material types and graph complexity; a preorder process memory mapping relation is introduced, and morphology evolution information recorded in the electroplating process is transmitted to an etching parameter optimization module; local fine adjustment is carried out on the etching rate, angle control and a disturbance mechanism, and the previous electroplating state is responded; collecting a fluctuation interface feedback signal; establishing a closed-loop optimization control loop of micro-disturbance, response evaluation and parameter correction; and the process consistency and the structure uniformity are improved.

The invention relates to the technical field of semiconductor etching, in particular to a semiconductor etching method based on plasma coordinated regulation, which comprises the following steps: alternately using first plasma and second plasma on a semiconductor to be etched to obtain a plurality of groove structures with a preset depth-to-width ratio, the second plasma is used for cleaning side wall residues; detecting by using a laser interference measurement method to obtain an etching rate ratio and a side wall angle corresponding to each groove structure, and determining corresponding treatment according to the change condition of the etching rate ratio and the side wall angle, including maintaining the etching and cleaning parameters of the current stage, or adjusting the corresponding parameters of the first plasma according to the need, or corresponding parameters of the second plasma are adjusted according to needs. According to the method, the first plasma and the second plasma are cooperatively controlled to adjust the groove structure in each stage, so that the uniformity of the groove structure is improved, and the damage to the surface of the side wall is reduced.

The invention discloses a compatible molybdenum-aluminum mixed acid etching solution which comprises the following components in percentage by mass: 4%-7% of nitric acid, 55%-65% of phosphoric acid, 17%-28% of acetic acid, 0.5%-3% of an oxidizing additive, 0.05%-5% of a metal corrosion inhibitor and 10%-20% of deionized water, and the oxidizing additive is ceric nitrate and at least one selected from sodium nitrate, potassium nitrate and ammonium nitrate; the etching liquid does not contain other organic components except for organic carboxylic acid and organic carboxylate. According to the compatible molybdenum-aluminum mixed acid etching solution, on the basis that ceric nitrate is introduced, the content of nitric acid is reduced, the nitrate ion concentration is increased by adding nitrate, the overall oxidation performance of an etching solution system is improved, the etching rate ratio of different metals is adjusted, CD-Bias is reduced, the etching dip angles of a molybdenum single layer and a molybdenum-aluminum laminated layer are controlled to be kept at 20-50 degrees, and the problem of aluminum thorns is solved. The invention further discloses a molybdenum-aluminum etching method based on the compatible molybdenum-aluminum mixed acid etching solution.

The invention discloses an alkaline medium-coarsening micro-etching solution as well as a preparation method and a micro-etching method thereof, and relates to the technical field of printed circuit board production. The alkaline medium-coarsening micro-etching liquid is prepared from the following components in mass concentration: 5-30 g / L of ammonium chloride, 0.5-2 g / L of tetramethylammonium hydroxide, 5-15 g / L of ammonia water, 2-10% of a catalyst, 0.1-1% of a wetting agent, 0.2-2% of an accelerator, 0.3-1.5% of a stabilizer, 0.5-5% of a color difference regulator and the balance of deionized water. The invention provides an alkaline medium-coarsening micro-etching solution and a preparation method and a micro-etching method thereof, which can solve the problem of color change of a board surface after micro-etching of a circuit board and overcome the defect that a sulfuric acid hydrogen peroxide micro-etching system is easily polluted by chloride ions, and can effectively improve the problem that hydrogen peroxide is easily decomposed by replacing sulfuric acid hydrogen peroxide with an alkaline substance. And the micro-etching rate is stable.

The invention relates to the technical field of OLED (Organic Light Emitting Diode) manufacturing process etching processes, in particular to a silver etching solution for an OLED manufacturing process as well as a preparation method and application of the silver etching solution. The silver etching liquid comprises nitric acid, phosphoric acid, a buffer agent, a metal ion chelating agent and an ionic liquid inhibitor, the ionic liquid inhibitor comprises 1-butyl-3-methylimidazole phosphate, the metal ion chelating agent is selected from at least one of pyromellitic acid, diethylenetriamine pentaacetic acid and ethylenediamine tetramethylene phosphoric acid, and the buffer agent is selected from at least one of sodium chloride, sodium chloride and sodium chloride. The buffering agent comprises acetic acid, and all the components are prepared according to a specific mass ratio. The etching solution can balance the etching rate of silver and indium tin oxide, avoid silver residues and black spot defects, prolong the service life of the solution, reduce the use of a volatile buffer agent, adapt to the OLED fine manufacturing process, improve the product yield and reduce the production cost, and is suitable for etching of a metal substrate in the OLED manufacturing process.

The invention discloses a self-adaptive etching control method for automobile circuit board manufacturing, and relates to the technical field of automobile circuit board manufacturing. The self-adaptive etching control method for manufacturing the automobile circuit board comprises the following steps: S1, real-time multi-source sensing: synchronously acquiring a copper layer etching rate, a three-dimensional shape and a bath solution temperature gradient through a multispectral confocal unit, an ultrasonic thickness measuring unit and a distributed temperature sensing unit which are integrated in an etching bath; s2, dynamic decision analysis; s3, multi-parameter cooperative execution: independently adjusting the pressure gradient, the atomization particle size and the oscillation frequency through a spraying pressure regulation and control unit, an etching agent atomization unit and a mechanical oscillation unit; s4, closed-loop process verification: feeding back etching uniformity, and dynamically correcting the decision model; through the steps of real-time multi-source sensing, dynamic decision analysis, multi-parameter cooperative execution and closed-loop process verification, accurate control over the automobile circuit board etching process is achieved, and the etching quality and efficiency are improved.

The invention discloses a super-lens design method based on etching uniformity compensation and an optimization system thereof. The super-lens design method specifically comprises the following steps: S1, etching a wafer and establishing an etching rate space distribution model; S2, designing layout partitions and distributing compensation coefficients; s3, pre-compensating the size of the nano structure; s4, generating a final mask and executing etching; according to the method, the space size pre-compensation of the nano structure is actively performed in the mask design stage, and the phase deviation caused by non-uniform etching depth is counteracted by using the change of the effective refractive index of the nano unit, so that the high-performance super lens is obtained under the non-ideal process condition, and the limitation of the process physical limit is broken through.

A method of fabricating an array substrate and an array substrate are disclosed. The array substrate includes a bonding portion, the bonding portion being fabricated by: providing a substrate, and forming a metal layer on the substrate; sequentially depositing a first and a second insulating layer material on the metal layer; etching the first and second insulating layer material respectively at a first etching rate and a second etching rate to form a first insulating layer having a first via hole and a second insulating layer having a second via hole, respectively, thus obtaining a composite insulating layer of a double-layer structure; forming on the composite insulating layer an electrode layer connected to the metal layer through the first and second via holes to form the bonding portion; where the first etching rate and the second etching rate are different, and the first and second via holes are arranged correspondingly.

A method for producing a nanochannel (200) is described with the following steps a) depositing a nanochannel sacrificial layer (3) using an ALD process on a substrate (1), which defines the subsequent channel height at least at one point b) depositing a first covering layer (4) on the nanochannel sacrificial layer (3) c) At least partially structuring and / or etching the nanochannel sacrificial layer (3) and the first cover layer (4) so ​​that a first exposed region (10) is formed d) At least partial etching of the now exposed nanochannel sacrificial layer (3) with an etching rate < 100nm / min, preferably <10nm / min, and particularly preferably <5nm / min and even more preferably <2nm / min, so that an under-etched second exposed region (20) is formed which defines the channel width e) depositing a second cover layer (5) onto the first cover layer (4) and the first exposed region (10) so that the second exposed region (20) is sealed and forms a nanochannel (200).

Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material. The methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

The invention relates to a semiconductor etching BOE waste liquid resource reutilization method, and relates to the technical field of waste liquid treatment and resource recovery, and the semiconductor etching BOE waste liquid resource reutilization method comprises the following steps: S1, waste liquid pretreatment; step S2, silicon removal treatment; s3, removing an additive; step S4, activated carbon adsorption; and S5, component adjustment and refining. The resource recycling method of the BOE waste liquid for semiconductor etching has more excellent additive and metal ion removal rate, and is higher in BOE etching rate and better in surface flatness when being used for a panel.

The invention discloses a high aspect ratio deep silicon etching structure and a patterning method thereof. The patterning method comprises the following steps: providing a substrate made of silicon; forming a plurality of photoresist patterns on the surface of the substrate, wherein an opening is formed between every two adjacent photoresist patterns; bombarding the interface of the substrate at the inner bottom corner of the opening by using plasma of a first gas at a first ultralow temperature to form a first protective film; depositing a polymer layer on the substrate, the photoresist pattern and the first protective film for protection by using plasma of second gas at a second ultralow temperature; etching the polymer layer and the substrate by using plasma of a third gas at a third ultralow temperature; repeating the steps of depositing the polymer layer and etching until a high aspect ratio deep silicon etching structure is formed on the substrate; and removing the photoresist pattern. According to the invention, the uniform protection of the side wall under the conditions of smaller size and higher aspect ratio can be realized, and the etching rate can be improved.

The invention discloses an etching solution and a preparation method and an etching method thereof, and belongs to the technical field of microelectronics and display panel manufacturing. The etching liquid comprises the following components in percentage by mass: 50-70% of phosphoric acid, 5-30% of acetic acid, 5-15% of nitric acid, 0.1-0.5% of a water-soluble polymer, 0.05-0.3% of a boron-containing compound, 0.05-0.5% of an etching control agent and the balance of water. The water-soluble polymer is selected from one or more of water-soluble polymers containing a hydroxyl group, an amide group, an ether bond or a pyrrolidone group. The etching solution contains a specific water-soluble polymer, a protective layer can be formed on the surface of the photoresist, attack of high-concentration acid to the etching solution is effectively inhibited, and the cracking problem is avoided; meanwhile, through the synergistic effect of the boron-containing compound and the azole etching control agent, the etching rate, the slope angle and the key size loss can be accurately controlled, and therefore the excellent etching morphology meeting the requirement is obtained.

The invention discloses a growth method for reducing a Pit defect on a silicon carbide epitaxial surface, which comprises the following steps of: after epitaxial growth is completed, increasing the air flotation flow of a base, increasing the temperature in a reaction chamber, reducing the pressure in the reaction chamber and increasing the hydrogen flow, and entering an etching stage; hydrogen chloride gas is introduced discontinuously in the etching stage, and at least one introduction time period and an interruption time period after the introduction time period are included; the thermal instability of SiC at high temperature / low pressure is utilized, efficient decomposition is achieved through an H2 / HCl synergistic etching system, sub-damage and dislocation are reduced while the etching rate is increased, the thickness of the removed epitaxial layer can be accurately controlled, the Pit defect of the surface layer of the epitaxial layer is reduced, the crystallization quality of the epitaxial layer is kept, and the subsequent power device preparation requirement is met.

The invention relates to an atomic layer etching system and method with a uniformity control mechanism. The ALE process includes a plurality of cycles, each cycle including a surface modification step and a sputtering step. The plasma source includes a center coil and an edge coil. The system supports the use of different selectable configurations in sputtering steps in different ALE cycles, capable of independently activating or closing the center coil and the edge coil. The flexibility provides a mechanism for adjusting the etching rate of the center and the edge of the substrate, so that non-uniformity (such as thickness difference) of the substrate to be processed is compensated. The system controller can generate a process formula based on the to-be-processed substrate data and the output specification so as to ensure that the etching process meets the expected performance requirement.

The invention relates to the technical field of semiconductor cleaning agents, and particularly discloses an etching solution for SiC surface silicon and a preparation method of the etching solution. The etching solution for SiC surface silicon comprises an aqueous solution of a component A and an aqueous solution of a component B. The component A comprises the following raw materials in parts by weight: 3-8 parts of nitric acid, 1-2 parts of hydrofluoric acid, 0.5-1 part of a complexing agent and 0.1-1 part of a surfactant; the raw materials of the component B comprise modified citric acid and citric acid in a mass ratio of (2.2-5.7): (1-1.8), and the modified citric acid is obtained by modifying a dihydroxy compound. The etching solution for the SiC surface silicon has higher selectivity on the SiC substrate surface silicon and other impurities, the etching effect and the etching rate of the etching solution on the SiC surface silicon are effectively improved, the loss of the SiC substrate is reduced, and the problem of environmental pollution is also reduced.

The invention provides an etching method of a double-color second-class superlattice infrared detector, and belongs to the technical field of chip manufacturing. The method comprises the following steps: providing a double-color second-class superlattice infrared detector, and forming a photoresist mask on the surface of the double-color second-class superlattice infrared detector; under the condition that the ratio of the longitudinal etching rate to the transverse etching rate is not less than 5: 1, performing dry etching on the surface of the double-color second-class superlattice infrared detector to obtain an initial mesa structure; the initial mesa structure is subjected to wet etching, a middle mesa structure is obtained, the wet etching time is smaller than or equal to 2 min, and the wet etching temperature is smaller than or equal to 10 DEG C; and post-processing the middle table-board structure to obtain the table-board structure. Through organic combination of a high-anisotropy forming effect of dry etching and a low-damage repairing effect of wet etching, the low surface damage characteristic is considered while high aspect ratio etching is realized, the dark current of the device is fundamentally reduced, and the intrinsic detection performance of the device is improved.

Provided is an etching solution composition capable of preventing reduction in the etching rate of a silicon nitride film, achieving high etching selectivity with respect to silicon nitride, and suppressing deposition of silica on the surface of silicon oxide.　This etching solution composition is based on an inorganic acid and is for selectively etching silicon nitride from a semiconductor containing the silicon nitride and silicon oxide, and comprises: (a) a fluorine compound that increases the etching rate of silicon nitride; and (b) a volatilization inhibitor that inhibits volatilization of the fluorine compound.

The present application provides a composition for forming an anti-reflective coating layer and an application thereof. The composition comprises a first polymer containing epoxy groups, a second polymer containing groups reacting with the epoxy groups and a functional molecule, wherein the functional molecule comprises at least two epoxy groups. The composition for forming the anti-reflection coating is a composition material which is strong in acid and alkali cleaning resistance and has wet etching resistance, the size of a pattern can be protected in the cleaning process, and therefore the stability of a semiconductor device is guaranteed; according to the composition, the etching rate can be adjusted by adjusting the structure of the functional molecules, more accurate control can be achieved in the manufacturing process, and it is ensured that the thickness and uniformity of a coating meet the design requirements.

The invention relates to the technical field of preparation of glass etching solutions, in particular to an anti-dazzle stripping etching solution suitable for high transmittance and a preparation method. The anti-dazzle stripping etching solution suitable for high transmittance comprises a substrate solution, a modified dispersion solution, a regulator and a stabilizer in parts by mass, the preparation method of the modified dispersion liquid comprises the following steps: adding molybdenum disulfide nanoparticles and povidone into an ethanol solution, and carrying out ultrasonic dispersion to obtain the dispersion liquid; adding N-aminoethyl-3-aminopropyl methyl dimethoxy silane into the dispersion liquid, raising the temperature of a reaction system to 60 DEG C, and keeping the temperature and stirring for 1 hour to obtain the modified dispersion liquid. The invention provides the anti-dazzle stripping etching solution suitable for high transmittance and the preparation method, so as to solve the problems that a non-fluorine etching solution in the related technology is relatively low in etching rate and cannot meet the balance of high transmittance and anti-dazzle performance.

The method includes forming a first semiconductor layer and a second semiconductor layer over a substrate; performing a first etching process on the first semiconductor layer and the second semiconductor layer to form a first fin; forming a gate structure across the first fin; performing a second etching process to form a first recess and a second recess in the first fin; removing the first semiconductor layer; depositing a first material layer along the second semiconductor layer and the exposed surface of the substrate; depositing a second material layer over the first material layer; etching the first material layer and the second material layer to form a third groove, wherein the first etching rate of the first material layer is different from the second etching rate of the second material layer; forming an internal spacer in the third groove; and forming a source / drain region in the first recess. The embodiment of the invention also relates to a method for forming the semiconductor device.

The invention provides a trench manufacturing method, which comprises the following steps of: providing a substrate, and sequentially forming an oxide layer and a titanium nitride layer on the substrate; the titanium nitride layers in the different areas are oxidized to different degrees, so that the titanium nitride layers with different thicknesses are oxidized to form titanium oxide layers, and the thickness of the oxidized titanium nitride layers is larger than or equal to zero and smaller than or equal to the thickness of the titanium nitride layers; and etching the titanium oxide layer or / and the titanium nitride layer in each region, the oxide layer below the titanium nitride layer and the substrate in sequence to form grooves with different depths. According to the method, the titanium nitride layers in different areas are oxidized to different degrees, so that the titanium nitride layers with different thicknesses are oxidized to form the titanium oxide layers, namely, the thicknesses of the titanium oxide layers formed in the areas are different, the etching rates of the titanium nitride layers and the titanium oxide layers are different, and the thicker the titanium oxide layers are, the slower the etching is; the depth of the formed groove is shallower, so that grooves with different depths can be formed in the same etching step.

The invention relates to the technical field of etching solutions, and particularly discloses an etching solution for inhibiting etching of metallic titanium and application of the etching solution. The etching solution contains hydrofluoric acid, ammonium fluoride, an additive 1 and an additive 2; wherein the additive 1 is a fluorine capture type inhibitor, and the additive 2 is a surface adsorption type organic protective agent. The etching solution can effectively inhibit the corrosion of a titanium layer while keeping the high etching rate of silicon oxide, obviously improves the etching selection ratio of silicon oxide to titanium, has lower surface tension and higher uniformity, and is suitable for a wet etching scene with a complex structure. The additive 1 captures free fluorine ions through complexation or precipitation, the activity of the fluorine ions is reduced, and therefore the chemical attack on the titanium surface is reduced; and the additive 2 can form a transient adsorption protective film on the titanium surface to further delay the dissolution of titanium. The synergistic effect of the two additives can effectively inhibit titanium corrosion and maintain high etching efficiency.

The invention relates to the technical field of etching solutions, and discloses a molybdenum-aluminum-niobium etching solution for a TFT-LCD (Thin Film Transistor Liquid Crystal Display), which comprises the following components in percentage by mass: 50 to 60 percent of phosphoric acid, 3 to 8 percent of nitric acid, 5 to 10 percent of glacial acetic acid, 1 to 5 percent of aluminum nitrate, 0.1 to 0.5 percent of diphenyl thiourea, 1 to 5 percent of etidronic acid, 3.0 to 5.0 percent of sodium hexametaphosphate, 0.1 to 0.2 percent of fatty alcohol-polyoxyethylene ether, 0.5 to 0.8 percent of amino trimethylene phosphonic acid and the balance of ultrapure water. The invention further discloses a preparation method of the molybdenum-aluminum-niobium etching solution. According to the invention, a phosphorus nitrate vinegar system, a composite additive, a novel corrosion inhibitor, a metal ion chelating agent and a surfactant matched with the etching liquid are adopted, so that the molybdenum-aluminum-niobium multi-layer composite metal film can be simultaneously etched at one time; the etching solution has the advantages of being uniform in etching, capable of inhibiting Mo / Nb etching, high in selectivity, controllable in etching rate, free of residues, long in service life, high in stability and the like.

The invention belongs to the technical field of machining and intelligent manufacturing, and particularly relates to an intelligent regulation and control system and method for discharge energy of a spark machine. Comprising a multi-mode gap state sensing module, a high-throughput data synchronous acquisition and preprocessing module, a discharge pulse real-time classification and feature extraction module, an LSTM-based gap state trajectory prediction module, a multi-target model prediction control module and a high-frequency pulse power supply execution module. By fusing the electrical parameters and the in-situ optical turbidity signal, multi-dimensional perception of the discharge state is realized, the future discharge trend is predicted by using an LSTM network, and an optimal pulse parameter combination is solved online by combining an MPC controller. By the adoption of the technical scheme, dynamic optimal balance of the material corrosion rate, the surface quality and the stability in the machining process can be achieved, and the overall machining benefit is improved.

The invention discloses a cleaning composition as well as a preparation method and application thereof, and relates to the technical field of cleaning fluid. The invention relates to a low-k passivating agent which comprises the following components in percentage by mass: 10%-35% of an alkaline compound, 1%-40% of fluoride, 0.01%-10% of a cyclophosphazene compound, 0.01%-10.00% of a low-k passivating agent, 20%-80% of an organic solvent, 0.0001%-10.00% of a surfactant and the balance of water. By compounding the alkaline compound, the fluoride, the cyclophosphazene compound, the low-k passivator, the organic solvent, the surfactant and the water, various residues generated in the back-end process of semiconductor manufacturing can be effectively removed, and meanwhile, the contacted metal and non-metal materials cannot be obviously corroded. The etching rate on metal materials such as copper, tungsten and tantalum nitride and non-metal materials such as low-dielectric-constant insulating materials (BD) is low, and the operation window is large.