1696 results about "Etching rate" patented technology

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention relates to the technical field of semiconductor manufacturing, in particular to an intelligent manufacturing process optimization method and system of an integrated industrial large model. Dynamic optimal combination solution of technological parameters such as photoetching dose, etching rate and film thickness is realized; an equipment operation instruction and an abnormal intervention strategy are generated in real time, and the accuracy and timeliness of operation are improved; and cross-process collaborative scheduling and bottleneck prediction are carried out, the whole production process is optimized, and finally the yield, efficiency and flexibility of semiconductor manufacturing are improved.

The invention discloses an automatic control etching system and method for a printed circuit board, and relates to the technical field of circuit boards, and the method comprises the following steps: 1, an operator puts a to-be-etched PCB into an etching groove, and inputs target etching parameters through a human-computer interaction interface; 2, the multi-dimensional sensor module continuously monitors key parameters in the etching tank, and data is transmitted to the central controller; 3, according to the data provided by the sensor, the central controller calculates a real-time etching rate by using a nonlinear kinetic model; 4, when the real-time etching rate deviates from the target rate, the system starts an adaptive control algorithm for adjustment; 5, when the system detects that the set etching depth or width reaches a target value, the etching process is automatically stopped, and key data are recorded; and step 6, the system analyzes based on the stored historical data, provides optimal etching parameters and adjustment strategies for different types of PCBs, and displays the data in real time through a human-computer interaction interface module.

The invention relates to an experimental method for manufacturing a through hole by using gray exposure, and aims to realize a through hole structure with a specific inclination angle and depth-to-width ratio through collaborative design of photoetching and etching processes. The method comprises the following steps: determining a through hole angle and a depth-to-width ratio, selecting an etching condition, designing a gray mask structure based on an etching rate selection ratio, implementing gray exposure to obtain a mask pattern, etching, removing residual photoresist and finally forming a target through hole. And by regulating and controlling the selection ratio k of the mask to the substrate material, the inclination angle beta of the through hole and the depth H, designing the gray-scale mask morphology conforming to the target structure. The gray mask can be constructed by adopting gray photoresist or an optical modulation mask, and the inclination morphology parameter, the etching time and the etching rate of the gray mask meet a specific relation, so that high-precision structure control is realized. The method is suitable for the fields of MEMS, micro-optical devices and the like with high requirements on the morphology precision of the through hole, and has the effects of good structure consistency and high process repeatability.

The invention belongs to the technical field of laser processing, and provides a quartz crystal etching solution which comprises the following components in volume concentration: 10-30% of hydrofluoric acid, 1-5% of sulfuric acid, 0.1-0.3% of surfactant and the balance of water. By optimizing the proportion, the manufacturing precision and the production and manufacturing efficiency of the tuning fork wafer are improved. And the stable etching rate and the optimal etching surface are obtained, and meanwhile, the cost is saved for process replacement. The invention further provides a method for cutting the tuning fork of the quartz crystal through the laser. The method comprises the steps that S1, the cutting contour line of the tuning fork is preset on the quartz crystal; s2, performing laser cutting on the quartz crystal based on a preset cutting contour line, and forming a tuning fork contour on the quartz crystal; and S3, integrally soaking the quartz crystal in the quartz crystal etching solution, and separating out the tuning fork. The machining process of the quartz crystal tuning fork is simplified, the cutting quality is optimized, the method is suitable for the large-piece manufacturing process, and the cutting efficiency and the yield are greatly improved.

The invention provides an etching parameter adjusting method and device in MOSFET chip production, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining plasma density distribution data and an etching rate monitoring value of a wafer surface, and dynamically dividing the wafer surface into a plurality of segment independent control units; adjusting a radio frequency power distribution weight, and synchronously adjusting a reaction gas injection parameter; carrying out coupling analysis on the concentration gradient of the etching by-product and the matching degree of the surface morphology of the wafer; and when the deviation of the target value threshold is detected, temperature compensation and air pressure compensation are carried out. According to the method and the device, the technical problem of poor etching precision of the MOSFET chip caused by non-uniform etching rates of different regions in the etching process is solved, and the uniformity of the etching rates is improved through real-time monitoring and dynamic compensation, so that the etching precision of the MOSFET chip is improved.

The invention provides a gas for plasma etching, a gas combination, an etching method and semiconductor equipment, which belong to the field of plasma etching, and are mainly characterized in that one or more of carbonyl halide, aldehyde halide and carboxyl halide are provided as process gases in the etching process to excite and form plasma, and the plasma is used as a plasma source. According to the method, the to-be-etched layer is etched, so that the problem of upper and lower inconsistency caused by large difference between the bottom etching rate and the middle etching rate when a high-aspect-ratio hole or groove is formed by etching to a certain degree is solved, the morphology of high-aspect-ratio etching is remarkably improved, the collimation is ensured, and the effectiveness of the semiconductor structure is improved.

The embodiment of the invention provides a manufacturing method of a semiconductor structure, the semiconductor structure and a CMOS (Complementary Metal Oxide Semiconductor) circuit. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor substrate; wherein the semiconductor substrate comprises a semiconductor substrate, and a buffer layer and a stress layer which cover the semiconductor substrate; the semiconductor substrate comprises an NMOS region and a PMOS region; a PMOS gate structure is formed on the surface of the PMOS region; the buffer layer covering the side surface of the PMOS gate structure and the buffer layer covering the surface of the semiconductor substrate form an adjacent region; removing a part of the stress layer covering the PMOS region in the semiconductor substrate, and forming a stress layer residual part on the surface, far away from the semiconductor substrate, of the adjacent region of the buffer layer; executing an ion implantation process in the PMOS region; wherein the region for executing the ion implantation process comprises a stress layer residual part, so that the etching rate of etching the stress layer residual part is increased; and etching to remove the residual part of the stress layer. According to the embodiment of the invention, the overall electrical performance of the CMOS circuit is improved.

A silicon-containing resist underlayer film forming composition for forming a resist underlayer film which is able to be removed not only by a conventional dry etching method but also by a wet etching method that uses a chemical agent, and which has excellent lithography characteristics, while enabling the achievement of a high etching rate during wet etching. A silicon-containing resist underlayer film forming composition which contains (A) a polysiloxane, (B) nitric acid, (C) a bisphenol compound and (D) a solvent.

The invention relates to an intelligent wafer etching process in the technical field of information, and the process comprises the steps: obtaining the etching rates of different materials under various liquid medicine formulas, constructing an etching rate database covering various material systems, screening out a material combination with high etching selectivity by comparing the etching rate differences in the database, and carrying out the etching of the material combination. Determining a targeted liquid medicine formula optimization direction; a multi-parameter online monitoring unit is installed in etching equipment, the concentration of liquid medicine is measured in real time through an optical fiber spectrometer, the temperature and the pH value of the liquid medicine are measured in real time through a thermocouple and a pH electrode, when monitoring parameters exceed a set range, a liquid medicine proportion adjusting program is started, and dynamic regulation and control over the property of the liquid medicine are achieved by controlling the liquid inlet amount and the liquid outlet amount. And the stability and the consistency of the etching process are ensured.

The invention discloses an integrated circuit equipment data optimization monitoring system and method based on big data, and relates to the technical field of integrated circuit manufacturing. The method is used for solving the problems of insufficient multi-physical field monitoring, difficulty in abnormal traceability and lack of closed-loop control in plasma etching. A plasma sheath thickness inversion model and an etching selection ratio model are constructed by collecting radio frequency reflection phase, mass spectrum ion strength and wafer temperature data, and process parameter-plasma state dynamic coupling is established. Interference image distortion features and electron microscope size data are fused, micro-groove geometric parameters are analyzed, morphology instability risk indexes are generated, and nanoscale early warning is achieved. And designing a dual-channel fusion network, embedding a physical constraint attention mechanism, and generating an etching rate optimization instruction. On the basis of incremental learning, model parameters are updated online, a'monitoring-decision-feedback 'closed-loop system is formed, anomaly detection sensitivity and decision reliability are improved, and technical support is provided for intelligence of integrated circuit equipment.

The invention relates to a method for optimizing electroplating and etching process parameters, which comprises the following steps of: establishing an interface migration behavior relationship by analyzing the influence of metal ions, doped impurities and surface roughness factors on a reaction interface migration rate and a boundary layer flow behavior in an electroplating and etching process; interface migration behaviors are combined with parameter sensitivity analysis, the influence of process parameters on the interface behaviors is dynamically evaluated, and priority optimization sorting is carried out; dynamic interval zooming is carried out on the sensitive parameters by using the fitted sensitivity function, and a local adjustment range is generated according to material types and graph complexity; a preorder process memory mapping relation is introduced, and morphology evolution information recorded in the electroplating process is transmitted to an etching parameter optimization module; local fine adjustment is carried out on the etching rate, angle control and a disturbance mechanism, and the previous electroplating state is responded; collecting a fluctuation interface feedback signal; establishing a closed-loop optimization control loop of micro-disturbance, response evaluation and parameter correction; and the process consistency and the structure uniformity are improved.

The invention discloses a preparation method of a magic angle nano-cavity and a topological body cavity based on a quantum dot single photon source, and the method comprises the steps: carrying out the preprocessing of a substrate, and enabling the substrate to comprise a quantum dot layer, a substrate layer, and a sacrificial layer located between the quantum dot layer and the substrate layer; treating the pretreated substrate by adopting oxygen plasma; photoresist is spin-coated on the surface of the quantum dot layer of the substrate, exposure and development are carried out, and a pattern is formed on the surface of the photoresist; transferring the pattern on the photoresist to the quantum dot layer through etching; and removing the sacrificial layer by wet etching to prepare two photonic crystal cavities, namely a magic angle nano cavity and a topological body cavity. Through fine electron beam exposure dose control, precise inductively coupled plasma gas component and etching rate control and appropriate corrosive liquid concentration and time control, a high-stability and high-repeatability photonic crystal suspension cavity structure, namely a magic angle nano cavity and a topological body cavity, with a line width of 30-50 nm is realized.

The invention relates to the technical field of laser etching, and discloses a high-precision laser etching parameter adjusting method and device, and the method comprises the steps: obtaining basic parameters and preliminary processing parameters of a processing material; according to the preliminary processing parameters, equipment is controlled to perform sample preparation to obtain a processing sample plate of the processing material, and etching depth measurement operation is performed on the surface of a photoetching structure of the processing sample plate to obtain the etching depth of the processing sample plate; performing data processing operation according to the etching depth to obtain an average etching rate; establishing a relation model of laser etching data by utilizing a linear regression formula according to the average etching rate; performing laser power adjustment operation according to the relation model and the basic parameters to obtain a laser power adjustment scheme; and according to the laser power adjustment scheme, completing adjustment of process parameters of all the processing materials. By means of the method, finer technological parameter setting can be achieved, and the high-precision machining requirement is met.

Method to selectively diffuse dipole dopants into the high-k gate dielectric layer is provided. A method of the present disclosure includes an etching back process controlling DC and bias power, a periodical switching of the bias power is synchronized with a periodical switching of the DC power, leading to a balanced etching rate and uniform depth of recesses in dummy materials within the gate trenches for the subsequent selective diffusion process across different devices. Additionally, during the etching back process, a protective passivation layer can be formed as a barrier on the sidewall of the recess and / or at the bottom of the recess.

The invention provides a silicon wafer metal pollution detection method, and particularly relates to the technical field of semiconductors, and the method comprises the steps: carrying out the heating treatment of a silicon wafer, enabling the surface layer of the heated silicon wafer to comprise a first structural defect formed by the heating silicification of a pollution source metal located on the surface layer, the pollution source metal positioned on the surface layer comprises front metal of the silicon wafer, and at least one of body metal and back metal which are heated and diffused to the surface layer of the silicon wafer; performing etching treatment on the heated silicon wafer, wherein the etching speed difference of the etching treatment on the first structural defect and the second structural defect of the silicon wafer meets a preset difference condition; a first structural defect is detected based on a structural defect difference between the heated silicon wafer and the etched silicon wafer. According to the technical scheme, effective detection and positioning of surface metal, body metal and back metal can be achieved at the same time, silicon wafer detection pollution is avoided, and the method is suitable for bare wafers and patterned silicon wafers.

The invention discloses an aluminum-based circuit acidic etching solution, which relates to the technical field of etching, and comprises the following components by mass concentration: 30-60 g / L of composite inorganic acid, 10-20 g / L of a wetting agent, 5-15 g / L of a stabilizer, 5-15 g / L of an accelerator, 6-15 g / L of a brightener, 0.5-2.5 g / L of a composite anti-lateral corrosion agent, and 2-4 g / L of a complexing agent. According to the acid etching solution for the aluminum-based circuit, the lateral etching rate of a 50-75-micron thin circuit can be lower than 30%, the etching rate is stable, the etched appearance is bright and uniform, and the circuit does not have a burr phenomenon; the wetting agent is added, so that the etching uniformity can be improved, the burr phenomenon can be prevented, the adsorption rate of inorganic acid can be increased for the burr part which is difficult to treat, and the corrosion efficiency of the burr part can be improved; by adding the brightener, the phenomena of uneven partial etching and blackening of the surface after etching can be solved.

The present invention discloses a copper-molybdenum metal etching liquid composition, and the raw materials for preparing the composition include a main agent and an auxiliary agent, including hydrogen peroxide, an organic acid, an amino base, a stabilizer, an electrochemical inhibitor, an alcohol additive, and a solvent. The present invention adopts ethylene glycol and an electrochemical inhibitor to synergize, reduce the surface tension between the etching solution and the metal film layer, enhance the adhesion rate of the etching solution and the metal film layer, and can perfectly solve the chamfering problem in the etching process. And by using isobutanolamine and triethanolamine as amino base I, copper ions can be complexed, the decomposition rate of hydrogen peroxide can be stabilized, the etching rate balance can be maintained, and a good etching morphology can be achieved, with excellent Taper angle, CD-Bais, and small variation, so that it can load a copper ion concentration of 12000ppm, and the lower limit of molybdenum residue reaches 0.45μm, with an excellent etching range, meeting the impact of customer process fluctuations on production, and being environmentally friendly, and the cost of waste liquid treatment is low.

To suppress a deviation of an etching rate.SOLUTION: A plasma processing apparatus includes a chamber, a bias power supply, a substrate support configured to support a substrate and an edge ring in the chamber, a plurality of first impedance adjusting mechanisms, and an electrical path. The substrate support includes a first region configured to support the substrate, a second region provided around the first region and configured to support the edge ring, a first bias electrode provided in the first region, a plurality of first impedance adjusting electrodes provided in the first region and grounded, and a second bias electrode provided in the second region. The plurality of first impedance adjusting mechanisms are configured to be respectively connected to the plurality of first impedance adjusting electrodes. The electrical path is configured to connect the bias power supply, the first bias electrode, and the second bias electrode.SELECTED DRAWING: Figure 9

In order to solve the problem that an existing BOE etching solution cannot consider the etching rate, the etching uniformity and the service life of the etching solution at the same time, the invention provides a BOE etching solution which comprises the following components: hydrogen fluoride, ammonium fluoride and a corrosion inhibitor, the corrosion inhibitor comprises a compound shown as a structural formula 1: # imgabs0 # structural formula 1, R1 is selected from substituted or unsubstituted C2-C6 alkyl, and R2 is selected from substituted or unsubstituted C2-C6 ether-containing alkyl. The BOE etching solution provided by the invention has a relatively high silicon oxide / silicon nitride and Si etching selection ratio, can effectively improve the etching uniformity, is beneficial to reducing surface defects, and ensures the flatness and smoothness of an etched surface. In addition, the BOE etching liquid is stable in chemical composition and long in service life.

The invention provides a method for forming a groove and semiconductor process equipment, and the method comprises the steps: executing a first etching step, carrying out the downward etching of a to-be-etched film layer of a wafer to a preset depth to form a groove, and enabling the preset depth to be smaller than the target depth of the groove; alternately and circularly executing the first deposition step and the second etching step, and modifying the base angle of the groove into a round angle; wherein in each cycle, the first deposition step is executed to form a passivation layer on the side wall of the groove, the second etching step is executed to etch the groove, and the etching rate of the bottom of the groove is greater than the etching rate of the bottom angle of the groove. According to the scheme, the control difficulty of the groove bottom angle morphology can be reduced, and the control precision can be improved.

Exemplary methods of semiconductor processing may include providing a hydrogen-containing precursor and a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. One or more layers of silicon-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor. The methods may include contacting one or more layers of silicon-containing material with plasma effluents of the hydrogen-containing precursor and the fluorine-containing precursor. The contacting may etch a portion of the one or more layers of silicon-containing material.

The invention discloses a cleaning composition, a preparation method thereof and a cleaning method of etching residues. The cleaning composition comprises the following components in percentage by mass: 1%-25% of an alkaline compound, 0.1%-15% of fluoride, 0.1%-25% of a metal corrosion inhibitor, 0.01%-25% of a cleaning aid and 10%-70% of an organic solvent. According to the cleaning composition disclosed by the invention, the alkaline compound, the fluoride, the metal corrosion inhibitor, the cleaning auxiliary agent and the organic solvent with proper contents are matched with one another, so that etching residues can be effectively removed; meanwhile, obvious corrosion to contacted metal and non-metal materials is avoided, the etching rate to aluminum, silver, titanium, silicon dioxide and the like is low, and an operation window is large; the cleaning composition disclosed by the invention can be used for cleaning etching residues, such as cleaning a silicon-based OLED (Organic Light Emitting Diode) after dry etching, and has an excellent cleaning effect.

The invention provides an ion beam etching system with an etching rate in-situ monitoring function and an etching method, the ion beam etching system is provided with an objective table which can deflect by 90 degrees and an electrical test detection element which can move close to or far away from the objective table, and by the etching method, an ion source is not closed, a sample is not taken out, and the etching rate can be accurately measured. The etching depth can be accurately monitored by measuring the surface resistance of the sample in situ, the etching rate can be reduced in time, and the method is more suitable for the tape-out process. According to the ion beam etching system and the etching method, sputter spectrum monitoring is replaced by sample surface resistance detection, so that the test sensitivity is higher, the system cost is lower, the etching precision in magnetic tunnel junction preparation is greatly improved, the sample is prevented from being excessively etched, the thickness of a sample layer can be kept consistent, the resistance distribution is uniform, and the quality of the magnetic tunnel junction is improved. And the high success rate preparation of the SOT-MRAM memory with large capacity and small size is realized.

The invention relates to the technical field of etching solutions, in particular to the field of IPC C23F, and more particularly relates to a double-agent copper-molybdenum-titanium etching solution and a preparation method thereof. Comprising a main agent and an auxiliary agent, and the main agent comprises the following components in parts by weight: 8-15 parts of an oxidizing agent, 4-13 parts of first organic acid, 1-3 parts of first inorganic acid, 1-3 parts of first organic alkali, 1-4 parts of a first surfactant, 0.05-0.5 part of a first fluorine-containing compound, 0.01-1 part of a first corrosion inhibitor and 60-80 parts of water; and the auxiliary agent comprises the following components: 10-60 parts of second organic acid, 2-10 parts of second inorganic acid, 1-5 parts of second organic alkali, 0.05-0.5 part of a second fluorine-containing compound, 1-5 parts of a second surfactant, 0.5-2 parts of a second corrosion inhibitor and 50-80 parts of water. The problems of large etching rate fluctuation, chamfering, vertical angle, precipitation, crystallization and the like in the etching process of the etching liquid are solved.

The invention relates to the technical field of plasma etching, and particularly provides a variable-pressure plasma etching system and method and etching equipment, and the system comprises an etching reaction chamber; an etching gas supply assembly; the voltage distribution adjusting assembly is arranged below the wafer to be etched and is used for adjusting the voltage of different etching areas; the etching rate acquisition assembly is arranged in the etching cavity and is used for acquiring the actual etching rate corresponding to each etching area; the controller is used for controlling the voltage distribution adjusting assembly to adjust the voltage of each etching area according to the preset etching rate and the actual etching rate, so that the difference value between the preset etching rate and the actual etching rate of each etching area is adjusted to be within a preset range; the system can effectively solve the problems that a device obtained by a plasma etching process is inconsistent with a target device, the performance of the device is affected and even waste products are generated due to the fact that the distribution uniformity of the etching rate is reduced.

The invention relates to the technical field of semiconductor etching, in particular to a semiconductor etching method based on plasma coordinated regulation, which comprises the following steps: alternately using first plasma and second plasma on a semiconductor to be etched to obtain a plurality of groove structures with a preset depth-to-width ratio, the second plasma is used for cleaning side wall residues; detecting by using a laser interference measurement method to obtain an etching rate ratio and a side wall angle corresponding to each groove structure, and determining corresponding treatment according to the change condition of the etching rate ratio and the side wall angle, including maintaining the etching and cleaning parameters of the current stage, or adjusting the corresponding parameters of the first plasma according to the need, or corresponding parameters of the second plasma are adjusted according to needs. According to the method, the first plasma and the second plasma are cooperatively controlled to adjust the groove structure in each stage, so that the uniformity of the groove structure is improved, and the damage to the surface of the side wall is reduced.

An edge ring for use in a plasma chamber includes a first pair of edge ring segments with each one of the first pair of edge ring segments having a first thickness and a second pair of edge ring segments with each one of the second pair of edge ring segments having a second thickness. Each of the first pair of edge ring segments is oriented adjacent to each of the second pair of edge ring segments and each of the second pair of edge ring segments is oriented adjacent to each of the first pair of edge ring segments.

The invention relates to the technical field of semiconductors and electronic chemicals, and particularly discloses an etching solution for selectively etching silicon nitride and titanium nitride and a preparation method of the etching solution, the etching solution comprises the following components in percentage by mass: 10-45% of phosphoric acid, 1-5% of hydrofluoric acid, 0.5-2.5% of a pH buffer agent, 0.01-1.8% of a solubilizer, 0.1-7% of an etching inhibitor and the balance of water. Wherein the pH buffering agent can effectively stabilize the pH of the etching solution, and the solubilizer can improve the solubility of a solvent in the etching solution, reduce the tension of a solid-liquid phase interface in the solution and promote the transfer rate of interphase substances; the etching inhibitor and metal can form a layer of film on the surface of titanium nitride in a coordination bond mode, and it is guaranteed that silicon nitride and titanium nitride have the high selection ratio. The etching solution provided by the invention can inhibit the etching rate of titanium nitride under the condition of higher etching rate of silicon nitride, and can ensure that the requirement of high selection ratio of silicon nitride and titanium nitride is met.