57 results about "Anisotropic plasma" patented technology

A method of manufacturing a semiconductor device is disclosed which comprises forming a gate structure on a major surface of a semiconductor substrate with a gate insulating film interposed therebetween, forming a first insulating film to cover top and side surfaces of the gate structure and the major surface of the semiconductor substrate, reforming portions of the first insulating film which cover the top surface of the gate structure and the major surface of the semiconductor substrate by an anisotropic plasma process using a gas not containing fluorine, and removing the reformed portions of the first insulating film.

Methods and apparatuses for dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating by a laser beam with a centrally peaked spatial power profile to form an ablated trench in the substrate below thin film device layers which is positively sloped. In an embodiment, a femtosecond laser forms a positively sloped ablation profile which facilitates vertically-oriented propagation of microcracks in the substrate at the ablated trench bottom. With minimal lateral runout of microcracks, a subsequent anisotropic plasma etch removes the microcracks for a cleanly singulated chip with good reliability.

Methods and apparatuses to etch recesses in a silicon substrate having an isotropic character to undercut a transistor in preparation for a source/drain regrowth. In one embodiment, a cap layer of a first thickness is deposited over a transistor gate stack and spacer structure. The cap layer is then selectively etched in a first region of the substrate, such as a p-MOS region, using a first isotropic plasma etch process and a second anisotropic plasma etch process. In another embodiment, an at least partially isotropic plasma recess etch is performed to provide a recess adjacent to the channel region of the transistor. In a particular embodiment, the plasma etch process provides a recess sidewall that is neither positively sloped nor more than 10 nm re-entrant.

The technology is based on the anisotropic plasma etching of organic polymer sheets partially protected by a metallic mask. The originality of the process is to pattern the surface properties by the same physical means as the one used for the three dimensional fabrication and simultaneously to this fabrication. Surface properties means, but are not limited to hydrophobicity, hydrophilicity, conductivity, reflectability, rugosity and more precisely the chemical and/or physical state of the surface. It is also possible to generate the desired fonctionalities, for instance carboxylic acid, ester, ether, amid or imid, during the etching process. The patterning of the different properties may be achieved by two different techniques that may be used separately or simultaneously.

An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.

A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the opening remain relatively untreated by the plasma. Thereafter, one or more barrier layers may be formed and the opening may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by plasma bombardment or ion implantation using a gas selected from one of O₂, an O₂/N₂ mixture, H₂O, or combinations thereof.

A method of anisotropic plasma etching of a silicon wafer, maintained at a temperature from −40° C. to −120° C., comprising alternated and repeated steps of:

• • etching with injection of a fluorinated gas, into the plasma reactor, and
  • passivation with injection of silicon tetrafluoride, SiF₄, and of oxygen into the plasma reactor, the flow rate of the gases in the plasma reactor being on the order of from 10% to 25% of the gas flow rate during the etch step.

A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer. A method is disclosed for forming a layer, protecting exposed surfaces of low-k dielectrics. More particularly the method comprises the steps of sealing exposed surfaces of a, preferably porous, low-k dielectric, by forming a protective layer on exposed surfaces during or after the step of patterning openings in the porous dielectric layers. Preferably this protective layer is formed by a N2/O2 plasma treatment of the exposed surfaces.

A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

Misalignment created during a multiple-patterning process is a serious challenge for critical dimension (CD) control and layout design in continuing integrated-circuit device scaling. A number of post-lithography misalignment correction technologies based on the shadow effect are invented for multi-patterning lithographic applications. When applied to transfer patterns from a top layer to an underneath layer, the subtractive shadow effect in anisotropic plasma etching combined with a hard-mask process, will shift the position of features such that the previously produced misalignment can be corrected. Also, additive shadow effect in a sputtering/evaporation process can be used. Misalignment correction methods allow the semiconductor industry to print sub-32 nm (half-pitch) features using the double-patterning technique with currently existing lithographic tools (e.g., 193-nm DUV scanner), therefore postponing the need of expensive next-generation lithography (NGL). The misalignment correction methods can be applied to existing lithography technologies to print features smaller than their physical resolution limits.

A method is provided for detecting an end point, a material transition or a boundary surface during the etching of a semiconductor element, a zone of the semiconductor element having non-homogeneous load carrier density and/or non-homogeneous load carrier polarity, particularly a p-n junction, which has an electrical voltage applied to it during etching, and an electrical current induced by it in this zone is measured, and reaching of this zone during etching is determined from a change in the electrical current. This method is suitable for the detection of the etching end point in gas phase etching, in particular with the aid of the etching gases ClF₃ and/or BrF₃, or in the anisotropic plasma etching of silicon substrates. In addition, a method is provided for etching a semiconductor element using a gaseous etching medium, during which the speed of removal of the semiconductor element is set or changed via a setting of the polarity and/or the density of free load carriers in the semiconductor element. In addition, a device for etching a semiconductor element, which device is suitable for carrying out the two methods described above, is provided.

Disclosed is a method for removing, from a processing target substrate having an insulating film with a predetermined pattern formed thereon, a silicon-containing oxide film formed in a silicon portion of a bottom of the pattern. The method includes: removing the silicon-containing oxide film formed on the bottom of the pattern by ionic anisotropic plasma etching using plasma of a carbon-based gas; removing a remaining portion of the silicon-containing oxide film after the anisotropic plasma etching, by chemical etching; and removing a residue remaining after the chemical etching.

The invention relates to a method for forming a pattern on a substrate (S) with an upper surface and a lower surface which comprises the steps of depositing a first layer (E1) of an opaque material on the upper surface of the substrate (S), depositing a photosensitive layer (R) such that part of the photosensitive layer (R) covers at least part of the first layer (E1), exposing the photosensitive layer (R) to a light beam (L), the light beam (L) impinging on the lower surface of the substrate (S) under an oblique angle (Φ) of incidence, removing the exposed region of the photosensitive layer (R), depositing a second layer (E2) of an opaque material such that part of the second layer (E2) covers a remaining region of the photosensitive layer (R), and removing at least a part of the remaining region of the photosensitive layer (R). According to another aspect of the method of the invention anisotropic plasma etching is applied from above the upper surface of the substrate (S) after removal of the exposed region of the photosensitive layer (R) and thereafter the second layer (E2) is deposited. The method of the invention can be applied for forming a source electrode and a drain electrode of a thin-film field effect transistor. The invention furthermore relates to an electronic device fabricated by such a method.

A method for manufacturing separated micromechanical components situated on a silicon substrate includes the following steps of a) providing separation trenches on the substrate via an anisotropic plasma deep etching method, b) irradiating the area of the silicon substrate which forms the base of the separation trenches using laser light, the silicon substrate being converted from a crystalline state into an at least partially amorphous state by the irradiation in this area, and c) inducing mechanical stresses in the substrate. In one specific embodiment, cavities are etched simultaneously with the etching of the separation trenches. The etching depths can be controlled via the RIE lag effect.

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, the exposed regions of the semiconductor wafer are cleaned with an anisotropic plasma process non-reactive to the exposed regions of the semiconductor wafer. Subsequent to cleaning the exposed regions of the semiconductor wafer, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant carbohydrate. In one embodiment, conforming ARC fluid is spun-on and hardened. A selective, dry plasma etches the hardened ARC over the sacrificial oxide while leaving intact part of the ARC that adheres to the trench fill sidewall. The remnant sidewall material defines a protective shroud which delays the subsequent isotropic etchant (e.g., wet HF solution) from immediately reaching the sidewall of the trench fill material. The delay length of the shroud can be controlled by tuning the etchback recipe. In one embodiment, the percent oxygen in an O₂ plus Cl₂ plasma and/or bias power during the plasma etch is used as a tuning parameter.

The invention provides a dry etching preparation method of a T-shaped hole of an integrated circuit. The method comprises the following steps: (1) manufacturing of a micropore etching window, carrying out primary photoetching on an isolation medium layer for metal interconnection and manufacturing the micropore etching window; (2) primary etching, carrying out micropore primary etching by an anisotropic plasma dry etching process, wherein the micropore depth after primary etching is smaller than the thickness of the isolation medium layer; and the difference between the thickness of the isolation medium layer and the depth of a micropore after primary etching is equal to the thickness of a macropore of the T-shaped hole; (3) manufacturing of a macropore etching window, carrying out degumming by a plasma dry degumming technology to form a macropore etching window; (4) secondary etching, carrying out secondary etching by the etching technology same as that in the step (2), wherein the secondary etching time is shorter than the primary etching time; and (5) degumming, removing a photoresist by the plasma dry degumming technology. The preparation method is simple; and etching of the T-shaped hole can be finished only by one piece of etching equipment, so that the production cost is reduced.

The invention provides a method of restraining a notch appearing at the bottom of a hole during an etching process, and a hole structure forming method. The hole structure forming method mainly comprises the following steps: (1) a substrate is provided, wherein the substrate comprises an to-be-etched material layer and an insulated layer attached to the lower surface of the to-be-etched material layer; (2) the to-be-etched material layer is subjected to anisotropic plasma etching, and a hole is formed initially; and (3) in a relatively-low working air pressure environment, anisotropic plasma etching is continued to deepen the hole. At least when the process of deepening the hole is over, the insulated layer can be exposed through the hole.