913results about How to "Increase etch rate" patented technology

The disclosed fabrication methodology addresses the problem of creating low-cost micro-electro-mechanical devices and systems, and, in particular, addresses the problem of delicate microstructures being damaged by the surface tension created as a wet etchant evaporates. This disclosure demonstrates a method for employing a dry plasma etch process to release encapsulated microelectromechanical components.

The present invention provides a plasma processing method and a plasma processing apparatus. The plasma processing method enables consistent processing by realizing a high selectivity and a high etching rate when etching a laminated film using a boron-containing amorphous carbon film, realizes high throughput including prior and post processes by simplifying a mask forming process, and has shape controllability of vertical processing. In the present invention, in a plasma processing method for forming a mask by plasma-etching a laminated film including an amorphous carbon film containing boron, the boron-containing amorphous carbon film is plasma-etched by using a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrafluoride gas, or a mixed gas of an oxygen gas, a fluorine-containing gas, a halogen gas, and a silicon tetrachloride gas.

An apparatus and method for providing an etching gas source for etching one or more microstructures located within a process chamber. the apparatus has a gas source supply line attached to a gas source and one or more chambers for containing an etching material. In use, the etching material is transformed into an etching material vapor within one or more of the chamber and the gas supply line provides a supply of carrier gas to the etching material vapor and also supplies the etching material vapor transported by the carrier gas to the process chamber. Advantageously, the apparatus of the invention does not require the incorporation of any expansion chambers or other complicated mechanical features in order to achieve a continuous flow of etching gas.

A method for selective etching of an SiGe mixed semiconductor layer on a silicon semiconductor substrate by dry chemical etching of the SiGe mixed semiconductor layer with the aid of an etching gas selected from the group including ClF₃ and/or ClF₅, a gas selected from the group including Cl₂ and/or HCl being added to the etching gas.

A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r₁ of the sacrificial oxide film is higher than an etching rate r₂ of the buried oxide layer during the etching.

A cleaning process for cleaning a thermal processing apparatus includes: a heating step of heating an interior of a reaction tube at 300° C., and a cleaning step of removing deposits deposited in the thermal processing apparatus. In the cleaning step, a cleaning gas containing fluorine gas, chlorine gas and nitrogen gas is supplied into the interior of the reaction tube heated at 300° C. to remove silicon nitride so to clean an interior of the thermal processing apparatus.

High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.

The disclosed cover glass is produced by etching a glass substrate that has been formed by a down-drawing process, and chemically strengthening the glass substrate to provide the glass substrate with a compressive-stress layer on the principal surfaces thereof. The glass substrate contains, as components thereof, 50% to 70% by mass of SiO₂, 5% to 20% by mass of Al₂O₃, 6% to 30% by mass of Na₂O, and 0% to less than 8% by mass of Li₂O. The glass substrate may also contain 0% to 2.6% by mass of CaO, if necessary. The glass substrate has an etching characteristic in which the etching rate is at least 3.7 μm/minute in an etching environment having a temperature of 22° C. and containing hydrogen fluoride with a concentration of 10% by mass.

The present invention provides a plasma reactor having a plasma source chamber capable of generating a high density plasma typically utilizing a helicon wave. The plasma is delivered to a process chamber having a workpiece. The present invention may provide a plurality of magnets, each being located longitudinally around an axis perpendicular to the plane of the workpiece to form a magnetic bucket that extends the length of the side wall of the processing chamber and across a workpiece insertion opening and a vacuum pump opening. The magnetic bucket of the present invention may be formed so that the pedestal need not be raised to be within the bucket, or may be formed by permanent magnets oriented with one pole of each magnet facing the interior of the processing chamber, or with opposite poles of adjacent magnets facing each other, thereby forming cusps around the axis perpendicular to the plane of the workpiece. Current carrying conductors may generate all or part of the magnetic bucket. The present invention may provide an inner wall member secured within the processing chamber. All or a portion of the inner wall may be grounded to provide a well defined anode for bias power that is applied to the workpiece pedestal, and may be heated so that deposits do not cause its impedance to drift.

It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.

In a method for manufacturing a compound semiconductor device, a principal surface of a SiC wafer, on which a compound semiconductor device is located, is bonded to a support substrate with an adhesive having a softening point higher than 200° C. A via hole is formed dry etching, including supplying a fluorine-containing etching gas to a rear side of the SiC wafer. Thereafter, the support substrate and the adhesive are removed. Preferably, the adhesive is formed by reacting one material coating the principal surface of the SiC wafer, and another material coating the support substrate.

To provide an EUV mask blank provided with a low reflective layer, which has excellent properties as an EUV mask blank. A reflective mask blank for EUV lithography comprising a substrate, and a reflective layer for reflecting EUV light, an absorber layer for absorbing EUV light and a low reflective layer to an inspection light (wavelength: 190 to 260 nm) for a mask pattern, formed in this order on the substrate, wherein the low reflective layer has a stacked structure having a first layer containing at least 95 at % in total of silicon (Si) and nitrogen (N), and a second layer containing at least 95 at % in total of tantalum (Ta), oxygen (O) and nitrogen (N) or a second layer containing at least 95 at % in total of tantalum (Ta) and nitrogen (N), stacked in this order from the absorber layer side.

The present invention relates to an antireflective coating composition comprising a crosslinking agent, a polymer comprising at least one chromophore group and at least one hydroxyl and/or a carboxyl group, and an additive, further where the additive has structure 1 and comprises at least one arylene-hydroxyl moiety,

where Y is selected from an carboxylate anion or sulfonate anion, R₁, R₂, and R₃ are independently selected from unsubstituted C₁-C₈ alkyl, substituted C₁-C₈ alkyl, aryl and arylene-hydroxyl; X₁, X₂, and X₃ are independently selected from direct valence bond and C₁-C₈ alkylene group, and, n=1, 2 or 3. The invention further relates to a process for using the composition.

A method of forming a contact structure and a contact structure so formed is described. The structure contacts an underlying layer of a semiconductor junction, wherein the junction comprises the underlying layer of a semiconductor material and is separated from an overlying layer of semiconductor material by creating an undercut region to shade subsequent metal formation. Various steps are performed using inkjet printing techniques.

The manufacturing method of the solar cell according to the present invention includes: 1) a first etching process in which an anisotropic etching is performed on an inner wall of each of a plurality of through holes, and 2) a second etching process in which an anisotropic etching is performed on a light-receiving surface. In the first etching process, a high concentration NaOH water solution (about 5% by weight) is used. Meanwhile, in the second etching process, a low concentration (about 1.5% by weight) NaOH water solution is used.

Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.