3results about How to "Etch rate reduction" patented technology

A thin film forming method according to one aspect of the present invention comprises the following steps: supplying a source gas containing a metal and a reaction gas for reacting with the source gas through a gas injection unit on a substrate placed on a substrate support frame in a process chamber, and supplying power through a plasma power unit to form a plasma environment in the process chamber, thereby pre-depositing a metal thin film on the substrate for a first time period; cutting off the power of the plasma power unit, and supplying the source gas and the reaction gas to the substrate for a second time period to pre-treat the substrate; supplying the source gas and the reaction gas on the substrate, and supplying power through the plasma power unit to form a plasma environment in the process chamber, thereby mainly depositing a metal thin film on the substrate for a third time period.

The present invention relates to a method for manufacturing a yttrium oxide thermal spray coating film, and more particularly, to a method for manufacturing a yttrium oxide thermal spray coating film, which forms a yttrium oxide thermal spray coating film on a substrate by disposing a spray unit at a distance of 50-130 mm from the substrate and performing atmospheric plasma spray of a Y2O3 thermal spray powder, and supplying water together with the powder for Y2O3 thermal spraying at a speed of 50 ml / m to 400 ml / m from a position 25 mm to 50 mm from a plasma forming nozzle, thereby manufacturing the powder for Y2O3 thermal spraying, which has low porosity, is very dense, and has excellent plasma resistance.

The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, comprising: providing a substrate, the substrate crossing an adjacent array region and a peripheral region; forming a first mask layer on the substrate in the array region and the peripheral region, wherein the first mask layer in the array region has a plurality of openings, and the openings pass through the first mask layer; forming a filling layer, the filling layer covers the top surface of the first mask layer and fills the openings; forming a second mask layer on the filling layer in the peripheral region; removing the filling layer higher than the top surface of the first mask layer in the array region under a first bias power condition by using a first etching process; removing the remaining filling layer in the array region under a second bias power condition by using a second etching process; and wherein the first bias power is greater than the second bias power. The embodiment of the present disclosure is at least beneficial to improve the performance and yield of the formed semiconductor structure.