1results about How to "Etch rate reduction" patented technology

The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, comprising: providing a substrate, the substrate crossing an adjacent array region and a peripheral region; forming a first mask layer on the substrate in the array region and the peripheral region, wherein the first mask layer in the array region has a plurality of openings, and the openings pass through the first mask layer; forming a filling layer, the filling layer covers the top surface of the first mask layer and fills the openings; forming a second mask layer on the filling layer in the peripheral region; removing the filling layer higher than the top surface of the first mask layer in the array region under a first bias power condition by using a first etching process; removing the remaining filling layer in the array region under a second bias power condition by using a second etching process; and wherein the first bias power is greater than the second bias power. The embodiment of the present disclosure is at least beneficial to improve the performance and yield of the formed semiconductor structure.