6results about How to "Improve etch selectivity" patented technology

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.

The application relates to the technical field of semiconductor and electronic chemicals, and particularly discloses an etching solution for selectively etching silicon nitride and titanium nitride and a preparation method thereof. The etching solution contains the following components in percentage by mass: 10-45% of phosphoric acid, 1-5% of hydrofluoric acid, 0.5-2.5% of a pH buffer, 0.01-1.8% of a solubilizer and 0.1-7% of an etching inhibitor, and the rest is water. The pH buffer can effectively stabilize the pH of the etching solution, the solubilizer can improve the solubility of the solvent in the etching solution, reduce the tension of the solid-liquid phase interface in the solution and promote the transmission rate of the interphase substances, and the etching inhibitor can form a film on the surface of the titanium nitride in the form of a coordination bond, so that the silicon nitride and the titanium nitride have a high selectivity ratio. The etching solution can inhibit the etching rate of the titanium nitride under the condition of a high etching rate of the silicon nitride, and can ensure the high selectivity ratio of the silicon nitride and the titanium nitride.

The invention provides a high-selection-ratio etching solution for SiGe laminations with different germanium contents and a use method, and the high-selection-ratio etching solution comprises the following components in percentage by mass: 0.1 to 20 percent of quaternary ammonium hydroxide, 0.00001 to 1 percent of oxidant, 0.0001 to 10 percent of inhibitor, 0.5 to 40 percent of solvent and the balance of water. The etching solution disclosed by the invention has a high etching rate for low-germanium-content SiGe, and is extremely slow in etching for high-germanium-content SiGe, so that the etching selection ratio of low-germanium / high-germanium SiGe is up to 60. The etching solution provided by the invention is suitable for a microelectronic device to selectively remove SiGe with low germanium content from SiGe laminations with different germanium contents.

The present disclosure relates generally to transistor source / drain contacts and methods of forming the same. In one embodiment, a device includes a gate structure over a channel region of a substrate, a gate mask over the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing along a direction extending from an upper region of the gate mask to a lower region of the gate mask, a gate spacer on sidewalls of the gate mask and sidewalls of the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing along a direction extending from an upper region of the gate spacer to a lower region of the gate spacer, and a source / drain region adjacent to the gate spacer and the channel region.

The present invention relates to an etching composition and a method for manufacturing a semiconductor device using the same, the etching composition comprising an inorganic acid and a silanol-based compound, and the content of the silanol-based compound in the etching composition and the viscosity of the etching composition satisfying formula 1, according to the present invention, a sufficient etching selection ratio of a nitride film with respect to an oxide film can be ensured while suppressing abnormal growth in a high-temperature wet etching process, and bubbles are not immediately generated after manufacturing, so that deterioration of etching process efficiency or damage to etching equipment are not caused, and excellent processability is achieved due to low viscosity.

A method of manufacturing a semiconductor device includes forming a first conductor structure on a substrate, forming a first spacer on sidewalls of the first conductor structure, forming a sacrificial layer on sidewalls of the first spacer, forming a second spacer on sidewalls of the sacrificial layer, forming a second conductor structure adjacent to the second spacer, and removing the sacrificial layer to form an air gap. The method of removing the sacrificial layer to form the air gap includes providing a first gas to form at a first pressure in a first stage, providing a second gas and the first gas to form at the first pressure in a second stage, providing a third gas, the second gas, and the first gas to form at the first pressure in a third stage, and providing the first gas to form at a second pressure in a fourth stage, wherein the second pressure is lower than the first pressure. The sacrificial layer is removed in the third stage. The stability of the vapor etching process is improved to improve the etching selectivity, thereby reducing the loss of the spacer to improve the yield of the semiconductor device.