27results about How to "Improve etch selectivity" patented technology

The invention relates to the technical field of semiconductors and electronic chemicals, and particularly discloses an etching solution for selectively etching silicon nitride and titanium nitride and a preparation method of the etching solution, the etching solution comprises the following components in percentage by mass: 10-45% of phosphoric acid, 1-5% of hydrofluoric acid, 0.5-2.5% of a pH buffer agent, 0.01-1.8% of a solubilizer, 0.1-7% of an etching inhibitor and the balance of water. Wherein the pH buffering agent can effectively stabilize the pH of the etching solution, and the solubilizer can improve the solubility of a solvent in the etching solution, reduce the tension of a solid-liquid phase interface in the solution and promote the transfer rate of interphase substances; the etching inhibitor and metal can form a layer of film on the surface of titanium nitride in a coordination bond mode, and it is guaranteed that silicon nitride and titanium nitride have the high selection ratio. The etching solution provided by the invention can inhibit the etching rate of titanium nitride under the condition of higher etching rate of silicon nitride, and can ensure that the requirement of high selection ratio of silicon nitride and titanium nitride is met.

The invention discloses a protection liquid for green light cutting and a preparation method and application thereof.The protection liquid is prepared from, by mass, 20-40 parts of water-soluble resin, 0.25-0.5 part of a green light absorbent and 50-100 parts of a solvent; wherein the water-soluble resin comprises water-soluble polyester and sodium polystyrene sulfonate; the green light absorbent comprises allura red and lac acid. The water-soluble resin is not easy to etch, the etching selection ratio is high, and the etching depth required by the base material can be met under the condition that the loss of the protective film layer is minimum; the relatively high solubility of sodium polystyrenesulfonate is beneficial to improving the solid content of the resin, improving the thickness of a film layer and improving the stability of the protection liquid; besides, the green light absorbent adopts the combination of allura red and lac acid, so that the solution stability and the light stability of the green light absorbent can be ensured, the addition amount of the absorbent is increased, and the absorbance is improved.

A wafer cleaning solution and a method for forming a semiconductor structure wherein the wafer cleaning solution comprises a mixed solution of an oxidizing agent, a cationic surfactant and water, and the wafer cleaning solution is used for removing a hard mask layer formed by a carbon-doped tungsten material after an etching process and enhancing the dispersibility of carbon in the solution, thereby reducing the adhesion of carbon on the surface of a wafer and improving the quality of the wafer. And the dissolution of carbon is promoted, so that the cleanliness of the wafer surface is improved.

The embodiment of the invention discloses a manufacturing method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) device region and a PMOS (P-channel Metal Oxide Semiconductor) device region; forming a high dielectric constant dielectric layer covering the NMOS device region and the PMOS device region above the substrate; forming a gate stack structure above the high dielectric constant dielectric layer, wherein the gate stack structure is located in the NMOS device region and the PMOS device region; patterning the high-dielectric-constant dielectric layer to reserve the high-dielectric-constant dielectric layer in the NMOS device region and the high-dielectric-constant dielectric layer covered by the gate stack structure in the PMOS device region; and after isolation side walls are formed on the side walls of the gate stack structure to define boundaries of sigma trenches, forming the sigma trenches between the isolation side walls of the gate stack structure in the PMOS device region by using an etching process by taking the patterned high-dielectric-constant dielectric layer as a mask. According to the embodiment of the invention, the height difference between the pseudo gate of the PMOS device region and the pseudo gate of the NMOS device region is eliminated.

The technology relates to a semiconductor device using a hard mask and a method for manufacturing the same, wherein the semiconductor device includes a hard mask that is easy to strip and can realize a fine pattern with high etching selectivity. According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming an etching target layer; forming a hard mask layer on the etching target layer, the hard mask layer including a first boron-doped silicon layer and a second boron-doped silicon layer on the first boron-doped silicon layer; and etching the etching target layer using the hard mask layer as an etching barrier layer, wherein the second boron-doped silicon layer has a greater boron concentration than the first boron-doped silicon layer.

An embodiment of the present invention discloses a dry etching method and semiconductor process equipment, wherein the dry etching method is used to selectively etch a SiGe layer from a stacked structure including alternately stacked Si layers and SiGe layers, and the method comprises: performing plasma etching on the stacked structure using a process gas to selectively remove the SiGe layer from the stacked structure, wherein the process gas comprises a fluorine-containing gas and an auxiliary etching gas, the auxiliary etching gas comprises an oxygen element, and the auxiliary etching gas also comprises at least one of a nitrogen element, a helium element, and an argon element.

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a first dielectric layer on the substrate; forming a first stop layer on the first dielectric layer, wherein a first opening is formed in the first stop layer; forming a second dielectric layer on the first dielectric layer and the first stop layer; forming a mask structure on the second dielectric layer, wherein the mask structure is internally provided with a second opening; the second dielectric layer is etched with the second opening as a mask, a first groove is formed in the second dielectric layer, and a part of the surface of the first stop layer is exposed out of the first groove; the first dielectric layer is etched with the first groove and the first stop layer as masks, a second groove is formed in the first dielectric layer, the second groove is communicated with the first groove, the second groove is exposed out of the surface of the substrate, and the projection range of the second groove on the substrate is located in the projection range of the first groove on the substrate; and forming a metal structure in the first groove and the second groove. The performance of the semiconductor structure formed by the method is improved.

The invention provides an HfO2 / IGZO etching solution with a high selection ratio. The HfO2 / IGZO etching solution with the high selection ratio is prepared from 1%-10% of hydrofluoric acid, 10%-50% of organic acid, 0.5%-5% of a chelating agent, 0.01%-0.5% of a cationic surface active agent and the balance water. Wherein the organic acid can effectively reduce the F <-> content in a system and inhibit the etching rate of IGZO, so that the selective etching of the etching solution to HfO2 is improved. The chelating agent and organic acid can serve as a synergistic acid system, and the dissolving capacity of Hf < 4 + > is further improved. The HfO2 / IGZO selection ratio of the high-selection-ratio etching solution disclosed by the invention is higher than or equal to 4.1, and the HfO2 etching rate can reach 11 / s.

The present application discloses a micro-electromechanical structure and a manufacturing method thereof, a wafer, a microphone and a terminal. The manufacturing method comprises: forming a first back plate above a substrate; forming a second sacrificial layer on the first back plate; forming a diaphragm on the second sacrificial layer, the diaphragm extending to the substrate along the side wall of the second sacrificial layer and the side wall of the first back plate; and removing part of the second sacrificial layer, with the remaining second sacrificial layer serving as a second supporting portion. The manufacturing method reduces the risk of the release liquid corroding the side wall of the second sacrificial layer during the release process by allowing the diaphragm to cover the side wall of the second sacrificial layer.

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate having a plurality of discretely arranged fins on the substrate; an isolation layer located on the substrate and covering a portion of the sidewall surface of the fin; a dummy gate structure located on the substrate and spanning the fin, and the dummy gate structure is arranged along the extension direction of the fin; an interlayer dielectric layer located on the substrate and having a top surface flush with the top surface of the dummy gate structure; a first trench located in the interlayer dielectric layer and the dummy gate structure, and the first trench penetrates the dummy gate structure along the extension direction of the fin; a second trench in the isolation layer, the first trench located in the dummy gate structure exposes the second trench, and the ratio of the depth of the second trench to the thickness of the isolation layer is 1:3 to 2:3. The semiconductor structure provided by the embodiment of the present invention has a deeper second trench, which can improve the isolation effect of the isolation structure formed subsequently, avoid damage to the metal gate, and improve the performance of the semiconductor structure.

The application relates to the technical field of semiconductor and electronic chemicals, and particularly discloses an etching solution for selectively etching silicon nitride and titanium nitride and a preparation method thereof. The etching solution contains the following components in percentage by mass: 10-45% of phosphoric acid, 1-5% of hydrofluoric acid, 0.5-2.5% of a pH buffer, 0.01-1.8% of a solubilizer and 0.1-7% of an etching inhibitor, and the rest is water. The pH buffer can effectively stabilize the pH of the etching solution, the solubilizer can improve the solubility of the solvent in the etching solution, reduce the tension of the solid-liquid phase interface in the solution and promote the transmission rate of the interphase substances, and the etching inhibitor can form a film on the surface of the titanium nitride in the form of a coordination bond, so that the silicon nitride and the titanium nitride have a high selectivity ratio. The etching solution can inhibit the etching rate of the titanium nitride under the condition of a high etching rate of the silicon nitride, and can ensure the high selectivity ratio of the silicon nitride and the titanium nitride.

The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a manufacturing method thereof. The manufacturing method of the three-dimensional memory comprises the following steps of forming a substrate, wherein the substrate comprises a substrate, a first dielectric layer located on the substrate and a first contact structure penetrating through the first dielectric layer; depositing a first metal material or a polycrystalline silicon material on the first dielectric layer to form a conductive bump electrically connected with the first contact structure, and taking the conductive bump as a lower electrode; forming a storage layer continuously covering the side walls and the top surfaces of the conductive bumps; and depositing a second metal material or a polycrystalline silicon material on the substrate to form an upper electrode covering the storage layer, and forming a storage structure by the lower electrode, the storage layer and the upper electrode together. According to the invention, the storage performance of the three-dimensional memory is effectively improved, the sensitivity, the stability and the reliability of the storage structure are greatly improved, and the service life of the three-dimensional memory is prolonged.

The invention provides a high-selection-ratio etching solution for SiGe laminations with different germanium contents and a use method, and the high-selection-ratio etching solution comprises the following components in percentage by mass: 0.1 to 20 percent of quaternary ammonium hydroxide, 0.00001 to 1 percent of oxidant, 0.0001 to 10 percent of inhibitor, 0.5 to 40 percent of solvent and the balance of water. The etching solution disclosed by the invention has a high etching rate for low-germanium-content SiGe, and is extremely slow in etching for high-germanium-content SiGe, so that the etching selection ratio of low-germanium / high-germanium SiGe is up to 60. The etching solution provided by the invention is suitable for a microelectronic device to selectively remove SiGe with low germanium content from SiGe laminations with different germanium contents.

The invention relates to the technical field of semiconductors and electronic chemicals, and particularly discloses a THOX and TEOS selective etching solution and application, the etching solution comprises the following components by mass: 80-95% of monohydric alcohol, 0.1-1.5% of polyhydric alcohol, 0.02-0.5% of hydrofluoric acid, 0.01-0.2% of organic acid, and the balance of water. According to the invention, the polyol and the organic acid are introduced as additives, so that the etching rates of THOX and TEOS can be obviously reduced, the etching rate of THOX to TEOS can be overturned, and the etching selection ratio is greater than 5. The etching liquid is stable, the contained substances are cheap and easy to obtain, the production cost can be reduced, the substance result is simple, and raw materials which are high in purity and accord with semiconductor use can be obtained on the market.

The present disclosure relates generally to transistor source / drain contacts and methods of forming the same. In one embodiment, a device includes a gate structure over a channel region of a substrate, a gate mask over the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing along a direction extending from an upper region of the gate mask to a lower region of the gate mask, a gate spacer on sidewalls of the gate mask and sidewalls of the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing along a direction extending from an upper region of the gate spacer to a lower region of the gate spacer, and a source / drain region adjacent to the gate spacer and the channel region.

The present invention relates to an etching composition and a method for manufacturing a semiconductor device using the same, the etching composition comprising an inorganic acid and a silanol-based compound, and the content of the silanol-based compound in the etching composition and the viscosity of the etching composition satisfying formula 1, according to the present invention, a sufficient etching selection ratio of a nitride film with respect to an oxide film can be ensured while suppressing abnormal growth in a high-temperature wet etching process, and bubbles are not immediately generated after manufacturing, so that deterioration of etching process efficiency or damage to etching equipment are not caused, and excellent processability is achieved due to low viscosity.

The invention provides a method for etching a semiconductor structure, which comprises the following steps of: providing a substrate which comprises a gate structure, an oxide layer and a first nitride layer beside the gate structure, and carrying out an etching step to remove the first nitride layer and retain the oxide layer, the etching selection ratio of the etching nitride layer to the etching oxide layer is greater than 300.

The present invention relates to a silicon-containing resist underlayer film forming composition and a pattern forming method. The subject of the present invention is to provide a silicon-containing resist underlayer film that has a high effect of suppressing the collapse of ultrafine patterns in a multilayer resist method and has an appropriate etching rate. The solution to this problem is a silicon-containing resist underlayer film forming composition, which contains at least one or more quaternary ammonium salts represented by the following general formula (A-1) and a thermally crosslinkable polysiloxane (Sx). [Chemical 1] In the formula, Ar 1 R represents an aromatic group having 6 to 20 carbon atoms or a heteroaromatic group having 4 to 20 carbon atoms. 11 Z represents an alkyl group, alkenyl group, oxoalkyl group or oxoalkenyl group having 1 to 12 carbon atoms, an aryl group having 6 to 20 carbon atoms, or an aralkyl group or aryloxyalkyl group having 7 to 12 carbon atoms, and some or all of the hydrogen atoms in these groups may be substituted. ‑ It represents an organic or inorganic anion that serves as a counter ion to a quaternary ammonium cation.

The present invention discloses an array substrate and a preparation method thereof, and a display panel, comprising a display area and a bending area, wherein the display area comprises a substrate, a shielding layer, a barrier layer, an active layer and a first source-drain metal layer, wherein the first source-drain metal layer is electrically connected to the active layer through a first sub-contact hole, and the first source-drain metal layer is electrically connected to the shielding layer through a first sub-contact hole and a second sub-contact hole; the present invention uses the active layer and the shielding layer as etching barrier layers, and the contact hole and the first opening and the second opening located in the bending area are prepared by the same yellow light process. Compared with the prior art in which the first opening and the second opening are prepared by a yellow light process respectively, a yellow light process for preparing the second opening is omitted, which is conducive to reducing costs.

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a semiconductor substrate which comprises a first surface; the transistor structure comprises a gate structure, a source electrode region and a drain electrode region, the gate structure is formed on the first surface of the semiconductor substrate, and the source electrode region and the drain electrode region are formed in the semiconductor substrate and are exposed through the first surface; a first hard mask layer disposed on the transistor structure; the interlayer dielectric layer is arranged on the first hard mask layer; the contact hole penetrates through the interlayer dielectric layer and the first hard mask layer and exposes at least one of the gate structure, the source region and the drain region; the etching selection ratio of the material of the interlayer dielectric layer is higher than the etching selection ratio of the material of the first hard mask layer, and the width of the first part of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole far away from the gate structure, the source region or the drain region. Therefore, a contact hole photoetching process window is enlarged, and stray capacitance between the contact hole and the grid electrode is reduced.

A method of manufacturing a semiconductor device includes forming a first conductor structure on a substrate, forming a first spacer on sidewalls of the first conductor structure, forming a sacrificial layer on sidewalls of the first spacer, forming a second spacer on sidewalls of the sacrificial layer, forming a second conductor structure adjacent to the second spacer, and removing the sacrificial layer to form an air gap. The method of removing the sacrificial layer to form the air gap includes providing a first gas to form at a first pressure in a first stage, providing a second gas and the first gas to form at the first pressure in a second stage, providing a third gas, the second gas, and the first gas to form at the first pressure in a third stage, and providing the first gas to form at a second pressure in a fourth stage, wherein the second pressure is lower than the first pressure. The sacrificial layer is removed in the third stage. The stability of the vapor etching process is improved to improve the etching selectivity, thereby reducing the loss of the spacer to improve the yield of the semiconductor device.

The present invention relates to a modified aminosilane copolymer, a silicon nitride etching solution, a preparation method and an application. The copolymer has three alkoxy groups connected to Si atoms and easily hydrolyzed, and the groups can be hydrolyzed under acidic conditions to generate Si-OH bonds, and the Si-OH bonds can be tightly combined with a silicon dioxide layer through van der Waals forces to adhere to and wrap the silicon dioxide layer. The silicon nitride etching solution components include a modified aminosilane copolymer, concentrated phosphoric acid and ultrapure water. The silicon nitride etching solution of the present invention can maintain a high etching selectivity ratio for both silicon dioxide and polysilicon, and can be applied in the field of silicon nitride etching of 3D flash memory chips.

The invention relates to an etching device, which comprises an etching chamber, an opening and closing unit for opening and closing the etching chamber, and a locking unit for selectively constraining the opening and closing unit.

The present application discloses a method for improving the etching selectivity of silicon nitride and silicon oxide and a mask layer etching method, wherein the method for improving the etching selectivity of silicon nitride and silicon oxide comprises: providing a substrate, wherein the substrate comprises a silicon nitride layer and a silicon oxide layer; etching the silicon nitride layer with a phosphoric acid solution, and heating the phosphoric acid solution and the silicon nitride layer and the silicon oxide layer by microwaves during the etching process, wherein the silicon nitride layer is doped with a carbon source, and / or the silicon oxide layer comprises porous silicon oxide, thereby achieving the purpose of improving the etching selectivity of the silicon nitride layer and the silicon oxide layer. Since there is no need to introduce expensive additives into the phosphoric acid solution during the entire etching process to achieve the improvement of the etching selectivity of the silicon nitride layer and the silicon oxide layer, the technical problems of high cost and large pollution existing in the existing methods are solved.

The invention discloses a manufacturing method of a memory device, and the method comprises the steps: providing a substrate which comprises a first region, a second region and a third region, forming a first polycrystalline silicon layer on a pad oxide layer of the first region, forming a second polycrystalline silicon layer above the first polycrystalline silicon layer, forming a third polycrystalline silicon layer on the pad oxide layer of the second region, and forming a second polycrystalline silicon layer above the third polycrystalline silicon layer; a fourth polycrystalline silicon layer is formed on the pad oxide layer in the third region; sequentially forming an etching protection layer and a cap layer on the second polycrystalline silicon layer, the third polycrystalline silicon layer and the fourth polycrystalline silicon layer; removing the etching protection layer and the cap layer in the second region and the third region; forming a first groove in the first region, forming a second groove in the second region, and forming a third groove in the third region; forming an isolation layer on the peripheral sides of the storage unit, the grid electrode of the first logic device and the grid electrode of the second logic device; forming an interlayer dielectric layer; and forming a through hole of the contact hole.

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate; a dielectric layer located on the substrate; a first opening and a second opening located in the dielectric layer, the first opening being located at the top of the second opening, the angle between the sidewall surface of the first opening and the top surface of the dielectric layer being an obtuse angle; and a gate structure located in the first opening and the second opening. The performance of the semiconductor structure is improved.

The processing method includes etching the metal nitride layer with an etchant. The etchant may be, for example, WCl5, WOCl4 or TaCl5. A method for improving the selectivity of the etching process is also disclosed.