1164 results about "Conductive channel" patented technology

A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements. The gate structure also includes a top gate member which interconnects the gate elements at their upper vertical ends to cover the channel elements. Finally, a dielectric layer is provided to separate the conductive channel elements from the gate structure.

In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element. Under another embodiment of the invention, the output node includes an isolation structure disposed in relation to the nanotube channel element so that channel formation is substantially invariant from the state of the output node. Under another embodiment of the invention, the isolation structure includes electrodes disposed on opposite sides of the nanotube channel element and said electrodes produce substantially the same electric field. Under another embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.

Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

A resistive memory device and a fabricating method thereof are introduced herein. In resistive memory device, a plurality of bottom electrodes is disposed in active region of a substrate. Each of the bottom electrodes is disposed to correspond to each of the conductive channels; a patterned resistance switching material layer and the patterned top electrode layer are sequentially stacked on the bottom electrodes. An air dielectric layer exists between the patterned resistance switching material layer and the bottom electrodes. A plurality of patterned interconnections is disposed on the patterned top electrode.

An integrated circuit with conductive channels connecting the bonding pads to alternative surfaces of the IC chip is disclosed. Typically the channels would be formed by reactive ion etching, passivated and then filled with copper or other conductive material. The channels may be formed at alternative points in the wafer processing flow depending on the requirements of the IC. Alternatively the channels may be used for heat sinks; in this case the channel would connect a chip “hot spot” with a conductive package member.

A Mixed-Signal Semiconductor Platform Incorporating Castellated-Gate MOSFET device(s) capable of Fully-Depleted operation is disclosed along with a method of making the same. The composite device/technology platform has robust I/O applications and includes a starting semiconductor substrate of a first conductivity type. One or more isolated regions of at least a first conductivity type is separated by trench isolation insulator islands. Within an isolated region designated for castellated-gate MOSFETs there exists a semiconductor body consisting of an upper portion with an upper surface, and a lower portion with a lower surface. Also within the castellated-gate MOSFET region, there exists a source region, a drain region, and a channel-forming region disposed between the source and drain regions, and are all formed within the semiconductor substrate body. The channel-forming region within the isolated castellated-gate MOSFET region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. One or more of the trench isolated regions may contain at least one type or polarity of logic and/or memory computing device. Alternately or additionally, one or more type of Logic and/or memory device may be incorporated within vertically displaced regions above the active body region of the semiconductor wafer, embedded within Interlevel Dielectric Layers.

The invention is applicable to the field of novel materials, and provides a silicon carbon composite negative electrode material for a lithium ion battery, as well as a preparation method and applications of the material. The negative electrode material is of a nuclear-shell-type composite structure, and consists of nano silicon in the core, amorphous carbon at the middle layer and a one-dimensional nano carbon material at the outermost layer, wherein the amorphous carbon at the middle layer forms an elastic loose surface structure, and thus the circulating performance and multiplying performance of silicon are improved; a network structure built by the one-dimensional nano carbon material at the outermost layer not only plays a role in buffering mechanical stress, but also provides a rapid electric conducting channel for active silicon particles, and improves the circulating performance and multiplying performance of silicon further; and meanwhile, a three-dimensional electric-conducting heat-conducting network formed by the one-dimensional nano carbon material can conduct heat generated by a battery during the discharging process to the space around, and the safety performance of the battery is improved. The preparation method of the silicon carbon composite negative electrode material for the lithium ion battery is simple and feasible in process, environment-friendly and energy-saving, low in cost, and easy for industrialization.

Described are methods of manufacturing a strain-inducing layer in semiconductor devices and structures formed to have such strain-inducing layers. Circuit elements are formed on a semiconductor substrate with conductive channel regions within the semiconductor substrate. Metal silicide contacts are formed on the semiconductor substrate and some are electrically connected to the channel regions. A strain-inducing layer can then be formed over the metal silicide contacts. Further, the strain-inducing layer is then treated with thermal processing, photo-thermal processing, or electron irradiation processing thereby increasing the stress of the strain-inducing layer and induce strain upon the crystal lattice structure in the conductive channel regions within the semiconductor substrate.

A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner.

An electronic device includes a printed circuit board (PCB) including a planar surface conductor, e.g. such as a microstrip transmission line or coplanar transmission waveguide. A surface mount connector portion is mounted to the PCB and includes an electrically conductive header having a cylindrical bore extending therethrough and aligned normal to the PCB, the electrically conductive header also having a radially extending main recess in a bottom end thereof in communication with the cylindrical bore. An electrically conductive pin extends through the main recess and has a first end coupled to the planar surface conductor, a second end within the cylindrical bore and a bend therebetween. A dielectric is in the main recess between the pin and adjacent portions of the electrically conductive header, and an interconnect is within the cylindrical bore and includes a center conductive channel to receive the second end of the pin.

The present invention relates to increasing the permeability of a subterranean formation by forming a resinous mass having conductive channels through which fluids can be produced in the formation. Some embodiments of the present invention provide methods of creating a permeable resinous mass comprising the steps of selecting an interval along a well bore; providing a resin slurry comprising an acid curable resin, filler, and degradable material; placing the resin slurry into the selected interval; and, activating the acid curable resin using an activator wherein the activation causes the acid curable resin to substantially cure, the degradable material to substantially degrade, and forms the permeable resinous mass.

The invention relates to a semi-active control magnetorheological hydraulic mount for an automotive powertrain, which belongs to a semi-active control element used for vibration control of an engine and is an engine mount filled with magnetorheological fluid, wherein the viscosity of the fluid changes along with the change of the strength of a magnetic field, and the semi-active control magnetorheological hydraulic mount mainly comprises a metal framework, a rubber main spring, a coil holder, an electromagnetic coil, a magnetic conductive channel body, an inertia channel assembly, a rubber basement membrane, a bottom framework and the like, and can control the strength of applied current according to the working condition of the engine by utilizing the viscosity of the magnetorheological fluid and the following performance of the strength of the magnetic field, further change the viscosity of the fluid, lead the vibration of the engine to be well attenuated in a wider frequency band and further actively isolate the transfer of vibration noise of the engine into an automobile in the wider frequency band. A vibration damper for the magnetorheological hydraulic mount for the engine can effectively isolate the vibration of the engine, reduce the noise in the automobile and improve the NVH properties of the whole automobile, thereby having great market potential and broad prospects.