376 results about "Conductive channel" patented technology

The invention discloses a modified graphite felt electrode for an all-vanadium redox flow battery and a preparation method of the modified graphite felt electrode, and belongs to the technical field of redox flow battery electrode materials. The preparation method comprises the following steps: graphite felt electrochemical oxidation etching treatment; self-assembling a conductive layer on the oxidized and etched graphite felt to obtain the graphite felt attached with the conductive layer; and loading a metal and nitrogen-doped carbon (M and NC) nano catalyst layer on the graphite felt attached with the conductive layer to obtain the modified graphite felt electrode. Various properties of the graphite felt are comprehensively improved through matrix treatment, structure change and load catalysis, mild electrochemical oxidation etching is adopted, a carbon fiber structure is protected, a self-assembled net-shaped conductive layer forms a stable conductive channel, the specific surface area is remarkably increased, a nitrogen-doped carbon shell is adopted to wrap metal nanodots to form an M-NC catalytic layer, and the specific surface area is remarkably increased. The catalyst layer is not easy to dissolve out, the capacity fading rate is obviously improved, the loading capacity of the catalyst layer on the reticular structure conducting layer with a larger specific surface area is larger, and meanwhile, the process is simple and low in cost.

The invention provides a multilayer circuit board and a processing method thereof, a chip system and electronic equipment, and the processing method comprises the steps: processing a second hole channel, a first conductive pattern and a second conductive pattern on a first substrate, and processing a third hole channel on a second substrate; the first substrate, the second substrate and the first insulating layer are stacked, pressed and fixed; the processing method further comprises the following steps: carrying out electroplating hole filling on the first substrate to form a second conductive channel; the processing method further comprises the steps that the second substrate is electroplated so that a sixth conductive pattern and a third conductive channel can be formed, the first insulating layer comprises a first conductive part, and the first conductive pattern, the second conductive pattern and the sixth conductive pattern are electrically connected with the second conductive channel through the third conductive channel and the first conductive part. The second hole channel and the third hole channel are filled in an electroplating hole filling mode, so that the wiring density and the chip signal transmission capability of the multilayer circuit board are improved, and the electrical performance and the thermal performance of the multilayer circuit board are improved; electroplating hole filling is suitable for mass production, and the process yield is stable.

The invention relates to the technical field of lithium secondary batteries, in particular to a negative electrode for a lithium secondary battery and the lithium secondary battery comprising the negative electrode, and the negative electrode comprises the following technical characteristics: a composite matrix structure: the negative electrode is composed of a multi-layer composite structure, and comprises (a) a conductive support layer, (b) a porous active material layer and (c) a surface functionalized coating. According to the invention, through the high porosity structure of the three-dimensional network metal matrix and the vertical conductive channel of the nanowire array, rapid transmission of lithium ions is realized, the interface resistance is reduced, and the rate capability is improved. And under a 10C high-rate condition, the capacity retention ratio of the negative electrode is still greater than or equal to 80%. The gradient pore structure design further optimizes a lithium ion diffusion path, and the diffusion rate of lithium ions is increased to # imgabs0 # by combining with a Poiseuille flow equation optimization parameter, so that polarization is effectively reduced, and the fast charging capacity of the electrode is improved.

The invention provides a photoelectric sensor packaging structure, a preparation method thereof and a camera module. The photoelectric sensor packaging structure comprises a substrate module, a light emitting unit and a light receiving unit. The substrate module comprises a substrate and is provided with a plurality of first channels and a plurality of second channels; the light emitting unit and the light receiving unit are arranged on the substrate, and the light receiving unit comprises a photosensitive area and a non-photosensitive area connected to the photosensitive area; the two ends of the first channel extend to the substrate and the non-photosensitive area respectively, a first conductive layer is arranged on the inner wall of the first channel to form a first hollow conductive channel, and the first hollow conductive channel is electrically connected to the substrate and the non-photosensitive area; the two ends of the second channel extend to the substrate and the light emitting unit respectively, a second conductive layer is arranged on the inner wall of the second channel to form a second hollow conductive channel, and the second hollow conductive channel is electrically connected to the substrate and the light emitting unit.

The invention discloses a silicon-based PHEMT epitaxial structure and a manufacturing method thereof, and belongs to the technical field of semiconductors, and the silicon-based PHEMT epitaxial structure comprises a silicon substrate, a GaAs buffer layer, an InGaAs channel layer, an AlGaAs spacer layer, an AlGaAs barrier layer, a passivation layer and a T-shaped gate which are sequentially laminated. Two sides of the passivation layer are respectively provided with a source electrode and a drain electrode, and the source electrode and the drain electrode are in contact with the n-doped AlGaAs barrier layer; the T-shaped grid electrode comprises grid electrode supporting columns and a grid root, and the grid electrode supporting columns are symmetrically arranged with the grid root as the axis; each gate support column is in contact with the passivation layer; a first distance between the gate heel and the drain electrode is greater than a second distance between the gate heel and the source electrode; the InGaAs channel layer and the AlGaAs barrier layer form a heterojunction, and two-dimensional electron gas used for providing a conductive channel is formed in the InGaAs channel layer under the polarization effect of the heterojunction.

The invention belongs to the technical field of lithium battery materials, and particularly relates to a preparation method of a polyvinylidene fluoride-hexafluoropropylene-based solid-state lithium battery, and the preparation method comprises the steps of preparing a composite solid electrolyte membrane and assembling the battery. Polyvinylidene fluoride hexafluoropropylene, lithium salt and nitrogen-methyl pyrrolidone are used as raw materials, and the plasticizer and the dendritic mesoporous nano silicon dioxide are added to prepare the composite solid electrolyte membrane, so that more conductive channels are provided for migration of lithium ions, and the electric capacity of the electrolyte is improved; according to the preparation method, the interface compatibility between the PVDF-HFP and the dendritic mesoporous nano silicon dioxide is improved, the electrochemical performance is improved, the crystallinity of the PVDF-HFP is reduced, and short circuit and explosion caused by the fact that dendritic crystals pierce the diaphragm are avoided; the invention solves the potential safety hazards caused by the traditional liquid electrolyte, such as leakage, combustion, explosion and the like, and has the advantages of simple preparation method and low cost, and is suitable for industrial large-scale production.

Aspects of the present disclosure include a battery measurement system having a plurality of capacitors, a plurality of probes each electrically coupled with a corresponding capacitor of the plurality of capacitors and a corresponding battery of a plurality of batteries, a controller configured to measure, via the plurality of probes, a plurality of voltages associated with the plurality of batteries in response to an interrogatory current, and a plurality of sense cables each associated with the corresponding battery of the plurality of batteries, wherein each sense cable of the plurality of sense cables is disposed across the corresponding battery such that the interrogatory current flows in a conduction channel in the corresponding battery in a first direction and in the corresponding cable in a second direction substantially opposite of the first direction.

The invention relates to a thin film solar cell module interconnection structure and a preparation method thereof. The preparation method comprises the following steps: 1) selecting a substrate to deposit a first electrode layer; (2) forming a P1 scribing line; 3) depositing a device functional layer; 4) forming a P2 scribing line; 5) depositing a second electrode layer; and (6) forming a P3 lineation line. On one hand, on the premise that the width of a dead zone is reduced, photon-generated carriers of a device function layer corresponding to P3 lineation have a certain probability under the drifting effect and can be collected, the photoelectric conversion performance of the assembly is further improved, the device function layer can form absorption, conductive channels between adjacent sub-cells are prevented from being broken, and the photoelectric conversion efficiency of the assembly is improved. Series resistance is reduced; on the other hand, on the basis of the formed paddle-tumbler, and the paddle-tumbler and the groove are communicated or separated by the second electrode layer, not only can the scratch edge be prevented from tilting to cause craters, but also the damage of the device layer can be controlled, and lattice defects near a dead zone can be eliminated, so that the open-circuit voltage and the fill factor can be improved.

The invention relates to a pole-mounted circuit breaker monitoring method and system, electronic equipment and a medium. The method comprises the following steps: acquiring a voltage recovery waveform characteristic and a mechanical vibration characteristic during operation of a vacuum arc-extinguishing chamber, and performing timestamp alignment; calculating a contact gap conductive channel risk value based on the aligned waveform characteristics; generating breaking capacity attenuation trend characteristics by combining the historical breaking current peak value, the breaking times and the risk value; calculating the remaining service life according to the trend characteristics, and synchronously obtaining a fault probability value according to the conductive channel risk value; and finally, according to the residual service life and the fault probability value, determining a maintenance early warning level and outputting a maintenance early warning signal. Therefore, according to the method, the risk of the conductive channel is evaluated through fusion of the operation waveform and the mechanical signal, and the breaking capacity attenuation trend is extrapolated along the historical breaking data, so that online evaluation and advanced early warning of the health state of the pole-mounted circuit breaker are realized, and the operation reliability and the operation and maintenance efficiency of the key node of the power distribution network are improved.

The invention discloses copper paste, an electrode and a preparation method and application of the electrode, the electrode comprises copper powder, the copper powder comprises nano-copper particles and flaky copper powder, the nano-copper particles comprise at least two connected copper nanoparticles, and the adjacent copper nanoparticles are connected in a surface contact mode. According to the electrode disclosed by the invention, the nano-copper particles formed by connecting more than two copper nano-particles are filled in the gap areas among the large-size flaky copper powder, so that the nano-copper particles are in direct contact with the flaky copper powder, conductive channels among the conductive particles are smoother, and the structure of the electrode is more compact due to the filling of the nano-copper particles; the bulk resistance of the electrode is greatly reduced and is equal to the conductivity of a silver electrode; the nano-copper particles can also be used as an auxiliary adhesive after being sintered and cured, so that the adhesive force between the copper grid line and the solar cell is improved, and the connection between the grid line and the solar cell is firmer.

The invention discloses a resistance-reducing grounding mechanism and an optimization method thereof.The resistance-reducing grounding mechanism comprises a grounding pile foundation, a grounding resistance-reducing cage, a grounding down lead and a corrugated external conductor wire, the grounding pile foundation is vertically buried underground, the grounding resistance-reducing cage wraps the grounding pile foundation in the horizontal dimension and the vertical dimension, and the grounding down lead is connected with the corrugated external conductor wire; the grounding down lead extends downwards from the ground to be connected to the grounding resistance reduction cage, and the corrugated external conductor wire is attached to the grounding resistance reduction cage. Therefore, the spatial three-dimensional wrapping design of the grounding resistance reduction cage can realize uniform diffusion in a larger range, the current diffusion capability of the grounding mechanism is improved, the external conductor wire with the corrugated structure increases the effective length and the surface area of the conductor, and the current diffusion capability of the grounding mechanism is further improved; and the grounding resistance reduction cage and the corrugated external conductor wire form a multi-layer conductive channel, so that the current discharge speed can be further increased, the grounding resistance value is reduced, and the transient overvoltage during lightning stroke is reduced, thereby ensuring the safe and stable operation of a power system.

The invention provides a phosphorus emitter passivation structure and a preparation method thereof, the passivation structure comprises a phosphorus emitter, the phosphorus emitter comprises silicon, phosphorus, hydrogen, carbon and / or nitrogen, the surface of the phosphorus emitter is provided with a nano silicon oxide layer, the phosphorus emitter comprises an electric injection region and a doped region, the electric injection region is provided with a conductive layer at a corresponding position, and the doped region is provided with a conductive layer at a corresponding position. The conductive layer is used for being connected with a metal electrode, a passivation anti-reflection layer is arranged at the corresponding position of the doped region, and the carbon and / or nitrogen concentration of the electric injection region is higher than that of the electric injection region. Partitioned passivation is performed on the surface of the phosphorus emitter, and carbon and / or nitrogen atoms are introduced into the doped region, so that the interface passivation effect is improved; the electric injection region is not subjected to carbon and nitrogen doping and is not provided with a passive film, so that the influence of passivation on the contact resistivity is reduced; a conductive channel is introduced into the electric injection region for electric injection, so that the defect state of the phosphorus emitter can be further eliminated, and the recombination current is reduced.

The invention discloses a preparation method of a single-crack sensor, and relates to the technical field of crack strain sensors, and the method comprises the following steps: 1, carrying out fluorination treatment on a silicon wafer in a closed container for 3 h to obtain a hydrophobic surface; 2, mixing the PMDS main agent and the curing agent according to the mass ratio of 10: 1, and then stirring the mixture by using a centrifugal mixer until the mixture is uniform; after the mixture is uniform, putting the mixture into a vacuum chamber to eliminate bubbles; carrying out spin coating on the fluorinated silicon wafer at a speed of 150r / min for 60s, and drying in a drying oven at 80 DEG C for 2h to obtain a PDMS film; 3, cutting the PDMS film into long strips with the length of 30mm and the width of 7mm, and attaching a pre-designed metal mask structure to the central position of the PDMS; according to the invention, by controlling a single crack in the conductive layer, cracks are prevented from being generated at other positions, the SWCNT conductive network on the crack provides a stable conductive channel, and the prepared crack strain sensor has better stability while maintaining high sensitivity.

The invention discloses an underwater communication equipment technology, and aims to provide a full-sea-depth antenna packaging assembly and a packaging method thereof.The full-sea-depth antenna packaging assembly is characterized in that the full-sea-depth antenna packaging assembly comprises a cabin penetrating part, an antenna unit, an antenna protection cover, a vulcanization coating layer and a sealing ring, and the full-sea-depth antenna packaging assembly is used for achieving stable transmission of signals in a deep sea environment; the antenna unit is used for transmitting and receiving electromagnetic wave signals; a conductive channel is arranged in the cabin penetrating piece and used for being electrically connected with the antenna unit so that electric signals inside and outside the cabin can penetrate through the cabin. The whole antenna protection cover is cylindrical, the end part of the antenna protection cover is in transition connection to form a hemispherical shape, and an antenna placement area is formed in the antenna protection cover; the vulcanized coating layer is coated on the peripheral side of the joint of the antenna protection cover and the cabin penetrating piece; the sealing ring is arranged between the antenna protection cover and the cabin penetrating piece and is of a metal-rubber composite structure. The invention is suitable for the technical field of underwater communication equipment.

A sensing device (100) for collecting a motion signal of a target object and a wearable device comprising the sensing device (100). The sensing device (100) comprises a first sensing unit (120) arranged on a first side face (110-a), facing a target object, of a flexible substrate (110). An electric signal generated by a first sensing unit (120) is conducted to a target position (A) through a first conductive channel (111) arranged on a flexible substrate (110), and the target position (A) is farther away from a target object relative to a first side face (110-a), so that the connection position of the sensing device (100) and an external circuit can be away from the first side face (110-a). The first side surface (110-a), facing the target object, of the sensing device (100) can be kept flat, and non-uniform deformation of the first sensing unit (120) of the first side surface (110-a) is avoided, so that the working stability of the sensing device (100) is improved. Meanwhile, the first side surface (110-a) is kept flat, so that the foreign body sensation when the sensing device (100) is worn can be reduced, and the wearing comfort of the sensing device (100) is improved.

The invention provides a 5KV high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal, and forming a drain metal layer; performing epitaxial growth to form a buffer layer and a drift layer; forming a barrier layer above the drift layer, and performing etching and ion implantation to form a P-type region; performing epitaxial growth to form an epitaxial layer; forming a barrier layer, etching, performing ion implantation, and forming a P + region, a P-type well region, an N-type region, a P-type shielding layer and an N-type source region; etching the epitaxial layer, the masking layer and the N-type region to form a groove and a lug boss, then oxidizing to form an insulating dielectric layer, and forming a trench in the insulating dielectric layer; depositing metal to form a gate metal layer; etching the N-type source region and the P + region, depositing metal to form a source metal layer, and removing the barrier layer to complete preparation; by constructing an L-shaped grid control structure, a multi-layer P-type protection structure from a drain electrode to a source electrode is formed, the source electrode and the grid electrode are protected, and the low-resistance characteristic of the device is ensured by double conductive channels.

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming an injection layer on the substrate; forming a buffer layer and a drift layer on the injection layer, and performing laser annealing on the buffer layer and the drift layer from one side away from the substrate; a plurality of conductive channel units arranged at intervals are formed on the upper surface layer of the drift layer, laser annealing is conducted on the conductive channel units from the side away from the substrate, and each conductive channel unit comprises a well region, an emitter region and a contact region, forming a gate structure above the well region; removing the substrate to expose the injection layer; laser annealing is carried out on the injection layer from the side, away from the buffer layer, of the injection layer, and laser wavelengths used in laser annealing of the buffer layer, the drift layer, the conductive channel unit and the injection layer are selected based on light absorption characteristic parameters of the injection layer, the buffer layer and the drift layer. According to the semiconductor structure and the preparation method thereof, the formation of parasitic capacitance is reduced, and the device performance is improved.

The utility model discloses an InCell glass electrostatic discharge assembly which comprises an InCell glass body and an FPC body, a CF layer is located on the upper portion of a glass face ITO layer, a CND ITO layer is arranged on the surface of the CF layer, the CND ITO layer is electrically connected with the glass face ITO layer, the glass face ITO layer is electrically connected with the FPC body, the FPC body comprises an FPC metal layer, and the FPC metal layer is arranged on the upper portion of the InCell glass body. One side of the stainless steel reinforcement is connected with the FPC metal layer in a bonding mode through the first conductive adhesive layer, and the other side of the stainless steel reinforcement is connected with the module iron frame in a bonding mode through the second conductive adhesive layer. After the FPC body is reversely folded, the module iron stand and the stainless steel reinforcement form an electric connection structure through the conductive adhesive. At the moment, once static electricity is generated on the CND ITO layer of the InCell glass body, the static electricity can quickly flow away from a conductive channel formed by the first conductive adhesive layer and the second conductive adhesive layer, so that the FPC body is prevented from being interfered by the static electricity, and the display effect is effectively improved.

The invention provides a porous silicon / carbon composite negative electrode material and a preparation method and application thereof.The preparation method comprises the steps that firstly, polyamide acid is evenly distributed in pore structures in porous silicon particles through a low-concentration polyamide acid solution dipping method, and a polyamide acid / porous silicon compound is obtained; mixing the polyamic acid / porous silicon compound with a high-concentration polyamic acid solution, coating the mixture on a substrate, and curing to obtain a polyimide / porous silicon compound composite membrane loaded on the substrate; then, polyimide inside and on the surfaces of the porous silicon particles is converted into graphene in situ by utilizing a laser-induced composite film, the porous silicon / carbon composite negative electrode material has a spatial three-dimensional network conductive channel structure, the cycle performance of a battery can be improved, the volume expansion of the battery can be reduced, and the performance of the battery can be improved. And the conductivity of the porous silicon / carbon composite negative electrode material can be remarkably improved, the resistance of a negative electrode diaphragm of a battery is greatly reduced, and the rate capability and the first coulombic efficiency of the battery are remarkably improved.

The invention relates to the technical field of lithium batteries, in particular to a conductive carbon fiber lithium iron manganese phosphate composite material and a preparation method. According to the method, conductive carbon fibers are prepared by adopting an electrostatic spinning method, and the conductive carbon fibers, a lithium source, a phosphorus source, an iron source and a manganese source are subjected to in-situ preparation through a solvothermal method to obtain the composite material. According to the method, the LMFP is modified by adopting a three-dimensional continuous conductive carbon fiber network, so that the problem that the electrochemical performance is greatly reduced due to agglomeration in the preparation process can be effectively solved; the lithium manganese iron phosphate directly grows in a conductive carbon grid in an in-situ synthesis mode to form gridding agglomeration, a conductive channel is provided for internal particles, and the composite material has good overall conductivity and is small in energy loss in the charging and discharging process.

The invention discloses a bidirectional high-voltage-resistant ESD (Electro-Static Discharge) protection device and an implementation method, relates to the technical field of chips, and aims to improve the bidirectional high-voltage-resistant capability of the ESD protection device. The ESD protection device comprises a semiconductor substrate and a heterojunction structure formed on the semiconductor substrate, a protection module is arranged on the heterojunction structure, the heterojunction structure comprises a first semiconductor layer and a second semiconductor layer, and a two-dimensional electron gas 2DEG conductive channel is formed at an interface of the heterojunction structure; the first semiconductor layer and the second semiconductor layer are both of a multi-stage stacked structure, and the first metal electrode and the second metal electrode are symmetrically distributed on the two sides of the heterojunction structure and are in ohmic contact with the 2DEG channel respectively; the P-type doped regions are located on the two sides of the heterojunction structure, and the composite passivation layer covers the heterojunction structure and the doped regions. According to the invention, the bidirectional high-voltage resistance of the ESD protection device is improved.

The invention relates to the photovoltaic field, and discloses a hot spot prevention structure of a back contact battery and a preparation method of the hot spot prevention structure. According to the hot spot prevention structure of the back contact battery, the boron-doped layer and the extended phosphorus-doped layer are disconnected through the gap; wherein the boron diffusion layer and the phosphorus diffusion layer can form a conductive channel, the conductive channel is located in the semi-silicon substrate and is formed by diffusing boron / phosphorus atoms into the silicon substrate and diffusing the boron / phosphorus atoms to the periphery, and the design can avoid generation of larger conduction electric leakage. According to the hot spot prevention structure of the back contact battery, the electric leakage loss can be effectively reduced on the basis of reducing the risk of generating a hot spot effect at the assembly end.

The invention discloses a cable assembly, and relates to the technical field of signal testing, the cable assembly comprises a shell, a rotating part, a first cable and a second cable, the shell is provided with a mounting cavity, at least part of the rotating part is arranged in the mounting cavity and can rotate relative to the shell, the rotating part penetrates through a conductive channel, and the outer surface of the rotating part comprises an arc-shaped surface; at least part of the first cable is located in the mounting cavity and located on one side of the rotating part, each of the first cable and the second cable comprises a coating layer and an inner conductor, and one end of the coating layer of the first cable is attached to the arc-shaped surface of the rotating part to drive the rotating part to rotate; at least part of the second cable is located in the mounting cavity and located on the other side of the rotating piece, and an inner conductor of the first cable and an inner conductor of the second cable stretch into the conductive channel and are in conductive connection. The bending service life of the cable assembly is long, the fault probability of the cable assembly can be reduced, and the test progress is guaranteed.

The present invention relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method for the semiconductor device. The semiconductor device comprises an epitaxial layer, a P-type ion implantation layer, an N-type ion implantation layer, a gate structure and a source structure. The manufacturing method comprises: forming the P-type ion implantation layer in the epitaxial layer; partially etching the P-type ion implantation layer to form a trench, a side wall area of the trench forming a cap layer structure; and then forming the N-type ion implantation layer in the P-type ion implantation layer, the N-type ion implantation layer being configured to be buried in the trench and to extend to the cap layer structure. Compared with the prior art, the present invention configures a first channel as a longitudinal conductive channel, so as to use the characteristic of high mobility of the longitudinal channel to increase turn-on current density in the case of a fixed size of unit cells, thereby achieving the purpose of improving performance. In addition, there is no need to use a trench type buried gate structure, achieving a simple process and being compatible with existing planar gate processes.

The invention relates to a low-voltage line emergency power supply non-inductive access system, which comprises a Rogowski coil sensor I, a Rogowski coil sensor II, an emergency power supply switching switch QF2, an emergency power supply non-inductive access auxiliary device, a puncture type wire clamp with an insulating handle and an overhead conductor, on the load side of a low-voltage line, a puncturing type wire clamp with an insulating handle directly penetrates through a wire insulating layer, and an overhead wire, an emergency power supply switching switch QF2 and an emergency power supply are electrically connected to establish a temporary conductive channel; the central processing unit compares whether the phase sequence, phase, voltage and frequency of the power grid main line are matched with those of the emergency power supply, if yes, the central processing unit outputs a signal to control an emergency power supply on / off switch QF2 to be switched on through a remote control output module, so that the emergency power supply supplies power to the load side of the low-voltage line; an emergency power supply grid-connected loop is formed on the premise of not interrupting power supply of a main line of a power grid, zero-power-failure access of the emergency power supply is achieved, access is rapid and convenient, and reliability is high.

The application provides a preparation method of a device based on electrostatic field induced microparticle patterning directional assembly, comprising the following steps: preparing a pre-patterning electrode and printing or depositing the pre-patterning electrode on a substrate to obtain a pre-patterning substrate; uniformly laying microparticles on a lower substrate and placing the pre-patterning substrate between the lower substrate and an upper substrate; forming a controllable electric field between the upper substrate and the lower substrate through corona discharge, and driving the microparticles to deposit on non-conductive areas of the pre-patterning substrate by electric field force to form a patterning conductive channel corresponding to the electrode; and packaging the substrate on which the patterning directional assembly is completed. The application realizes template-free, contact-free and solvent-free patterning directional assembly of microparticles, and has the advantages of simple process, low cost, high efficiency and strong universality. The application can be used to prepare multiple devices such as photoelectric detectors, pressure sensors and flexible electronics, and has important industrial application value.

The invention relates to the technical field of thermoelectric functional materials, in particular to an SWCNT / MBene composite thermoelectric thin film and a preparation method and application thereof. An acidified P-type doped one-dimensional SWCNT is used as a substrate, two-dimensional MBene is loaded, a one-dimensional / two-dimensional mixed structure is formed through hot pressing, and the thin film of a heterojunction structure is obtained. Wherein the one-dimensional SWCNT provides a good flexible skeleton and a conductive channel, the two-dimensional MBene nanosheet provides a Seebeck coefficient to enhance the thermoelectric conversion performance of the film, and the two-dimensional SWCNT and the two-dimensional MBene nanosheet cooperate to effectively balance the flexibility, the stability and the power factor of the thermoelectric film. Meanwhile, the preparation process is simple and controllable, large-scale production is easy, and damage to material performance and restriction on production efficiency by a complex process are avoided. The composite thermoelectric thin film is good in flexibility and excellent in performance, the preparation process is suitable for large-scale production, the composite thermoelectric thin film has wide application prospects in the fields of miniature thermoelectric power generation devices, flexible electronic temperature control devices and the like, and a new scheme is provided for practical application of high-performance thermoelectric materials.

The invention discloses a three-dimensional micro-LED chip with a novel heat dissipation structure and a dielectric layer manufacturing method. The chip comprises a silicon substrate, a red micro-led, a green micro-led and a blue micro-led, the silicon substrate, the red micro-led, the green micro-led and the blue micro-led are sequentially stacked, and a dielectric layer is arranged between any two of the silicon substrate, the red micro-led, the green micro-led and the blue micro-led; a plurality of copper-plated through holes are formed in the dielectric layer, and the conductive circuits of the red micro-LED, the green micro-LED and the blue micro-LED penetrate through the copper-plated through holes and then are connected with the silicon substrate; the method comprises the following steps: patterning a diamond film and plating copper on a through hole in manners of etching, electroplating and the like, so as to manufacture a light-transmitting and heat-conducting dielectric layer; through the stacking structure of the silicon substrate and the three-color micro-LEDs and the design of the copper-plated through holes in the dielectric layer, heat conduction and electric conduction channels are formed in the vertical direction, meanwhile, efficient heat dissipation and electrical isolation are achieved through the diamond film, the problems that in a traditional scheme, heat dissipation paths are insufficient, materials are contradicted, and the light emitting rate is reduced are solved, and the light emitting efficiency is improved. The LED lamp has the advantages of improving a vertical heat dissipation path, giving consideration to electrical isolation and thermal conductivity and improving light emitting efficiency.

The application provides a semiconductor device, a preparation method, a memory and an electronic device. The semiconductor device comprises: a first semiconductor structure, a first isolation layer and a second semiconductor structure which are sequentially stacked along a first direction; wherein the first direction is perpendicular to the first isolation layer; the first semiconductor structure comprises at least one first standard unit, each first standard unit comprises two sub-units, and each sub-unit comprises two first transistors; the second semiconductor structure comprises at least one second standard unit, each second standard unit comprises two second transistors; a power supply track is located between the two first transistors of each sub-unit, and the power supply track is connected with a first source-drain structure of the first transistor; and a conductive channel is located in the second semiconductor structure, a first end of the conductive channel is connected with a power supply metal structure in the second semiconductor structure, and a second end of the conductive channel extends along the first direction and is connected with the power supply track through the first isolation layer.

The present invention relates to the field of semiconductor field-effect transistors, and more specifically, to a MISFET with a bidirectional channel depletion and integrated diode. The device comprises an n-type gallium oxide substrate, an n-type gallium oxide epitaxial layer formed on the front surface of the n-type gallium oxide substrate, p-type semiconductor material layers formed in rows within and on the upper surface of the n-type gallium oxide epitaxial layer, and a gate electrode, a source electrode, and a drain electrode formed between or above the region between two rows of p-type semiconductor material layers. The portion of the p-type semiconductor material layer located within the n-type gallium oxide epitaxial layer has a multi-step structure, and the region of the p-type semiconductor material layer located between the upper surfaces of the n-type gallium oxide epitaxial layer serves as the gate region. Vertical conductive channels are formed on both sides of the gate region, and a horizontal conductive channel is formed between the vertical conductive channels. The thickness of the horizontal conductive channel is no greater than the height of the vertical conductive channel. The device is a junction enhancement type device capable of simultaneously achieving bidirectional channel depletion and an integrated diode.