30 results about "Control memory" patented technology

Embodiments of the present invention provide a memory operation method, a memory, an electronic device, and a storage medium. The memory operation method comprises: in response to detecting an error in a storage array of a memory during a working state of the memory, determining an error location of the error in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-package repair process, and on the basis of the error location, performing replacement of a target storage cell at the error location with a replacement storage cell in the storage array used for the post-package repair process; and after the post-package repair process, switching the memory back to the working state, and using the replacement storage cell to replace the target storage cell for operation. The memory operation method can improve the reliability of the memory.

The embodiments of the present application provide a memory device and a method for preforming a write operation in a memory device. The memory device comprising: a memory chip comprising a plurality of memory cells made at a first process node; and a control chip comprising a control circuit made at a second process node, wherein the first process node is more advanced than the second process node; wherein the control chip and the memory chip are bonded together to form the memory device, and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip.

An inspection apparatus includes: a memory; an image sensor configured to obtain a luminance image of the display apparatus comprising a plurality of pixels; and a processor configured to recognize a defective pixel based on the obtained luminance image, configured to recognize location information of the recognized defective pixel, and configured to control the memory to store the recognized location information of the defective pixel.

This disclosure relates to a controller for controlling a memory device and a method of operating the controller. The controller may include: a host interface adapted to acquire a write command received from a host; and a processor adapted to control a write operation of the memory device in response to the acquired write command, wherein, when the workload of the processor's background operations is greater than the workload of the host write operation, the host interface is further adapted to: determine a delay time amount, and provide the completion response to the host after delaying the write command by the delay time amount.

A memory module includes a memory device that includes a memory cell array including a fault block in which a fault cell is included and a remap block for replacing the fault block, and a controller that communicates with a host device through a compute express link (CXL) interface and to control the memory device. The controller may redundantly store recovery information including a fault flag and a remap address corresponding to the remap block in the memory device, may read data corresponding to a target address from the memory device, based on receiving a first, may identify whether the target address is the fault address, based on the data corresponding to the target address, and may generate a second request including the remap address based on the data corresponding to the target address, when it is determined that the target address is the fault address.

A semiconductor memory device includes a memory block including at least one programmed page and at least one erased page; and a control circuit configured to generate characteristic information for the memory block. The characteristic information includes information related to reliability of the memory block. The semiconductor memory device also includes a peripheral circuit configured to control an operation of the memory block based on the characteristic information. In another example, a semiconductor memory device includes: a memory block including at least one programmed page and at least one erased page; a control circuit configured to generate a block closed ratio (BCR) indicating a ratio of the at least one programmed page in the memory block to a total number of pages in the memory block; and a peripheral circuit configured to control an operation of the memory block based on the block closed ratio (BCR).

This invention belongs to the field of high-dimensional vector retrieval technology, specifically involving a method for constructing and retrieving high-dimensional vector indexes based on hierarchical heterogeneous storage. The method includes an index construction stage and a query retrieval stage. The index construction stage includes hierarchical configuration of the Hierarchical Navigation Small World Graph (HNSW), hierarchical heterogeneous storage, and neighbor rule construction. The query retrieval stage includes starting node selection, PQ algorithm candidate set pre-screening, LRU cache optimization, and binary serialization storage. The method is structured as "basic storage - pre-screening - intermediate acceleration - low-level parsing." Through the collaborative design of "hierarchical heterogeneous storage + multiple optimization mechanisms," this method significantly improves query throughput during retrieval while controlling memory overhead. It is suitable for AI applications in high-dimensional vector scenarios such as retrieval enhancement generation, personalized recommendation systems, and multimodal search, where there are strict requirements for memory usage, query throughput, retrieval recall, and dynamic update efficiency.

The application discloses a storage device and a data recovery method thereof. The storage device comprises a memory, a controller and a power supply. The controller comprises a first detection module, a retry module and a restart module. The first detection module is used for judging whether the memory is abnormal. The retry module is used for performing a predetermined number of retry operations. The restart module is used for controlling the memory to be powered off and powered on after a preset time. The memory completes the discharge operation within the preset time, so as to avoid the controller from repeatedly performing the retry operation and improve the service life of the memory.

Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes memories that store data received from a host device. The memory device includes a memory interface to the host device. The memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. An output of the neural network is stored in one of the memories. The memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. The memory device communicates with the host device over the memory interface using a DRAM bus protocol. This communication includes sending the output of the neural network to the host device.

This application discloses a text output method, apparatus, electronic device, and computer-readable storage medium. The method includes: obtaining a previous input lexical representation sequence and a previous output lexical; wherein the previous output lexical is generated based on the previous input lexical representation sequence, the previous input lexical representation sequence including encoded representations of several lexical elements, the several lexical elements including at least one anchor lexical and at least one scrolling lexical, and the previous input lexical representation sequence being generated based on user input text; adding the encoded representation of the previous output lexical to the previous input lexical representation sequence to obtain the current input lexical representation sequence; generating the current output lexical based on the current input lexical representation sequence; wherein the output lexical elements of each iteration are sequentially combined to form the output text sequence corresponding to the user input text sequence. Through the above method, this application can control memory overhead, thereby avoiding performance crashes caused by excessive memory consumption.

Embodiments of the present disclosure relate to adaptive word line underdrive control for in-memory compute operations. An in-memory compute circuit includes a memory array having SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates parallel word lines for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated in dependence on an integrated circuit process and / or temperature conditions in order to optimize word line underdrive performance and suppress unwanted memory cell data flips.

This invention provides a fast calculation method, apparatus, electronic device, and storage medium for the directed distance field from point cloud to STL mesh of blood vessel wall, belonging to the field of medical image processing. The method starts with the directed distance from a single point to the STL mesh of the blood vessel wall, transforming the calculation of the directed distance from a single point to the STL mesh into a binary tree traversal. The binary tree is constructed non-recursively, tree nodes are stored using a linear array, and the depth of the auxiliary stack is estimated, allowing the binary tree generated on the CPU to be directly sent to the GPU for use. When performing binary tree search on the GPU, the non-recursive traversal method strictly controls memory overhead. During threaded search, the GPU-side algorithm achieves near-linear scalability, greatly improving the calculation efficiency of the directed distance field from point cloud to STL mesh of blood vessel wall. This method can be widely used in medical image analysis and biomechanical calculations and analysis related to blood vessels.

Disclosed is an electronic device comprising: a memory including a volatile memory and a non-volatile memory, and for storing instructions; and at least one processor. The instructions may cause the electronic device to: detect a page fault indicating that data corresponding to a page requested to be read does not exist in the volatile memory; identify, on the basis of detecting the page fault, that the data corresponding to the page is stored in a first storage block in the non-volatile memory through a memory swap; determine whether a read operation for the first storage block is possible, on the basis of identifying that the data corresponding to the page is stored in the first storage block; obtain the data corresponding to the page from the non-volatile memory through the read operation for the first storage block on the basis of identifying that the read operation for the first storage block is possible; store the data corresponding to the page in the volatile memory; and put the read operation for the first storage block on standby until a previous read operation for the first storage block is completed, on the basis of identifying that the read operation for the first storage block is not possible.

The application relates to a learning method and device based on association rules and dynamic path planning, wherein the learning method based on association rules and dynamic path planning improves an existing neural network model through an LSTM and a gate mechanism, controls memory and forgetting, and prevents gradient explosion and gradient disappearance problems. Similarity and correlation between a current learner and a corresponding user group are calculated first, and then the similarity and correlation are used as prior data of the LSTM to optimally plan a learning path of the learner, and an optimal user learning path of the current learner is generated in combination with a knowledge graph. Since the gate mechanism is introduced, the influence of features before the current time on the next time state can be retained, the next learning state of the user is more accurate, long-time path prediction results are more accurate, and the obtained learning path is more perfect.

Memory devices, circuits, and methods for voltage control in memory devices are provided. One example method includes adjusting a rate of change of a reference voltage based on a step voltage and a step time duration, where adjusting the rate of change of the reference voltage includes changing the reference voltage by the step voltage over a time period that equals the step time duration. An output voltage from one or more charge pumps is generated using the reference voltage, where a ratio between the output voltage and the reference voltage is locked.

This application is directed to data protection in a memory system of an electronic device. The memory system has a first memory block and a second memory block, and each memory block includes one or more respective memory dies. Each memory die of the second memory block is distinct from the one or more respective memory dies of the first memory block. The electronic device stores user data including a plurality of user data items in the first memory block and integrity data including a plurality of integrity data items in the second memory block. Each of the plurality of user data items is configured to be validated based on a respective one of the plurality of integrity data items. The electronic device invalidates the integrity data in the second memory block, and reads the user data from the first memory block independently of the integrity data.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

A network interface controller (NIC) circuit may control data transfers between a network interface and a memory interface circuit. The NIC circuit receives data packets on the network interface and determines whether a packet type of a data packet corresponds to one of a first plurality of operations or a second plurality of operations. For data packets that correspond to one of the first plurality of operations, the NIC circuit controls the memory interface circuit according to the packet type and for data packets that correspond to one of the second plurality of operations, the NIC sends a notification to a processor circuit in the IC to execute software instructions to control the memory interface circuit according to the packet type. The NIC circuit quickly processes data packets corresponding to the first plurality of operations without software involvement but relies on software assistance for the second plurality of operations.

A processor includes a memory access controller that accesses a memory based on a memory access request, a storage that stores a plurality of limit values of an access bandwidth of the memory in association with a plurality of power consumption values of the memory, respectively, a power capping controller that acquires a limit value corresponding to a specified power consumption value from the storage and controls the memory access controller so that the access bandwidth is the acquired limit value or less, and an initial setting circuit that repeatedly accesses the memory during an initialization mode, monitors a power consumption value for a case where the access bandwidth is not limited and a plurality of the power consumption values when the limit value is gradually varied, and stores the plurality of limit values in the storage in association with the plurality of monitored power consumption values, respectively.

Control device that controls multiple loads by controlling multiple semiconductor switches corresponding to the respective loads, wherein the control device comprises: a receiving unit (1, 2) which receives a load control signal, which contains a signal indicating a control state of each load, from an external control device; a control storage unit (11) that stores the load control signal received by the receiving unit; a control unit (20) that controls the semiconductor switches according to the load control signal stored in the control memory unit; a procurement unit that procures a current control state, which is the control state of each load at a current time, or a current vehicle state; a determination storage unit (50) which stores a transition determination value for determining whether the load control signal received by the receiving unit is abnormal, wherein the transition determination value correlates with a control transition starting from the current control state or the current vehicle state; and a determination unit (30, 40) that compares a correlated control state of each of the loads, which correlates with the load control signal received by the receiving unit, with the transition determination value and determines that the load control signal received by the receiving unit is abnormal if the correlated control state and the transition determination value satisfy a predetermined corresponding relationship.

A memory device and a method for controlling a verification voltage of a memory device are provided. The method includes: determining a bit count of data bits verified in one verification cycle to be K according to electrical characteristics of a memory sector of the memory device, wherein K is a positive integer; controlling a charge pump circuit of the memory device to start detecting the verification voltage and start pulling up the verification voltage at a beginning time point of a present verification cycle of the memory sector; controlling the charge pump circuit to stop pulling up the verification voltage at a verification time point of the present verification cycle in response to the verification voltage reaching a predetermined level; and after the verification time point of the present verification cycle, using the verification voltage to verify K data bits written into the first memory sector.

Disclosed is an operation method of a controller which communicates with a plurality of memory devices. The method includes receiving a first reception signal, a second reception signal, and a data strobe signal, respectively, generating a first delay signal by performing first and second per-pin delay locked loop (ppDLL) operations on the first and second reception signals based on a rising edge of the data strobe signal, respectively, and generating first and second correction signals by performing first and second per-pin duty cycle correction (ppDCC) operations on the first and second delay signals based on a falling edge of the data strobe signal, respectively. Rising edges of the first and second correction signals are aligned with the rising edge of the data strobe signal, and first and second falling edges of the first correction signals are aligned with the falling edge of the data strobe signal.

There is a method of controlling a memory device. The method comprises acquiring a size of a PIM array provided to compute a convolution layer included in a deep neural network, a size of input data input to the convolution layer, and a size of a kernel filtering the input data; and determining a size of a parallel window such that a number of times of cycles of the PIM array for the convolution layer is minimized based on the size of the PIM array, the size of the input data, and the size of the kernel.

A memory module includes: a memory device comprising a memory cell array including a fault block comprising a faulty cell and a remapped block for replacing the faulty block; and a controller communicating with a host device and controlling the memory device via a compute fast link (CXL) interface. The controller may include fault flags and recovery information of remapped addresses corresponding to the remapped blocks redundantly stored in the memory device; may read data corresponding to a target address from the memory device based on receiving a first request; may identify whether the target address is a faulty address based on the data corresponding to the target address; and when the target address is determined to be a faulty address, may generate a second request including the remapped address based on the data corresponding to the target address.

Disclosed is an operation method of a memory controller controlling a memory device. The operation method includes loading raw data from the memory device, performing a 0th error correction operation on the raw data, generating first flip data by performing a first bit flip operation on the raw data based on a correction history table, when an error of the raw data is not corrected through the 0th error correction operation, and performing a first error correction operation on the first flip data, and the correction history table includes correction addresses indicating locations of one or more memory cells in the memory device, which are associated with previously corrected error bits.

This disclosure relates to a memory device and a controller for controlling the writing of data to and reading data from the memory of the memory device. The memory includes a plurality of memory structures, each memory structure including an array of memory cells configured to sequentially store data. The controller is configured to receive instructions to write data to or read data from a specific memory structure of the memory, wherein the instructions indicate the number of bits of data to be written or read. The controller is also configured to control the memory to write data to or read data from a specific memory structure, wherein in each clock cycle of one or more clock cycles, one bit of data is pushed into or pulled out of the specific memory structure.

The present disclosure provides an apparatus and method for controlling memory, an electronic device. The apparatus for controlling memory comprises: a bus interface module configured to receive a control signal for memory from a bus and transmit the control signal; a cross-clock domain module configured to perform cross-clock domain transmission on the control signal; a master controller module configured to count from when the memory is not selected to when the control signal is received by the master controller module through a counter, compare a count value of the counter with a minimum time value required for the memory from not being selected to being selected, and output an indication signal for selecting the memory based on a comparison result to start transmitting the control signal; and a memory transmission interface configured to transmit the control signal to the memory according to the indication signal. The apparatus can achieve greater optimization of control signal transmission delay.

Disclosed are a clock delay compensation circuit and a memory device including the same. The memory device includes: a memory cell array including a plurality of memory cells; a memory peripheral portion controlling the memory cell array; and the interface comprises a system clock signal receiver, a data clock signal receiver, a data signal receiver and a clock delay compensation circuit. The clock delay compensation circuit includes a clock driver including a plurality of cross-coupled latches and a four-phase clock generation circuit. The clock driver generates a second pair of differential clock signals using the first pair of differential clock signals. The four-phase clock generation circuit generates a plurality of phase clock signals using the second differential clock signal pair. At least one of the plurality of cross-coupled latches receives an external power supply voltage.