317 results about "Control memory" patented technology

Data storage systems are disclosed. In some implementations, a data storage device includes a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein the interface device includes a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device, and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller.

Storage devices and methods are disclosed. In an embodiment, a storage device may include a memory device including a plurality of memory units configured to store data and a plurality of page buffers coupled to the plurality of memory units, respectively, a volatile memory configured to store write data requested by a host, a power control device configured to control power supply to the memory device and the volatile memory and a processing circuit configured to control the memory device based on a command transmitted from the host. The processing circuit backs up the write data to a first page buffer among the plurality of page buffers in response to a low power mode entry command transmitted from the host. The power control device cuts off power supply to the volatile memory after the write data is backed up in the first page buffer.

There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

The invention discloses a processor supporting merging of memory access requests, a data memory access method, a medium and equipment. The processor supporting the merging of the memory access requests comprises a calculation circuit which is used for generating a plurality of memory access requests; the request merging circuit is used for determining respective request parameters of the plurality of memory access requests, and the request parameters are used for controlling memory access operation; based on the respective request parameters of the plurality of memory access requests, determining different memory access requests meeting a preset merging condition in the plurality of memory access requests; merging different memory access requests meeting a preset merging condition to obtain a merged memory access request; and the cache circuit is used for processing the merged memory access request so as to complete memory access operations corresponding to different memory access requests meeting a preset merging condition. According to the embodiment of the invention, the processing efficiency of the memory access request can be improved.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention discloses a tensor extension calculation method and device based on TPU, a medium and a product, and relates to the technical field of chips, and the method comprises the steps: analyzing a tensor extension request, and obtaining the first dimension information of an original tensor and the second dimension information of a target tensor; determining a tensor expansion demand according to the first dimension information and the second dimension information; according to the tensor expansion requirement, data, needing to be subjected to dimension expansion, in the original tensor is carried to a control memory or a vector memory from a high-bandwidth memory of the TPU, and in combination with a tensor broadcasting mechanism on the TPU, target tensor data is formed and stored in the high-bandwidth memory again through parallel processing of all the core computing units. According to the technical scheme of the embodiment of the invention, a tensor extension algorithm capable of accurately adapting to TPU hardware features is provided, so that the TPU native supports the extension calculation of the tensor dimension, the blank of the TPU function is filled, and the calculation parallelism and the transmission efficiency in the tensor extension calculation are improved.

There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

This disclosure describes approaches for sandboxing a thread and memory resources within non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: providing a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to establish a sandbox for a particular thread that executes in the non-secure processing environment and is associated with at least one specified memory region; and associating other threads of the non-secure processing environment with the secure processing environment, such that the particular thread is unable to access memory resources of the other threads while the particular thread is sandboxed.

A display device can include a display panel having a plurality of subpixels, a memory storing image control data for controlling an image displayed on the display panel, a mode control signal generation circuit generating a mode control signal based on a first mode signal supplied from a first controller, and a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal.

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

A semiconductor package includes a substrate, a platform die provided on the substrate, a memory die provided on the platform die, and a processor die provided on the platform die and provided adjacent to the memory die, wherein the platform die includes a memory controller configured to control data communication between the memory die and the processor die.

Examples of the present disclosure disclose a memory controller, a memory system and an operating method thereof, the memory controller includes a processor and a data buffer; the processor is configured to: control a memory device to sequentially write data into a buffer area of the memory device; and sequentially write the data in the buffer area into the storage area of the memory device; wherein the buffer area includes multiple first zones which include contiguous physical addresses and equal storage capacities, the first zone includes multiple first memory cells in which data is stored in a single-level mode; the storage area includes multiple second memory cells in which data is stored in a multi-level mode.

This disclosure describes approaches for securing memory among non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: configuring a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to lock a specified memory region of the computing device, with the specified memory region being associated with the non-secure processing environment; associating the specified memory region with the secure processing environment (e.g., by using a Security Attribution Unit to upgrade the region to secure memory); subsequently, identifying an access attempt to the specified memory region, with the access attempt being received from the non-secure processing environment; and controlling the access attempt to the specified memory region, based on a policy.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

Embodiments of the present invention provide a memory operation method, a memory, an electronic device, and a storage medium. The memory operation method comprises: in response to detecting an error in a storage array of a memory during a working state of the memory, determining an error location of the error in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-package repair process, and on the basis of the error location, performing replacement of a target storage cell at the error location with a replacement storage cell in the storage array used for the post-package repair process; and after the post-package repair process, switching the memory back to the working state, and using the replacement storage cell to replace the target storage cell for operation. The memory operation method can improve the reliability of the memory.

The embodiments of the present application provide a memory device and a method for preforming a write operation in a memory device. The memory device comprising: a memory chip comprising a plurality of memory cells made at a first process node; and a control chip comprising a control circuit made at a second process node, wherein the first process node is more advanced than the second process node; wherein the control chip and the memory chip are bonded together to form the memory device, and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip.

According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

A data storage device may include a memory device and a memory controller. The memory controller may allocate a system region. The memory controller may control the memory device to store system data in the system region without distinguishing between the plurality of memory regions in the system region based on a type of the system data. Therefore, the memory controller may randomly store the system data in the system region without allocating system region based on the type of system data.

A storage device for efficiently performing garbage collection may include a memory device including a plurality of zones corresponding to groups of consecutive logical addresses provided from a host device, the plurality of zones including a first zone and a second zone, and a memory controller for receiving a garbage collection request from the host device, and controlling, in response to the garbage collection request, the memory device to store, in the second zone, a plurality of valid data items stored in the first zone. The garbage collection request may include first identification information identifying the first zone, a plurality of first offset information items indicating positions at which the plurality of valid data items are stored in the first zone, second identification information identifying the second zone, and second offset information indicating positions at which the plurality of valid data items are to be stored in the second zone.

Disclosed is an electronic device that includes a memory device operating in a current frequency set point (FSP) operation mode among FSP operation modes and a system-on-chip (SoC) controlling the memory device. The memory device includes FSP mode register sets storing FSP data sets respectively corresponding to the FSP operation modes, and a temperature monitoring circuit monitoring a temperature range of the memory device. The SoC controls the current FSP operation mode based on a current operation frequency of the memory device and a current temperature range of the memory device. The FSP operation modes include a first FSP operation mode for an operation of the memory device at a first operation frequency and a first temperature range, and a second FSP operation mode for an operation of the memory device at the first operation frequency and a second temperature range higher than the first temperature range.

Memory controllers and memory systems including the same are disclosed. The memory controller is configured to control a memory module, the memory controller comprising: processing circuitry configured to: perform ECC decoding of a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome; determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome; and output a decode status flag indicative of the type of error.

Aspects of the technology described herein relate to apparatuses and methods for performing elevational beamforming of ultrasound data. Elevational beamforming may be implemented by different types of control circuitry. Certain control circuitry may be configured to control memory such that ultrasound data from different elevational channels is summed with stored ultrasound data in the memory that was collected at different times. Certain control circuitry may be configured to control a decimator to decimate ultrasound data from different elevational channels with different phases. Certain control circuitry may be configured to control direct digital synthesis circuitry to add a different phase offset to complex signals generated by the DDS circuitry for multiplying with ultrasound data from different elevational channels.

There is provided an apparatus having an exposure head including K light-emitting chips arranged along a rotation axis of a photosensitive body. Light-emitting elements to form a latent image are arranged in each light-emitting chip. The apparatus includes: a dividing unit that divides image data into K pieces of partial image data for the K light-emitting chips that are temporarily stored in memory resources; and a control unit that controls output of the K pieces of partial image data from the memory resources to the K light-emitting chips. The control unit controls allocation of the memory resources to the K light-emitting chips based on information indicating which ones of odd-numbered and even-numbered light-emitting chips of the K light-emitting chips are arranged on downstream side with respect to the photosensitive body which rotates.

Embodiments of the present disclosure relate to a circuit for generating and trimming stages of memory cell read operations. A read signal generator generates a read signal to control a read operation of a memory array. The read signal generator may be selectively controlled to generate an oscillating signal having a period corresponding to a characteristic of the read signal. The oscillation signal is passed to a frequency divider that divides the oscillation signal and supplies the divided oscillation signal to an output pad. The frequency of the oscillating signal may be measured at the output pad. The frequency of the oscillating signal may be calculated as a function of the frequency of the oscillating signal, and the duration of the signal characteristic read. The read signal characteristics may then be adjusted as required.

A semiconductor package includes: a substrate; a platform die disposed on the substrate; a memory die disposed on the platform die; and a processor die disposed on the platform die and disposed adjacent to the memory die, where the platform die includes a memory controller configured to control data communication between the memory die and the processor die.

A system, apparatus, and method for protecting coherent memory content in a coherent data processing network by filtering data access requests and snoop responses based on read / write (R / W) access permissions. Requests are augmented with access permissions in a memory protection unit, and the access permissions are used to control memory accesses by master nodes of the network.

An inspection apparatus includes: a memory; an image sensor configured to obtain a luminance image of the display apparatus comprising a plurality of pixels; and a processor configured to recognize a defective pixel based on the obtained luminance image, configured to recognize location information of the recognized defective pixel, and configured to control the memory to store the recognized location information of the defective pixel.

This disclosure relates to an electronic device. According to the present technology, a storage device includes: a memory device configured to include memory cells for storing data and circuitry configured to generate voltage information indicating whether a voltage for performing an operation on the memory cells is within a preset voltage range; and a memory controller communicating with the memory device and configured to transmit a status command to the memory device requesting a status response indicating a state of operation, and to control the memory device to change the voltage for performing the operation based on the status response provided from the memory device and including voltage information.

Methods for input / output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.