504 results about "Control memory" patented technology

A system, method and apparatus to control memory devices over computer networks. For example, a server system establishes a secure authenticated connection with a client computer system. Over the connection, the server receives from the client computer system a request identifying a memory device and determine, based on data stored in the server system, that the client computer system is eligible to control the memory device. In response to a request from the client computer system, the server system generates a digital signature for a command using at least a cryptographic key stored in the server system in association with the memory device. The client computer system receives the digital signature from the server system and submits the command with the digital signature to the memory device. The memory device validates the digital signature prior to execution of the command.

The invention discloses a memory operation method, a memory, electronic equipment and a storage medium. The memory operation method comprises the following steps: in response to an error detected in a memory array of the memory in a working state of the memory, determining an error position of the error in the memory array; after the memory enters the idle state, the memory is controlled to start a post-package repair process, and according to the error position, a target memory unit at the error position is replaced with a replacement memory unit used for the post-package repair process in the memory array; and after the post-package repair process, the memory is switched back to the working state, and the replacement memory unit is used for replacing the target memory unit for operation. The memory operation method can improve the reliability of the memory.

The present disclosure provides a memory device and a control method for the memory device. The memory device includes a memory array and a control logic circuit. The memory array includes memory cell rows. The control logic circuit comprises a counter and a reset circuit. The counter counts the number of accesses performed on the memory cell rows to generate a count value corresponding to the memory cell row accessed among the memory cell rows, and sets the count value to a random value when the count value is equal to a predetermined value and when the accesses are performed. The reset circuit resets the count value to a predetermined value in response to a refresh command. When the count value reaches a threshold value, the control logic circuit arranges a memory cell row near the accessed memory cell row into a mitigation operation.

Data storage systems are disclosed. In some implementations, a data storage device includes a controller coupled to a plurality of memory devices to control memory operations of the plurality of memory devices, and including M communication lanes, and an interface device configured to include N communication lanes to be connected to a host device that includes N communication lanes and to the M communication lanes of the controller, wherein the interface device includes a connector configured to connect the N communication lanes of the host device to the N communication lanes of the interface device, and a selector configured to, in response to a host port type identification signal received from the host device, selectively activate M communication lanes of the interface device, out of the N communication lanes of the interface device, to transmit or receive the data to or from the M communication lanes of the controller.

A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes a plurality of memory cell rows. The control logic circuit perform an access on the memory array. The control logic circuit counts a number of the access performed on the memory cell rows to generate a plurality of count values corresponding to the memory cell rows. When a count value corresponding to an accessed memory cell row among the memory cell rows is larger than or equal to a threshold value generated with random number corresponding to the accessed memory cell row, the control logic circuit arranges the memory cell rows nearby the accessed memory cell row into a mitigation operation.

A method of operating a memory device including a memory cell array and a memory circuit includes receiving a first command from a controller, determining, in response to the first command, whether first device information stored in the memory circuit has an error, receiving, in response to the determining that the first device information has the error, a reset command from the controller, and performing a refresh operation on the memory circuit in response to the reset command. The first device information includes information about an operation parameter and an operating frequency of the memory device.

Storage devices and methods are disclosed. In an embodiment, a storage device may include a memory device including a plurality of memory units configured to store data and a plurality of page buffers coupled to the plurality of memory units, respectively, a volatile memory configured to store write data requested by a host, a power control device configured to control power supply to the memory device and the volatile memory and a processing circuit configured to control the memory device based on a command transmitted from the host. The processing circuit backs up the write data to a first page buffer among the plurality of page buffers in response to a low power mode entry command transmitted from the host. The power control device cuts off power supply to the volatile memory after the write data is backed up in the first page buffer.

There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

The invention discloses a processor supporting merging of memory access requests, a data memory access method, a medium and equipment. The processor supporting the merging of the memory access requests comprises a calculation circuit which is used for generating a plurality of memory access requests; the request merging circuit is used for determining respective request parameters of the plurality of memory access requests, and the request parameters are used for controlling memory access operation; based on the respective request parameters of the plurality of memory access requests, determining different memory access requests meeting a preset merging condition in the plurality of memory access requests; merging different memory access requests meeting a preset merging condition to obtain a merged memory access request; and the cache circuit is used for processing the merged memory access request so as to complete memory access operations corresponding to different memory access requests meeting a preset merging condition. According to the embodiment of the invention, the processing efficiency of the memory access request can be improved.

An operating method may include; communicating maximum power information from the memory system to the host, communicating power table information and battery information from the host to the memory system in response to the maximum power information, and controlling power consumption by a component of the memory system in response to a maximum consumption power value, wherein each of the power table information and the battery information is related to a battery associated with the memory system and operating in accordance with battery steps, the power table information includes a number of entries including a first entry related to a first battery step among the battery steps and associated with a first maximum consumption power value, and a second entry related to a second battery step among the battery steps and associated with a second maximum consumption power value.

A memory built-in self-test (BIST) controller, corresponding to a partition BIST controller, is configured to control memory testing in one or more corresponding static random access memories (RAMs) and has a first corresponding register configured to store a failure indicator for each of the one or more corresponding RAMs and a second corresponding register configured to store an uncorrectable failure indicator for each of the one or more corresponding RAMs. The partition BIST controller is configured to generate, based on the first and second registers of the MBIST controller, a first in-field test status indicator which indicates whether a failure occurred during memory testing of any RAM corresponding to the partition BIST controller and a second in-field test status indicator which indicates whether an uncorrectable failure occurred during the memory testing of any RAM corresponding to the partition BIST controller.

The invention discloses a tensor extension calculation method and device based on TPU, a medium and a product, and relates to the technical field of chips, and the method comprises the steps: analyzing a tensor extension request, and obtaining the first dimension information of an original tensor and the second dimension information of a target tensor; determining a tensor expansion demand according to the first dimension information and the second dimension information; according to the tensor expansion requirement, data, needing to be subjected to dimension expansion, in the original tensor is carried to a control memory or a vector memory from a high-bandwidth memory of the TPU, and in combination with a tensor broadcasting mechanism on the TPU, target tensor data is formed and stored in the high-bandwidth memory again through parallel processing of all the core computing units. According to the technical scheme of the embodiment of the invention, a tensor extension algorithm capable of accurately adapting to TPU hardware features is provided, so that the TPU native supports the extension calculation of the tensor dimension, the blank of the TPU function is filled, and the calculation parallelism and the transmission efficiency in the tensor extension calculation are improved.

There is provided a Cluster Controller, CC, configured to control memory access by a cluster of multiple processing units or processing elements, PEs, to a common Cluster Memory, CM, shared by the processing elements within the cluster. The Cluster Controller is configured to receive requests, referred to as cluster broadcast requests, from at least a subset of the multiple processing elements within the cluster for broadcasting of data from the common cluster memory to said at least a subset of the multiple processing elements. The Cluster Controller is configured to initiate broadcasting of data in response to the received cluster broadcast requests only after broadcast requests have been received from all processing elements of said at least a subset of said multiple processing elements that are participating in the broadcast.

This disclosure describes approaches for sandboxing a thread and memory resources within non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: providing a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to establish a sandbox for a particular thread that executes in the non-secure processing environment and is associated with at least one specified memory region; and associating other threads of the non-secure processing environment with the secure processing environment, such that the particular thread is unable to access memory resources of the other threads while the particular thread is sandboxed.

A display device can include a display panel having a plurality of subpixels, a memory storing image control data for controlling an image displayed on the display panel, a mode control signal generation circuit generating a mode control signal based on a first mode signal supplied from a first controller, and a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal.

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

Provided herein may be an electronic device and a method of operating the same. The electronic device may include a memory device including a replay protected memory block (RPMB) configured to store security data, a memory controller configured to control the memory device, and a host device configured to verify, using a password, an external device coupled thereto wherein the memory controller controls the memory device to read, when the external device is verified, the security data, and wherein the host device is further configured to encrypt the read security data, and transmit, to the verified external device, the encrypted security data, a decryption key for decrypting the encrypted security data, and an RPMB key for accessing the security data.

A semiconductor package includes a substrate, a platform die provided on the substrate, a memory die provided on the platform die, and a processor die provided on the platform die and provided adjacent to the memory die, wherein the platform die includes a memory controller configured to control data communication between the memory die and the processor die.

Examples of the present disclosure disclose a memory controller, a memory system and an operating method thereof, the memory controller includes a processor and a data buffer; the processor is configured to: control a memory device to sequentially write data into a buffer area of the memory device; and sequentially write the data in the buffer area into the storage area of the memory device; wherein the buffer area includes multiple first zones which include contiguous physical addresses and equal storage capacities, the first zone includes multiple first memory cells in which data is stored in a single-level mode; the storage area includes multiple second memory cells in which data is stored in a multi-level mode.

This disclosure describes approaches for securing memory among non-secure / secure processing environments such as in a TrustZone-M processor architecture. An example method of controlling memory access includes: configuring a memory locking service in a computing device having a secure processing environment and a non-secure processing environment, and executing the memory locking service in the secure processing environment; receiving a request with the memory locking service to lock a specified memory region of the computing device, with the specified memory region being associated with the non-secure processing environment; associating the specified memory region with the secure processing environment (e.g., by using a Security Attribution Unit to upgrade the region to secure memory); subsequently, identifying an access attempt to the specified memory region, with the access attempt being received from the non-secure processing environment; and controlling the access attempt to the specified memory region, based on a policy.

Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

A transmission device transmits signals between a server and an opposing device. The transmission device includes a memory and includes a controller that controls a first queue and a second queue in the server and controls the memory. When detecting issuance of a processing request from the server to the opposing device, the controller queues the processing request in the first queue, obtains the data from the server according to the processing request, and stores the obtained data in the memory. After requesting the transfer of the data and the processing request to the opposing device, before executing the processing request in the opposing device, the controller queues the processing completion of the processing in the second queue and releases the queue of the processing completion.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, an integrated circuit (IC) base die is disclosed. The IC base die is configured to couple to a stack of memory die and includes a first port including a die-to-die (D2D) interface to couple to an IC device. A second port includes a memory interface to access a memory other than the stack of memory die. Memory control circuitry controls memory access operations directed to the memory other than the stack of memory die.

The invention provides a key value storage system. The key value storage system comprises a data pre-reading module, a cache management module and an index adjustment module. And the data pre-reading module is used for predicting the data blocks which can be accessed in the preset time period and loading the data blocks to the cache in advance so as to reduce reading delay and disk I / O (Input / Output) operation, so that the reading efficiency is improved. The cache management module is used for monitoring the running state of the key value storage system in real time and dynamically adjusting the cache space based on the running state, it is ensured that the cache meets the high hit rate, memory use can be reasonably controlled, resource waste is avoided, and the reading performance and the response speed are further improved. The index adjusting module is used for dynamically adjusting an index structure according to the access frequency of the key value pair, reducing disk I / O operation during reading, improving the searching speed and reducing the searching cost. Therefore, according to the key value storage system, the negative influence caused by read amplification can be reduced, the response speed of the system is improved, and faster and more efficient data access experience is provided for a user.

Embodiments of the present invention provide a memory operation method, a memory, an electronic device, and a storage medium. The memory operation method comprises: in response to detecting an error in a storage array of a memory during a working state of the memory, determining an error location of the error in the storage array; after the memory enters an idle state, controlling the memory to initiate a post-package repair process, and on the basis of the error location, performing replacement of a target storage cell at the error location with a replacement storage cell in the storage array used for the post-package repair process; and after the post-package repair process, switching the memory back to the working state, and using the replacement storage cell to replace the target storage cell for operation. The memory operation method can improve the reliability of the memory.

The memory controller may detect degradation based on a bit error rate (BER) of a resistive memory device including a memory cell. The memory controller may control the memory cell to be programmed to a first resistance state, read the programmed memory cell, and receive the BER of the memory cell generated during the read operation from the resistive memory device. The memory controller may determine the number of programming loops for the memory cell based on the BER. The number may be determined based on reference to a lookup table indicating a correlation between the BER and the number of programming loops.

The embodiments of the present application provide a memory device and a method for preforming a write operation in a memory device. The memory device comprising: a memory chip comprising a plurality of memory cells made at a first process node; and a control chip comprising a control circuit made at a second process node, wherein the first process node is more advanced than the second process node; wherein the control chip and the memory chip are bonded together to form the memory device, and the control circuit is configured to control an operation of the plurality of the memory cells in the memory chip.

According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

A data storage device may include a memory device and a memory controller. The memory controller may allocate a system region. The memory controller may control the memory device to store system data in the system region without distinguishing between the plurality of memory regions in the system region based on a type of the system data. Therefore, the memory controller may randomly store the system data in the system region without allocating system region based on the type of system data.