50 results about "Remote memory access" patented technology

The present disclosure relates to systems and methods remote memory access between systems. In particular, some implementations relate to remote memory access using data processing units that can reduce loads on central processing units or other system components. Some implementations utilize scheduling algorithms to optimize memory transfers. Some implementations relate to data processing unit hardware that includes programmable logic, which can be configured for scheduling, data processing, and the like.

Methods, apparatus, and systems for adaptive collaborative memory with the assistance of programmable networking devices. Under one example, the programmable networking device is a switch that is deployed in a system or cluster of servers comprising a plurality of nodes. The switch selects one or more nodes to be remote memory server nodes and allocate one or more portions of memory on those nodes to be used as remote memory for one or more remote memory client nodes. The switch receives memory access request messages originating from remote memory client nodes containing indicia identifying memory to be accessed, determines which remote memory server node is to be used for servicing a given memory access request, and sends a memory access request message containing indicia identifying memory to be accessed to the remote memory server node that is determined. The switch also facilitates return of messages containing remote memory access responses to the client nodes.

The invention discloses a separated memory-oriented page migration method and system, and belongs to the field of data storage. The page migration method comprises the following steps that: a node dynamically samples the access condition of a page through NUMA Balancing, tracks and marks the access record of the page; static screening is carried out in combination with an LRU list, hot pages are obtained through identification, and other pages are marked as cold pages; storing the identified hot pages and cold pages in a hot to-be-migrated queue and a cold to-be-migrated queue respectively; the background kernel thread continuously obtains to-be-migrated hot pages and cold pages from the hot to-be-migrated queue and the cold to-be-migrated queue, asynchronous page migration is conducted, the hot pages are migrated to the node from the far-end memory node, and the cold pages of the node are migrated to the far-end memory node; when the page is migrated, the access of the user to the page is decoupled. Preferentially migrating a real high-frequency access page to a local memory node; the hit rate of local memory access is improved, and the delay of remote memory access is reduced.

The invention relates to the technical field of server resource scheduling, in particular to a server virtualization integration system and method. The method comprises the following steps: executing a multi-dimensional reference pressure test on each NUMA node in a physical server cluster to generate physical node performance data; monitoring a virtual machine cache event of a tenant virtual machine in real time by utilizing the virtualization management platform, and determining tenant load snapshot data; evaluating the matching degree between the remote memory access demand of the virtual machine and the node localization supply capability according to the tenant load snapshot data, determining an optimal host migration target, and starting real-time migration of the virtual machine by the virtualization management platform to obtain a server migration integration process; and monitoring an abnormal state after migration in real time according to a server migration integration process so as to realize secondary forced scheduling integration request processing. According to the method, the optimal matching between the virtual machine and the physical node in the server is realized, the resource utilization efficiency is improved, and the cross-NUMA access overhead is reduced.

The invention discloses a method, a device and a system for realizing remote memory access based on Ethernet, electronic equipment and a medium. The method comprises the following steps of: packaging a message generated by an application layer in a transmission layer by using a source port number field, a destination port number field and an RDMA basic transmission message header; the message header of the message in the network layer comprises a source IP address field, a destination IP address field, a service type field, a total length field and a protocol field, and the service type field, the total length field and the protocol field are used for representing the priority of a frame, the length of the frame and an upper layer protocol respectively; and the message uses a source IP address field and a destination IP address field to replace a source MAC address field and a destination MAC address field respectively for addressing in a data link layer. The communication overhead can be reduced, and the communication performance can be improved.

The present invention discloses a method, device, equipment and medium for remote memory access based on network messages, which relates to the field of communication technology, and solves the technical problem that the transmission logic of existing RDMA devices is complex and data needs to be copied to realize data transmission. The key points of its technical solution are to only configure the mapping table of the MAC header information of the data and the destination address, and then obtain the MAC header information corresponding to the data destination address; the data destination address and its corresponding MAC header information and data information are packaged and sent to the receiving device, and the receiving device outputs the data information to the data destination address after receiving. The implementation is simpler and the cost is lower. Compared with the existing RDMA method, the processing logic is reduced; zero copy, reducing the bus traffic bandwidth, the sending device directly receives the data transmitted by the third-party component, and adds the MAC header information and destination address information based on the data, and no data copy is required during the message packaging process.

The present invention relates to video coding technology, and discloses a video coding optimization method and system. A video coding optimization method is applied to a NUMA architecture, and the method includes: detecting the CPU hardware of a server, and obtaining the total number of CPU nodes and the logical cores included in the CPU nodes, where the total number of CPU nodes is M; creating coding threads, and allocating the original frame memory and the reconstructed frame memory according to the number of CPU nodes; encoding the video on an encoder according to the gop id of the current video frame; for the encoded video outputting a video bitstream, and sequentially splicing the bitstreams into a complete bitstream according to the display order of I frames in the bitstream from low to high. The present invention improves the coding parallelism while avoiding remote memory access existing in conventional software coding, and at the same time reduces the consumption of computing resources by the encoder.

The application relates to a chip parallel communication system. The system comprises a plurality of nodes, each node comprising a GMAC unit, and a processor unit, an MC unit and a NIC unit connected to the GMAC unit; the GMAC unit is configured to, in response to receiving an access request, transmit a first remote memory access request to the NIC unit and a second remote memory access request to the MC unit; the NIC unit is configured to transmit the first remote memory access request to a corresponding external node; the MC unit is configured to read or write data from a memory coupled to the MC unit according to at least one of a local memory access request and the second remote memory access request, and in the case of reading out data, transmit the read-out data to a corresponding processor unit through the GMAC unit; by configuring the GMAC unit and the processor unit, the MC unit and the NIC unit connected to the GMAC unit, the application reduces the communication delay between the nodes, thereby improving the data volume communication parallel computing performance, and improving the system performance and efficiency.

The invention relates to a method, a computing device, a computer readable storage medium and a computer program product for direct remote memory access of a graphics processor. The method comprises the following steps: respectively obtaining page granularity of a to-be-communicated source equipment memory and a to-be-communicated target equipment memory; in response to the determined page granularity of the predetermined size of at least one unaligned PCIE in the source equipment memory and the target equipment memory, constructing a virtual address space mapped with a physical address space with the page granularity of the predetermined size based on the physical address space of the unaligned memories of the equipment, the mapped virtual address space meets the requirements of the PCIE page table; and based on the constructed virtual address space, performing communication between memories of the source device and the target device in a direct remote memory access mode. According to the invention, an additional physical memory aligned with the memory page does not need to be configured as an intermediate cache, the memory calling operation can be simplified, and the transmission delay is remarkably reduced.

The invention relates to a topology adaptive optimization method and device based on NPU training features, and a storage medium. The method comprises the steps of collecting all hardware devices and connection modes thereof on the topology adaptive optimization device based on the NPU training features; collecting and analyzing communication characteristics among the devices in a preset collection period; dynamically optimizing a link topological relation among the devices based on communication characteristics among the devices; obtaining a high-frequency communication link and a low-frequency communication link based on the communication characteristics among the devices, and respectively configuring multiple levels of caches; and repeating the execution steps, and dynamically optimizing the link topological relation and the multi-level cache mode between the devices. According to the invention, through adaptive optimization, the communication efficiency between devices under different training tasks is improved; dynamically adapting to the optimal topological structure; the delay of remote memory access is reduced, and the training speed is improved.

The application provides a NUMA system page cache copy management method and system. The application first generates a read-only copy page in the local memory of an access node through the linkage of target file page cache identification, access subject NUMA node information acquisition and policy copy judgment, thereby avoiding cross-node remote memory access. Then, in combination with local copy priority mapping and page fault triggered by unmapping when process node scheduling is changed, the dynamic adaptation of process scheduling behavior and page mapping relationship is realized. Finally, in the read page fault interrupt process, the page mapping update is completed based on the copy strategy, and the association relationship between the node and the access task is recorded. Without damaging the file page cache semantics, the remote access overhead of the multi-NUMA node system file page cache can be greatly reduced, the problem of continuous remote access caused by process node drift can be solved, and the overall file access performance and running stability in the concurrent scenario can be significantly improved.

The present application relates to a method for direct remote memory access of a graphics processor, a computing device, a computer readable storage medium and a computer program product. The method comprises: obtaining page granularity of source device memory and target device memory to be communicated respectively; in response to determining that at least one of the source device memory and the target device memory is not aligned to a predetermined size page granularity of PCIE, constructing a virtual address space mapped to a physical address space of the device unaligned memory at the predetermined size page granularity, so that the mapped virtual address space meets the requirements of a PCIE page table; and communicating between the memories of the source device and the target device in a direct remote memory access manner based on the constructed virtual address space. The present application can avoid configuring additional memory page aligned physical memory as an intermediate cache, and can simplify memory call operations, and significantly reduce transmission delay.

The embodiment of the invention discloses a memory access optimization method and device, electronic equipment, a storage medium and a program.The method comprises the steps that memory access data of an application program are dynamically monitored in real time, and remote memory access data of the application program are determined according to the memory access data of the application program; under the condition of determining that the remote memory access data of the application program meets the memory exchange condition, determining a target exchange local memory from local memories; determining a target exchange remote memory according to the remote memory access data of the application program; and performing memory exchange processing on the target exchange local memory and the target exchange remote memory. According to the technical scheme provided by the embodiment of the invention, efficient management of the memory can be realized in a high-memory-demand use scene, and memory access delay is reduced, so that the memory access efficiency is improved, and the overall performance of the system is improved.

The application discloses an MCM-GPU adaptive last-level cache structure arranged in a GPU module, comprising a Tag Array and a Date Array, wherein the Date Array is used for storing data, and the Tag Array is used for checking whether the data corresponding to an address is in the cache; the application further comprises a local memory access queue used for storing a memory access request of the current GPU module, a remote memory access queue used for storing a memory access request of other GPU modules, an LLC architecture change flag register used for storing an LLC architecture change flag indicating whether the architecture organization mode of the current last-level cache needs to be changed, and an LLC architecture flag register used for storing an LLC architecture flag indicating whether the current last-level cache is switched to a private last-level cache design or a shared last-level cache design. The application can support the dynamic switching of the shared last-level cache and the private last-level cache, can adaptively select the last-level cache architecture organization mode according to the configuration during program running, can meet the program memory access requirement, and can improve the performance of the MCM-GPU.

Disclosed herein are a method and apparatus for migrating a virtual machine in a memory-disaggregated environment. The method for migrating a virtual machine in a memory-disaggregated environment includes determining whether to migrate a virtual machine based on a number of accesses to a remote memory, establishing a migration policy for the virtual machine based on a remote memory access pattern, and determining a migration destination node based on the migration policy, wherein the migration policy includes a first migration policy corresponding to a case where the remote memory access pattern is sequential, and a second migration policy corresponding to a case where the remote memory access pattern is non-sequential.

The application relates to a method and system for improving the speed of writing shared main memory critical resources in parallel by a new generation Shenwei many-core processor, which comprises the following steps: a slave core applies for a data space on its private local data memory; critical resource data in the main memory is copied to the respective private local data memory; each slave core performs read-write operation; each slave core initiates a reduction operation through a remote memory access (RMA) channel, wherein the reduction operation refers to performing certain aggregation function operation on the critical resource data in the private local data memory of the plurality of slave cores to obtain a final result; and the critical resource data in the private local data memory after the reduction operation is written back to the main memory through a direct memory access (DMA) channel. The method can effectively improve the speed of reading and writing the shared main memory critical resources by the slave core of the Shenwei many-core processor, and improve the performance and efficiency of the supercomputer.

The present application provides a method for constructing a remote memory access protection mechanism, a remote memory node, and a device. The method includes: obtaining a permission application from a computing node, wherein the permission application is generated based on the computing node submitting an access request from a user program to a network card queue pair, and the access request includes a remote memory address; if the permission application is authenticated, the memory window is bound to the remote memory address, and a permission symbol is returned, which is used for remote memory access; if the remote memory access ends, the memory window is unbound from the remote memory address to invalidate the permission symbol. In this way, the permission mechanism can be used to effectively isolate illegal remote access from user programs, and the permission symbol becomes invalid after the access ends, effectively avoiding potential problems such as remote data corruption and remote data privacy leakage faced by the remote memory architecture.

The invention discloses a server-free remote memory access performance optimization method based on cross-process memory tracking, and belongs to the technical field of computer memory management. The method comprises the following steps: designing a memory state table as a unified perception layer for remote memory access of homologous server-free containers, and realizing cross-process tracking of memory page states among different containers; a memory state table query process is embedded into hardware page table traversal, page state query is completed by hardware acceleration, and extra overhead on a memory access key path is eliminated; the remote memory access is merged and optimized based on the memory state table, cached local memory pages are reused in the container creation stage, the same remote memory access requests are merged in the operation stage, and the page missing exception frequency and the network bandwidth contention are reduced. According to the method, extra overhead caused by remote memory access in a server-free environment is effectively reduced, page missing abnormity and network bandwidth contention in a concurrent scene are greatly reduced, and the running performance and the system expandability of memory-intensive server-free applications are remarkably improved.

The embodiment of the invention discloses a network controller, electronic equipment, a computer network system and a remote access method, relates to the technical field of integrated computers, and can effectively simplify the access operation of a processor on a remote memory. The network controller comprises a semantic conversion module which is configured to convert a memory access request into a network access request under network semantics under the condition that a processor initiates the memory access request to a first memory address; wherein the first memory address is an address within a first address range in physical memory addresses of first equipment; and the control module is electrically connected with the semantic conversion module and is configured to send the network access request to the second equipment, so that the memory access request acts on a memory buffer area corresponding to a second memory address of the second equipment through the network access request, and the memory buffer area corresponds to the second memory address of the second equipment. The second memory address is located in the second address range. The method is suitable for remote memory access.

The invention relates to the technical field of remote memory access, in particular to a selective confirmation-based data packet out-of-order recovery method, which comprises the following steps of: when a data packet is received, judging whether a hole region exists in a bitmap, whether the hole region is a newly generated hole region and whether all hole regions can be cleared; and feeding back a selective acknowledgement message or an acknowledgement response frame according to a judgment result. In order to solve the problem that the RoCE in the prior art needs to repeatedly transmit subsequent data packets for multiple times in the retransmission process, in the embodiment, the data packets needing to be retransmitted are indicated on the receiving end side in a bitmap maintenance mode. In the process of receiving the data packets, filling is sequentially carried out according to the received serial numbers of the data packets, the holes needing to be retransmitted are indicated, the sending end retransmits the specific data packets according to the fed back hole information, the backspacing process does not need to be completely executed, and therefore the transmission efficiency is improved.

A network interface card (NIC) receives a stream of commands, a respective command comprising memory-operation requests, each request associated with a destination NIC. The NIC buffers asynchronously the requests into queues based on the destination NIC, each queue specific to a corresponding destination NIC. When first queue requests reach a threshold, the NIC aggregates the first queue requests into a first packet and sends the first packet to the destination NIC. The NIC receives a plurality of packets, a second packet comprising memory-operation requests, each request associated with a same destination NIC and a destination core. The NIC buffers asynchronously the requests of the second packet into queues based on the destination core, each queue specific to a corresponding destination core. When second queue requests reach the threshold, the NIC aggregates the second queue requests into a third packet and sends the third packet to the destination core.

The present invention relates to the field of computer technology, and particularly to a method for running the DeePMD-kit model on the Shenwei supercomputer. Six core groups CG of the Shenwei supercomputer are respectively responsible for the inference of six sub-regions of MPI processes. Each core group CG includes an MPE and 64 CPEs. The MPE contains a 256-bit SIMD unit; each CPE contains a 512-bit SIMD unit; each CPE contains a local data memory, and each local data memory LDM realizes continuous data transmission with the main memory through the DMA strategy; data transmission between CPEs in the same core group CG is realized through remote memory access RMA; the inference method of each core group CG is as follows: time-consuming operators are accelerated by SACA, and the MPE distributes the computationally intensive part of the time-consuming operators to 64 CPEs; after the calculation is completed, the MPE synchronizes the calculation results of the 64 CPEs and stores the results in the main memory; SIMD parallelism during the operation of SACA: 512-bit vectorized instructions are issued by the CPE. Through the above technical solution, the present invention has the advantage of enabling the DeePMD-kit model to be applied on the Shenwei computer.

The present invention relates to the technical field of communications. Disclosed is a smart network interface controller unloading-based remote memory system, comprising a computing node, a smart network interface controller and a memory node. The computing node sends a remote memory access request to the smart network interface controller; the smart network interface controller is used for analyzing the remote memory access request and accessing the memory node; the memory node is used for initializing and storing a remote memory. The smart network interface controller comprises a remote memory request processing module, a data address management module and an RDMA communication frontend; the memory node comprises an RDMA communication backend; the use stage of the remote memory system comprises an initialization stage, an application registration stage and an operation stage. The present invention unloads the management unit overhead originally on the memory node to the smart network interface controller, thus achieving in-network management of the remote memory; in addition, the memory node is only responsible for providing the memory, and is completely unaware of remote memory access by applications, thereby effectively reducing the computational management overhead of a CPU on the memory node.

The present disclosure relates to aggregating small remote memory access requests. A network interface card (NIC) receives a stream of commands, respective commands including memory operation requests, each request associated with a destination NIC. The NIC asynchronously buffers the requests into queues based on the destination NIC, each queue specific to a corresponding destination NIC. When a first queue of requests reaches a threshold, the NIC aggregates the first queue of requests into a first packet and sends the first packet to the destination NIC. The NIC receives a plurality of packets, a second packet including memory operation requests, each request associated with a same destination NIC and a destination core. The NIC asynchronously buffers the requests of the second packet into queues based on the destination core, each queue specific to a corresponding destination core. When a second queue of requests reaches a threshold, the NIC aggregates the second queue of requests into a third packet and sends the third packet to the destination core.

The application discloses a memory allocation method and an electronic device, and relates to the technical field of computers, which comprises the following steps: identifying semantic information of an object, dynamically binding the semantic information with a cache area and a memory allocation strategy, improving the flexibility of cache replacement, and realizing differentiated management and control of cache resources. The selection of the memory access node is optimized by fusing remote delay, shared domain characteristics and the semantic information of the object. The management of the L3 cache area, the memory pool and the memory access node in the related art is in an independent optimization state. Through semantic-driven partition binding and cross-node decision-making, the cache hit rate is improved and the delay of cross-node memory access is reduced. The problems of low cache replacement flexibility, low cache utilization and high remote memory access delay are solved.

The invention discloses a memory allocation method and electronic equipment, and relates to the technical field of computers, which comprises the following steps of: dynamically binding semantic information with a cache region and a memory allocation strategy by identifying the semantic information of an object, so that the flexibility of cache replacement is improved, and differential management and control of cache resources are realized. Remote delay, shared domain characteristics and semantic information of objects are fused, and selection of memory access nodes is optimized. And the condition that management of the L3 cache region, the memory pool and the memory access node is in an independent optimization state in related technologies is avoided. Through semantic-driven partition binding and cross-node decision, the cache hit rate is improved, and the delay of cross-node memory access is reduced. The problems of low cache replacement flexibility, low cache utilization rate and high remote memory access delay are solved.

A system for providing memory access is disclosed. In some embodiments, the system is configured to receive at a source server fabric adapter (SFA), from a server, a memory access request comprising a virtual memory address; using associative mapping, determining whether the virtual address corresponds to a source-local memory associated with the source SFA or to a remote memory. If the virtual address corresponds to the source-local memory, the virtual memory address is translated, at the source SFA, into a physical memory address of the source-local memory. If the virtual address corresponds to the remote memory, a request message is synthesized, and the synthesized request message is transmitted to the destination SFA using a network protocol.

Disclosed in the present application are a method, apparatus and system for implementing remote memory access on the basis of Ethernet, and an electronic device and a medium. The method comprises the following steps: at a transport layer, using a source port number field, a destination port number field and an RDMA base transport header to encapsulate a packet generated by an application layer; enabling a packet header of the packet at a network layer to comprise a source IP address field, a destination IP address field, a type of service field, a total length field and a protocol field, wherein the type of service field, the total length field and the protocol field are used for representing a frame priority, a frame length and an upper-layer protocol, respectively; and at a data link layer, using the source IP address field and the destination IP address field to replace a source MAC address field and a destination MAC address field, respectively, so as to address the packet. The present application can reduce communication overheads and improve the communication performance.

This invention relates to the field of electronic digital data processing technology and discloses an AI-based intelligent computing operating system for energy and carbon data. The system includes an energy and carbon tensor management module, a bypass scheduling module, and a mapping processing module. The energy and carbon tensor management module allocates a non-paged, continuous physical space in memory to store time-series energy consumption data streams. The bypass scheduling module acquires the server's memory access topology graph and identifies the local memory nodes corresponding to different cores. The mapping processing module extracts topology boundary nodes based on the computational topology correlation matrix and generates kernel-state topology boundary cut sets. The operating system implements physical mirror multi-projection mapping based on the topology graph and cut sets, establishing redirection paths to convert remote memory access into local addressing access. This invention eliminates hardware cache consistency probe signals through a mirroring mechanism, solving the memory access latency bottleneck in large-scale graph computation and ensuring computational determinism.

A data processing apparatus includes one or more cache configuration data stores, a coherence manager, and a shared cache. The coherence manager is configured to track and maintain coherency of cache lines accessed by local caching agents and one or more remote caching agents. The cache lines include local cache lines accessed from a local memory region and remote cache lines accessed from a remote memory region. The shared cache is configured to store local cache lines in a first partition and to store remote cache lines in a second partition. The sizes of the first and second partitions are determined based on values in the one or more cache configuration data stores and may or not overlap. The cache configuration data stores may be programmable by a user or dynamically programmed in response to local memory and remote memory access patterns.